dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28482 1 T1 17 T2 2 T3 18



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 24977 1 T1 17 T3 18 T4 34
auto[ADC_CTRL_FILTER_COND_OUT] 3505 1 T2 2 T5 27 T11 12



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22203 1 T3 18 T4 34 T5 16
auto[1] 6279 1 T1 17 T2 2 T5 22



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24412 1 T1 17 T2 2 T3 18
auto[1] 4070 1 T4 16 T5 15 T11 2



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 46 1 T181 10 T272 13 T275 11
values[0] 115 1 T5 22 T109 22 T171 7
values[1] 665 1 T41 1 T115 8 T128 5
values[2] 752 1 T14 14 T72 1 T114 32
values[3] 624 1 T4 25 T14 19 T30 2
values[4] 739 1 T11 12 T14 16 T114 19
values[5] 3038 1 T8 6 T13 22 T40 4
values[6] 913 1 T2 2 T116 1 T128 5
values[7] 485 1 T4 9 T30 7 T153 2
values[8] 543 1 T5 16 T12 10 T13 26
values[9] 1275 1 T1 17 T11 2 T12 10
minimum 19287 1 T3 18 T6 20 T7 178



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 1043 1 T5 22 T114 32 T41 1
values[1] 597 1 T14 33 T72 1 T34 4
values[2] 563 1 T4 25 T30 2 T72 1
values[3] 3205 1 T11 12 T14 16 T73 17
values[4] 694 1 T8 6 T40 4 T16 31
values[5] 844 1 T2 2 T13 22 T153 2
values[6] 519 1 T4 9 T5 5 T30 7
values[7] 535 1 T5 11 T12 10 T13 26
values[8] 966 1 T30 13 T16 15 T48 27
values[9] 227 1 T1 17 T11 2 T12 10
minimum 19289 1 T3 18 T6 20 T7 178



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24296 1 T1 1 T2 2 T3 18
auto[1] 4186 1 T1 16 T4 16 T5 20



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2


Uncovered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 281 1 T114 15 T41 1 T128 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 283 1 T5 12 T115 8 T185 5
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T14 14 T72 1 T34 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T14 19 T127 2 T128 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T4 12 T110 1 T132 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T30 1 T72 1 T34 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1666 1 T14 16 T73 2 T113 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 306 1 T11 10 T114 20 T16 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T8 6 T40 4 T16 8
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 209 1 T108 13 T124 1 T133 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 244 1 T13 11 T147 9 T36 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 243 1 T2 2 T153 1 T116 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T4 6 T30 3 T187 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T5 5 T49 1 T166 11
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T5 6 T12 10 T40 5
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T13 15 T178 14 T38 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 266 1 T30 13 T108 23 T123 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 273 1 T16 8 T48 16 T159 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T1 17 T11 2 T12 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 11 1 T34 3 T181 1 T17 4
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 19143 1 T3 18 T6 20 T7 178
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T276 1 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 205 1 T114 17 T128 4 T109 12
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 274 1 T5 10 T185 2 T17 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T34 1 T179 16 T120 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T127 22 T128 5 T109 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T4 13 T110 3 T156 16
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T30 1 T48 1 T179 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 983 1 T73 15 T113 21 T137 23
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 250 1 T11 2 T114 16 T16 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T16 23 T177 9 T171 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T183 21 T168 1 T20 3
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T13 11 T147 10 T36 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T153 1 T190 13 T177 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 104 1 T4 3 T30 4 T172 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T166 9 T127 2 T122 21
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T5 5 T33 4 T173 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T13 11 T178 9 T38 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T120 10 T277 5 T278 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T16 7 T48 11 T119 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 55 1 T206 7 T237 10 T259 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T34 1 T181 9 T17 5
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 145 1 T33 1 T16 1 T34 1



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 13 1 T272 13 - - - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T181 1 T275 11 T279 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 11 1 T109 10 T171 1 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 43 1 T5 12 T192 1 T250 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 225 1 T41 1 T128 1 T160 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T115 8 T185 5 T17 5
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T14 14 T72 1 T114 15
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T34 1 T127 1 T109 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T4 12 T159 1 T110 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T14 19 T30 1 T72 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T14 16 T155 1 T123 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 299 1 T11 10 T114 12 T16 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1712 1 T8 6 T13 11 T40 4
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T114 8 T108 13 T125 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 229 1 T123 1 T112 3 T38 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 255 1 T2 2 T116 1 T128 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T4 6 T30 3 T147 9
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T153 1 T49 1 T166 11
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T5 6 T12 10 T40 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T5 5 T13 15 T178 14
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 435 1 T1 17 T11 2 T12 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 294 1 T16 8 T34 3 T48 16
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 19142 1 T3 18 T6 20 T7 178
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 18 1 T181 9 T279 9 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 18 1 T109 12 T171 6 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 43 1 T5 10 T192 14 T277 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T128 4 T131 14 T184 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T185 2 T17 2 T81 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T114 17 T34 1 T179 16
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T127 11 T109 10 T118 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T4 13 T110 3 T156 16
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T30 1 T48 1 T35 3
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 108 1 T155 2 T179 11 T119 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T11 2 T114 7 T16 4
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1019 1 T13 11 T73 15 T113 21
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T114 9 T125 13 T183 21
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 239 1 T38 1 T177 9 T171 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T128 4 T190 13 T177 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 71 1 T4 3 T30 4 T147 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T153 1 T166 9 T127 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 98 1 T5 5 T173 11 T49 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T13 11 T178 9 T38 3
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 315 1 T33 4 T120 10 T206 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T16 7 T34 1 T48 11
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 145 1 T33 1 T16 1 T34 1



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 258 1 T114 18 T41 1 T128 5
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 334 1 T5 11 T115 1 T185 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T14 1 T72 1 T34 4
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T14 1 T127 24 T128 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T4 14 T110 4 T132 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T30 2 T72 1 T34 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1333 1 T14 1 T73 17 T113 24
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 304 1 T11 7 T114 18 T16 6
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 224 1 T8 1 T40 1 T16 25
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T108 1 T124 1 T133 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T13 12 T147 11 T36 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T2 2 T153 2 T116 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 140 1 T4 4 T30 5 T187 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T5 1 T49 1 T166 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T5 6 T12 1 T40 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 149 1 T13 12 T178 10 T38 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 269 1 T30 1 T108 2 T123 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 265 1 T16 8 T48 12 T159 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 73 1 T1 1 T11 2 T12 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 23 1 T34 3 T181 10 T17 7
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 19288 1 T3 18 T6 20 T7 178
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T276 1 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T114 14 T109 9 T131 12
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T5 11 T115 7 T185 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T14 13 T31 3 T184 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 110 1 T14 18 T109 10 T138 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 106 1 T4 11 T132 2 T156 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 107 1 T111 18 T203 11 T191 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1316 1 T14 15 T129 34 T130 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 252 1 T11 5 T114 18 T16 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T8 5 T40 3 T16 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T108 12 T183 17 T216 18
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T13 10 T147 8 T36 5
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T190 15 T177 10 T156 14
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 87 1 T4 5 T30 2 T205 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 100 1 T5 4 T166 10 T122 15
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 105 1 T5 5 T12 9 T40 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T13 14 T178 13 T125 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T30 12 T108 21 T219 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T16 7 T48 15 T39 3
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T1 16 T12 9 T111 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 4 1 T34 1 T17 2 T212 1



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T272 1 - - - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 21 1 T181 10 T275 1 T279 10
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 20 1 T109 13 T171 7 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 49 1 T5 11 T192 15 T250 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T41 1 T128 5 T160 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T115 1 T185 3 T17 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T14 1 T72 1 T114 18
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 258 1 T34 1 T127 12 T109 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 182 1 T4 14 T159 1 T110 4
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T14 1 T30 2 T72 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T14 1 T155 3 T123 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 277 1 T11 7 T114 8 T16 6
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1372 1 T8 1 T13 12 T40 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T114 10 T108 1 T125 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 276 1 T123 1 T112 1 T38 2
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 238 1 T2 2 T116 1 T128 5
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 106 1 T4 4 T30 5 T147 11
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T153 2 T49 1 T166 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T5 6 T12 1 T40 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T5 1 T13 12 T178 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 396 1 T1 1 T11 2 T12 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 294 1 T16 8 T34 3 T48 12
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 19287 1 T3 18 T6 20 T7 178
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 12 1 T272 12 - - - -
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 12 1 T275 10 T279 2 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 9 1 T109 9 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 37 1 T5 11 T250 10 T277 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T131 12 T184 14 T18 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T115 7 T185 4 T17 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T14 13 T114 14 T31 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T109 10 T148 19 T149 16
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T4 11 T156 4 T184 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T14 18 T35 1 T111 18
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 79 1 T14 15 T132 2 T264 3
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 242 1 T11 5 T114 11 T16 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1359 1 T8 5 T13 10 T40 3
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T114 7 T108 12 T125 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T112 2 T38 2 T177 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T190 15 T177 10 T156 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 91 1 T4 5 T30 2 T147 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T166 10 T122 15 T191 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 107 1 T5 5 T12 9 T40 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T5 4 T13 14 T178 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 354 1 T1 16 T12 9 T30 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T16 7 T34 1 T48 15



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 24296 1 T1 1 T2 2 T3 18
auto[1] auto[0] 4186 1 T1 16 T4 16 T5 20

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%