Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25225

1

T1

17

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3257

1

T2

1

T4

25

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22551

1

T1

17

T3

18

T4

9

auto[1]

5931

1

T2

2

T4

25

T8

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T280	1		T281	5		-	-
values[0]	97	1			T203	12		T171	13		T133	1
values[1]	689	1			T11	2		T72	1		T34	4
values[2]	574	1			T1	17		T5	11		T40	4
values[3]	591	1			T40	5		T33	13		T16	7
values[4]	3026	1			T4	9		T5	22		T8	6
values[5]	970	1			T114	17		T48	27		T119	5
values[6]	694	1			T2	1		T4	25		T16	31
values[7]	646	1			T5	5		T72	1		T49	9
values[8]	868	1			T49	9		T155	3		T147	19
values[9]	1034	1			T2	1		T12	10		T13	48
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T11	2		T72	1		T34	4
values[1]	492	1			T1	17		T5	11		T40	9
values[2]	665	1			T8	6		T11	12		T12	10
values[3]	3136	1			T4	9		T5	22		T30	7
values[4]	852	1			T114	17		T16	31		T178	23
values[5]	709	1			T2	1		T4	25		T72	1
values[6]	809	1			T36	14		T116	1		T108	23
values[7]	618	1			T5	5		T49	10		T155	3
values[8]	775	1			T2	1		T13	26		T14	30
values[9]	203	1			T12	10		T13	22		T116	1
minimum	19341	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T34	3		T112	15		T17	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	2		T72	1		T115	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	17		T5	6		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T40	4		T33	9		T16	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	6		T12	10		T14	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	10		T114	15		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T4	6		T30	3		T73	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	12		T34	1		T48	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T178	14		T117	1		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T114	8		T16	8		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	1		T72	1		T127	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	12		T49	9		T109	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T116	1		T108	9		T109	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T36	8		T108	14		T111	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	5		T49	5		T147	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	1		T155	1		T189	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T13	15		T14	30		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	1		T30	1		T114	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T13	11		T116	1		T111	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T12	10		T108	13		T122	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19167	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T203	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	1		T17	2		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T179	11		T171	12		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	5		T16	4		T185	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T33	4		T16	7		T122	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T190	13		T182	8		T191	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	2		T114	17		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T4	3		T30	4		T73	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	10		T48	11		T192	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T178	9		T156	14		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T114	9		T16	23		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T127	13		T37	1		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	13		T109	12		T265	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T109	10		T185	11		T179	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	6		T131	14		T179	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	4		T147	10		T110	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T155	2		T189	11		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	11		T153	1		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	1		T114	7		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	11		T156	16		T206	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T122	14		T171	6		T282	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	1		T16	1		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T281	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T227	2		T197	13		T200	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T203	12		T171	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T34	3		T112	15		T17	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	2		T72	1		T115	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	17		T5	6		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	4		T16	8		T122	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	5		T16	3		T115	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T33	9		T166	11		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1662	1			T4	6		T8	6		T12	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	12		T11	10		T114	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T119	1		T17	4		T156	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T114	8		T48	16		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T178	14		T127	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	12		T16	8		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	5		T72	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	9		T111	19		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T49	5		T147	9		T109	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T155	1		T108	14		T189	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	26		T14	30		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	1		T12	10		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T281	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T197	13		T200	11		T283	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T171	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	1		T17	2		T262	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	10		T180	4		T170	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	5		T185	2		T190	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T16	7		T122	7		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	4		T171	3		T119	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T33	4		T166	9		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T4	3		T30	4		T73	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	10		T11	2		T114	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T119	4		T17	5		T156	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T114	9		T48	11		T192	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T178	9		T127	13		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	13		T16	23		T36	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T110	3		T179	16		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	14		T181	9		T193	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T49	4		T147	10		T109	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T155	2		T189	11		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	22		T153	1		T128	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	1		T114	7		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	4		T112	1		T17	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	2		T72	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T5	6		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T40	1		T33	10		T16	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T12	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	7		T114	18		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T4	4		T30	5		T73	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	11		T34	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T178	10		T117	1		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T114	10		T16	25		T192	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	1		T72	1		T127	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	14		T49	1		T109	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T116	1		T108	1		T109	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	9		T108	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T49	5		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T49	1		T155	3		T189	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	12		T14	2		T153	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T30	2		T114	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T13	12		T116	1		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T12	1		T108	1		T122	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19306	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T203	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T112	14		T17	1		T216	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T115	7		T132	15		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	16		T5	5		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T40	3		T33	3		T16	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	5		T12	9		T14	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	5		T114	14		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T4	5		T30	2		T129	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	11		T48	15		T184	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T178	13		T156	14		T184	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T114	7		T16	6		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	1		T177	9		T216	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	11		T49	8		T109	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T108	8		T109	10		T112	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T36	5		T108	13		T111	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	4		T49	4		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T189	17		T125	11		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	14		T14	28		T177	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T114	11		T34	1		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T13	10		T111	4		T156	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T12	9		T108	12		T122	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T200	18		T283	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T203	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T281	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T227	2		T197	14		T200	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T203	1		T171	13		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T34	4		T112	1		T17	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	2		T72	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T5	6		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	1		T16	8		T122	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	1		T16	6		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T33	10		T166	10		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T4	4		T8	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	11		T11	7		T114	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T119	5		T17	7		T156	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T114	10		T48	12		T192	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T178	10		T127	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T4	14		T16	25		T36	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	1		T72	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T49	1		T111	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T49	5		T147	11		T109	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T155	3		T108	1		T189	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T13	24		T14	2		T153	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T12	1		T30	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T197	12		T200	18		T283	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T203	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T112	14		T17	1		T215	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	7		T132	15		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	16		T5	5		T185	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T40	3		T16	7		T122	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	4		T16	1		T115	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T33	3		T166	10		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T4	5		T8	5		T12	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	11		T11	5		T114	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T17	2		T156	14		T184	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T114	7		T48	15		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T178	13		T37	1		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	11		T16	6		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	4		T108	8		T112	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T49	8		T111	18		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	4		T147	8		T109	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T108	13		T189	17		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T13	24		T14	28		T111	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	9		T114	11		T34	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20