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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.51


Total test records in report: 917
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T796 /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3887119512 May 12 04:10:23 PM PDT 24 May 12 04:19:15 PM PDT 24 213191863162 ps
T797 /workspace/coverage/default/48.adc_ctrl_filters_both.902144353 May 12 04:14:24 PM PDT 24 May 12 04:17:48 PM PDT 24 350181846932 ps
T87 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4156592229 May 12 04:08:47 PM PDT 24 May 12 04:08:49 PM PDT 24 583942954 ps
T45 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1178326177 May 12 04:08:40 PM PDT 24 May 12 04:08:43 PM PDT 24 499953909 ps
T50 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1345464158 May 12 04:08:50 PM PDT 24 May 12 04:09:02 PM PDT 24 4383658612 ps
T46 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1759246295 May 12 04:08:41 PM PDT 24 May 12 04:08:54 PM PDT 24 5352956627 ps
T53 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1891451798 May 12 04:08:56 PM PDT 24 May 12 04:09:01 PM PDT 24 655183713 ps
T798 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3170194697 May 12 04:09:00 PM PDT 24 May 12 04:09:03 PM PDT 24 528728683 ps
T799 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.900082214 May 12 04:09:08 PM PDT 24 May 12 04:09:10 PM PDT 24 398705166 ps
T800 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.838658013 May 12 04:08:57 PM PDT 24 May 12 04:09:00 PM PDT 24 308976523 ps
T801 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.266239757 May 12 04:08:36 PM PDT 24 May 12 04:08:37 PM PDT 24 524811016 ps
T88 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3677590585 May 12 04:08:47 PM PDT 24 May 12 04:08:49 PM PDT 24 427541443 ps
T47 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.306087854 May 12 04:08:52 PM PDT 24 May 12 04:08:54 PM PDT 24 2242921064 ps
T802 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2009361869 May 12 04:08:57 PM PDT 24 May 12 04:08:59 PM PDT 24 474819744 ps
T803 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.98253788 May 12 04:09:02 PM PDT 24 May 12 04:09:04 PM PDT 24 516141968 ps
T804 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.504292624 May 12 04:09:09 PM PDT 24 May 12 04:09:11 PM PDT 24 325075703 ps
T89 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1484336799 May 12 04:08:56 PM PDT 24 May 12 04:09:00 PM PDT 24 465536721 ps
T107 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2220577038 May 12 04:08:41 PM PDT 24 May 12 04:08:44 PM PDT 24 954877742 ps
T54 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1053670754 May 12 04:09:02 PM PDT 24 May 12 04:09:04 PM PDT 24 349791796 ps
T103 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4187729219 May 12 04:08:49 PM PDT 24 May 12 04:08:55 PM PDT 24 2600558479 ps
T104 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3085770374 May 12 04:08:57 PM PDT 24 May 12 04:08:59 PM PDT 24 552335031 ps
T805 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3079325542 May 12 04:08:59 PM PDT 24 May 12 04:09:00 PM PDT 24 338192707 ps
T90 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1835429010 May 12 04:08:38 PM PDT 24 May 12 04:08:40 PM PDT 24 1374990448 ps
T91 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.865911816 May 12 04:08:42 PM PDT 24 May 12 04:08:45 PM PDT 24 931497281 ps
T76 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.35467192 May 12 04:08:47 PM PDT 24 May 12 04:08:49 PM PDT 24 744144407 ps
T57 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4147262347 May 12 04:08:43 PM PDT 24 May 12 04:08:45 PM PDT 24 317556968 ps
T806 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.18051718 May 12 04:09:03 PM PDT 24 May 12 04:09:05 PM PDT 24 457454056 ps
T92 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.48402276 May 12 04:08:57 PM PDT 24 May 12 04:09:00 PM PDT 24 352992377 ps
T807 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.260993896 May 12 04:08:57 PM PDT 24 May 12 04:08:59 PM PDT 24 352983850 ps
T51 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3769495159 May 12 04:08:43 PM PDT 24 May 12 04:08:48 PM PDT 24 9209542014 ps
T808 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1178301032 May 12 04:08:44 PM PDT 24 May 12 04:08:48 PM PDT 24 1170383675 ps
T809 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.623989165 May 12 04:09:01 PM PDT 24 May 12 04:09:02 PM PDT 24 494515844 ps
T105 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3888186932 May 12 04:09:00 PM PDT 24 May 12 04:09:09 PM PDT 24 2272840795 ps
T77 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2676101705 May 12 04:08:46 PM PDT 24 May 12 04:08:49 PM PDT 24 492706792 ps
T106 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4272883167 May 12 04:08:47 PM PDT 24 May 12 04:08:58 PM PDT 24 4905770653 ps
T810 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1972831492 May 12 04:08:58 PM PDT 24 May 12 04:09:00 PM PDT 24 340989599 ps
T811 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.705541280 May 12 04:09:02 PM PDT 24 May 12 04:09:04 PM PDT 24 425910812 ps
T58 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3602435345 May 12 04:08:52 PM PDT 24 May 12 04:08:55 PM PDT 24 460634498 ps
T59 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2001168933 May 12 04:08:36 PM PDT 24 May 12 04:08:39 PM PDT 24 370803537 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.693027139 May 12 04:08:41 PM PDT 24 May 12 04:08:51 PM PDT 24 5190720882 ps
T813 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3105900589 May 12 04:09:03 PM PDT 24 May 12 04:09:08 PM PDT 24 2323122122 ps
T814 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2975632155 May 12 04:09:07 PM PDT 24 May 12 04:09:10 PM PDT 24 428023987 ps
T52 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2369333501 May 12 04:08:49 PM PDT 24 May 12 04:08:54 PM PDT 24 4422065485 ps
T815 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.29148696 May 12 04:09:00 PM PDT 24 May 12 04:09:01 PM PDT 24 332864453 ps
T63 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3171264199 May 12 04:08:49 PM PDT 24 May 12 04:08:51 PM PDT 24 348105230 ps
T816 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3732857220 May 12 04:08:54 PM PDT 24 May 12 04:08:56 PM PDT 24 448815484 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2170329699 May 12 04:08:38 PM PDT 24 May 12 04:08:40 PM PDT 24 711208134 ps
T818 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3054607923 May 12 04:09:07 PM PDT 24 May 12 04:09:09 PM PDT 24 471815390 ps
T62 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.139964701 May 12 04:08:35 PM PDT 24 May 12 04:08:58 PM PDT 24 8683431094 ps
T819 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.490072797 May 12 04:09:07 PM PDT 24 May 12 04:09:11 PM PDT 24 606220502 ps
T311 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2950400853 May 12 04:08:39 PM PDT 24 May 12 04:08:47 PM PDT 24 7781314713 ps
T65 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1798409934 May 12 04:09:01 PM PDT 24 May 12 04:09:04 PM PDT 24 429575878 ps
T314 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4082769537 May 12 04:08:49 PM PDT 24 May 12 04:08:57 PM PDT 24 8739907074 ps
T820 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2517556867 May 12 04:08:44 PM PDT 24 May 12 04:08:57 PM PDT 24 26492442645 ps
T821 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.69147465 May 12 04:08:51 PM PDT 24 May 12 04:08:52 PM PDT 24 515415055 ps
T66 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1369311151 May 12 04:08:54 PM PDT 24 May 12 04:08:59 PM PDT 24 4595422882 ps
T64 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2335652215 May 12 04:08:53 PM PDT 24 May 12 04:08:56 PM PDT 24 841728897 ps
T822 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1004619984 May 12 04:08:50 PM PDT 24 May 12 04:08:52 PM PDT 24 378566794 ps
T823 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3461171677 May 12 04:08:54 PM PDT 24 May 12 04:08:57 PM PDT 24 490566546 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.946766438 May 12 04:08:49 PM PDT 24 May 12 04:08:52 PM PDT 24 394235976 ps
T825 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2811790767 May 12 04:09:03 PM PDT 24 May 12 04:09:05 PM PDT 24 356877489 ps
T93 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2323610669 May 12 04:08:36 PM PDT 24 May 12 04:08:41 PM PDT 24 1332711339 ps
T826 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3428703055 May 12 04:09:00 PM PDT 24 May 12 04:09:02 PM PDT 24 354438181 ps
T94 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3636669719 May 12 04:08:57 PM PDT 24 May 12 04:08:59 PM PDT 24 566965791 ps
T827 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.525850990 May 12 04:08:56 PM PDT 24 May 12 04:08:57 PM PDT 24 366851466 ps
T828 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2545340591 May 12 04:08:45 PM PDT 24 May 12 04:08:47 PM PDT 24 486185099 ps
T829 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.438367181 May 12 04:09:01 PM PDT 24 May 12 04:09:03 PM PDT 24 490205486 ps
T830 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2768502953 May 12 04:08:58 PM PDT 24 May 12 04:09:00 PM PDT 24 498590983 ps
T831 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2479370530 May 12 04:08:45 PM PDT 24 May 12 04:08:51 PM PDT 24 2767867587 ps
T832 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1589204155 May 12 04:08:44 PM PDT 24 May 12 04:08:46 PM PDT 24 2221876790 ps
T833 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2291367301 May 12 04:09:08 PM PDT 24 May 12 04:09:11 PM PDT 24 454595954 ps
T834 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3918319600 May 12 04:08:58 PM PDT 24 May 12 04:09:01 PM PDT 24 521401003 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.202244894 May 12 04:08:52 PM PDT 24 May 12 04:08:57 PM PDT 24 621256759 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1110560266 May 12 04:08:57 PM PDT 24 May 12 04:08:59 PM PDT 24 417960492 ps
T837 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3877795718 May 12 04:08:48 PM PDT 24 May 12 04:09:00 PM PDT 24 4465629174 ps
T838 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1022046087 May 12 04:08:47 PM PDT 24 May 12 04:08:51 PM PDT 24 731350882 ps
T95 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3934760606 May 12 04:08:40 PM PDT 24 May 12 04:08:43 PM PDT 24 1320100239 ps
T839 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.724798663 May 12 04:08:55 PM PDT 24 May 12 04:08:57 PM PDT 24 472495385 ps
T840 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3224227882 May 12 04:08:40 PM PDT 24 May 12 04:08:42 PM PDT 24 425819784 ps
T841 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.842165719 May 12 04:08:45 PM PDT 24 May 12 04:08:49 PM PDT 24 578567956 ps
T842 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.627899111 May 12 04:08:59 PM PDT 24 May 12 04:09:01 PM PDT 24 386339197 ps
T843 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2465297772 May 12 04:08:51 PM PDT 24 May 12 04:09:17 PM PDT 24 8977406088 ps
T844 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3879203921 May 12 04:08:49 PM PDT 24 May 12 04:08:54 PM PDT 24 4898337978 ps
T845 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3490257894 May 12 04:09:00 PM PDT 24 May 12 04:09:02 PM PDT 24 363457349 ps
T315 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.308263192 May 12 04:08:56 PM PDT 24 May 12 04:09:19 PM PDT 24 8469934912 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1155112620 May 12 04:08:45 PM PDT 24 May 12 04:08:49 PM PDT 24 887140214 ps
T847 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.801273690 May 12 04:09:06 PM PDT 24 May 12 04:09:07 PM PDT 24 536760594 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.7156209 May 12 04:08:50 PM PDT 24 May 12 04:08:52 PM PDT 24 507637845 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3392979440 May 12 04:09:04 PM PDT 24 May 12 04:09:06 PM PDT 24 417216896 ps
T850 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4218194057 May 12 04:08:49 PM PDT 24 May 12 04:08:51 PM PDT 24 790482670 ps
T851 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1860728503 May 12 04:08:49 PM PDT 24 May 12 04:08:52 PM PDT 24 759734454 ps
T852 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1177306329 May 12 04:08:41 PM PDT 24 May 12 04:08:44 PM PDT 24 545105027 ps
T96 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2798724972 May 12 04:08:49 PM PDT 24 May 12 04:08:50 PM PDT 24 435266113 ps
T853 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1282613508 May 12 04:08:54 PM PDT 24 May 12 04:08:57 PM PDT 24 529391968 ps
T854 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1889883248 May 12 04:08:49 PM PDT 24 May 12 04:08:51 PM PDT 24 339742440 ps
T855 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.711104538 May 12 04:09:07 PM PDT 24 May 12 04:09:10 PM PDT 24 538022741 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.131264713 May 12 04:08:58 PM PDT 24 May 12 04:09:00 PM PDT 24 518331750 ps
T97 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.458215448 May 12 04:08:52 PM PDT 24 May 12 04:08:53 PM PDT 24 519400740 ps
T857 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.654902799 May 12 04:09:07 PM PDT 24 May 12 04:09:10 PM PDT 24 398454558 ps
T858 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3402215861 May 12 04:09:02 PM PDT 24 May 12 04:09:04 PM PDT 24 427525725 ps
T859 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1231560168 May 12 04:09:03 PM PDT 24 May 12 04:09:10 PM PDT 24 7907694717 ps
T860 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3748402398 May 12 04:08:45 PM PDT 24 May 12 04:08:47 PM PDT 24 431954459 ps
T861 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1793616244 May 12 04:09:08 PM PDT 24 May 12 04:09:10 PM PDT 24 310859938 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2404660676 May 12 04:08:43 PM PDT 24 May 12 04:08:47 PM PDT 24 2058565161 ps
T863 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2252008888 May 12 04:09:00 PM PDT 24 May 12 04:09:02 PM PDT 24 446779860 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4238816718 May 12 04:08:42 PM PDT 24 May 12 04:08:46 PM PDT 24 615561005 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3061129192 May 12 04:08:45 PM PDT 24 May 12 04:08:48 PM PDT 24 523761178 ps
T866 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.383882274 May 12 04:09:07 PM PDT 24 May 12 04:09:09 PM PDT 24 310496603 ps
T867 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.350128373 May 12 04:08:46 PM PDT 24 May 12 04:08:52 PM PDT 24 9033764241 ps
T868 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1186980799 May 12 04:08:46 PM PDT 24 May 12 04:08:49 PM PDT 24 499091391 ps
T869 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.441924886 May 12 04:08:55 PM PDT 24 May 12 04:08:57 PM PDT 24 511400950 ps
T870 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1047310813 May 12 04:08:55 PM PDT 24 May 12 04:09:04 PM PDT 24 9043517436 ps
T871 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3720764346 May 12 04:09:06 PM PDT 24 May 12 04:09:08 PM PDT 24 396448220 ps
T872 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3895225550 May 12 04:08:45 PM PDT 24 May 12 04:08:46 PM PDT 24 453024090 ps
T873 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3769839622 May 12 04:08:56 PM PDT 24 May 12 04:09:05 PM PDT 24 2807391111 ps
T874 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3089878291 May 12 04:08:39 PM PDT 24 May 12 04:08:40 PM PDT 24 406376139 ps
T875 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1308589998 May 12 04:09:03 PM PDT 24 May 12 04:09:07 PM PDT 24 519197295 ps
T876 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4262725141 May 12 04:08:52 PM PDT 24 May 12 04:08:54 PM PDT 24 498948712 ps
T877 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2914506497 May 12 04:08:39 PM PDT 24 May 12 04:08:41 PM PDT 24 330716319 ps
T98 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1349823350 May 12 04:08:39 PM PDT 24 May 12 04:08:52 PM PDT 24 42594466497 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3052642696 May 12 04:08:46 PM PDT 24 May 12 04:08:48 PM PDT 24 452072385 ps
T879 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.542094185 May 12 04:09:01 PM PDT 24 May 12 04:09:02 PM PDT 24 486635332 ps
T880 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.380317638 May 12 04:09:03 PM PDT 24 May 12 04:09:05 PM PDT 24 406405527 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1434218645 May 12 04:08:41 PM PDT 24 May 12 04:08:43 PM PDT 24 980067929 ps
T882 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.818436486 May 12 04:08:56 PM PDT 24 May 12 04:08:58 PM PDT 24 385097424 ps
T883 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2146277866 May 12 04:08:43 PM PDT 24 May 12 04:08:45 PM PDT 24 1464988657 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.904823595 May 12 04:08:56 PM PDT 24 May 12 04:09:08 PM PDT 24 4113820901 ps
T312 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.866582598 May 12 04:08:54 PM PDT 24 May 12 04:09:16 PM PDT 24 7878654687 ps
T885 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1315908685 May 12 04:08:53 PM PDT 24 May 12 04:08:55 PM PDT 24 610135732 ps
T886 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.24297917 May 12 04:08:56 PM PDT 24 May 12 04:08:58 PM PDT 24 381261612 ps
T99 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.816069837 May 12 04:08:40 PM PDT 24 May 12 04:08:44 PM PDT 24 1237556995 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.226135004 May 12 04:08:46 PM PDT 24 May 12 04:08:48 PM PDT 24 530088069 ps
T100 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.762503452 May 12 04:08:45 PM PDT 24 May 12 04:08:47 PM PDT 24 324682101 ps
T888 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2147502605 May 12 04:08:45 PM PDT 24 May 12 04:08:48 PM PDT 24 674527377 ps
T889 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1102411999 May 12 04:08:39 PM PDT 24 May 12 04:08:40 PM PDT 24 427114831 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1935699354 May 12 04:08:57 PM PDT 24 May 12 04:09:01 PM PDT 24 4912225070 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3268168530 May 12 04:08:45 PM PDT 24 May 12 04:08:54 PM PDT 24 3073708341 ps
T892 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3630397811 May 12 04:08:56 PM PDT 24 May 12 04:08:58 PM PDT 24 362867537 ps
T893 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2603293578 May 12 04:09:03 PM PDT 24 May 12 04:09:06 PM PDT 24 503388805 ps
T894 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1213217290 May 12 04:09:02 PM PDT 24 May 12 04:09:11 PM PDT 24 5120460262 ps
T101 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4041241212 May 12 04:08:44 PM PDT 24 May 12 04:11:04 PM PDT 24 53070816890 ps
T895 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2623565798 May 12 04:08:55 PM PDT 24 May 12 04:08:58 PM PDT 24 478856505 ps
T896 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1206119454 May 12 04:08:56 PM PDT 24 May 12 04:09:06 PM PDT 24 2750509426 ps
T897 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.21539707 May 12 04:08:57 PM PDT 24 May 12 04:08:59 PM PDT 24 452662146 ps
T898 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3000535755 May 12 04:08:56 PM PDT 24 May 12 04:08:59 PM PDT 24 458150320 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2873865278 May 12 04:08:44 PM PDT 24 May 12 04:10:50 PM PDT 24 52148759913 ps
T102 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.766694350 May 12 04:08:39 PM PDT 24 May 12 04:10:32 PM PDT 24 49747112235 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1543704812 May 12 04:08:57 PM PDT 24 May 12 04:09:00 PM PDT 24 480085524 ps
T901 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2129847599 May 12 04:08:46 PM PDT 24 May 12 04:08:51 PM PDT 24 563212847 ps
T902 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2032709270 May 12 04:08:57 PM PDT 24 May 12 04:09:05 PM PDT 24 2513727796 ps
T903 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1131901291 May 12 04:08:46 PM PDT 24 May 12 04:08:49 PM PDT 24 512401047 ps
T904 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3458834407 May 12 04:09:03 PM PDT 24 May 12 04:09:17 PM PDT 24 4492392256 ps
T905 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2086838270 May 12 04:09:10 PM PDT 24 May 12 04:09:12 PM PDT 24 423628937 ps
T906 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2652397608 May 12 04:08:57 PM PDT 24 May 12 04:09:01 PM PDT 24 1773539220 ps
T67 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3397501306 May 12 04:08:46 PM PDT 24 May 12 04:08:53 PM PDT 24 8500725171 ps
T907 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2319729671 May 12 04:08:58 PM PDT 24 May 12 04:09:06 PM PDT 24 4340837570 ps
T908 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2805059583 May 12 04:08:47 PM PDT 24 May 12 04:08:58 PM PDT 24 2290040693 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2497235602 May 12 04:09:03 PM PDT 24 May 12 04:09:05 PM PDT 24 334796411 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1351711711 May 12 04:08:40 PM PDT 24 May 12 04:08:42 PM PDT 24 495303781 ps
T313 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2533660612 May 12 04:08:49 PM PDT 24 May 12 04:09:02 PM PDT 24 4378885941 ps
T911 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3389319606 May 12 04:08:56 PM PDT 24 May 12 04:09:00 PM PDT 24 4480850332 ps
T912 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2039573479 May 12 04:08:44 PM PDT 24 May 12 04:08:45 PM PDT 24 326270512 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3659284987 May 12 04:08:40 PM PDT 24 May 12 04:08:45 PM PDT 24 4389921020 ps
T914 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3334562134 May 12 04:09:07 PM PDT 24 May 12 04:09:09 PM PDT 24 530132715 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.379180538 May 12 04:08:43 PM PDT 24 May 12 04:08:46 PM PDT 24 590327977 ps
T916 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.105441484 May 12 04:09:03 PM PDT 24 May 12 04:09:05 PM PDT 24 338179009 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1864616539 May 12 04:08:45 PM PDT 24 May 12 04:08:47 PM PDT 24 419869184 ps

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.420921780
Short name T1
Test name
Test status
Simulation time 197596325188 ps
CPU time 118.54 seconds
Started May 12 04:13:02 PM PDT 24
Finished May 12 04:15:01 PM PDT 24
Peak memory 202352 kb
Host smart-38a9e94c-4cbd-44bf-8790-fc89008511cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420921780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.420921780
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3147099839
Short name T11
Test name
Test status
Simulation time 124593640264 ps
CPU time 309.81 seconds
Started May 12 04:09:06 PM PDT 24
Finished May 12 04:14:16 PM PDT 24
Peak memory 218624 kb
Host smart-b285ac79-f9c8-4f3b-b9ee-c99ee67ccf5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147099839 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3147099839
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2333387241
Short name T16
Test name
Test status
Simulation time 650594838200 ps
CPU time 311.32 seconds
Started May 12 04:10:17 PM PDT 24
Finished May 12 04:15:29 PM PDT 24
Peak memory 210928 kb
Host smart-2711cbcd-20db-467c-99a1-cd73207caf5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333387241 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2333387241
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1763162298
Short name T30
Test name
Test status
Simulation time 532796492744 ps
CPU time 941.37 seconds
Started May 12 04:13:29 PM PDT 24
Finished May 12 04:29:11 PM PDT 24
Peak memory 202424 kb
Host smart-e3ae59bc-fa3a-438a-9886-b5b9f1e36f92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763162298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1763162298
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.124091234
Short name T5
Test name
Test status
Simulation time 492553619482 ps
CPU time 1221.56 seconds
Started May 12 04:12:18 PM PDT 24
Finished May 12 04:32:40 PM PDT 24
Peak memory 202316 kb
Host smart-30ee5172-d76d-451f-8af5-ad6b667cbb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124091234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.124091234
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3455875097
Short name T169
Test name
Test status
Simulation time 145575431257 ps
CPU time 374.49 seconds
Started May 12 04:12:55 PM PDT 24
Finished May 12 04:19:10 PM PDT 24
Peak memory 211000 kb
Host smart-adda8ed2-25ad-4734-af20-48a060600527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455875097 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3455875097
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1775015182
Short name T125
Test name
Test status
Simulation time 515714602836 ps
CPU time 104.1 seconds
Started May 12 04:09:45 PM PDT 24
Finished May 12 04:11:30 PM PDT 24
Peak memory 202316 kb
Host smart-9084a8f8-4790-41a8-845a-546e05129441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775015182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1775015182
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2218216918
Short name T177
Test name
Test status
Simulation time 489897895335 ps
CPU time 217.58 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:13:14 PM PDT 24
Peak memory 202280 kb
Host smart-2764c1b1-bda9-4011-a4a9-0a7b3c87d6d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218216918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2218216918
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1285641429
Short name T114
Test name
Test status
Simulation time 498704619802 ps
CPU time 154.53 seconds
Started May 12 04:10:37 PM PDT 24
Finished May 12 04:13:12 PM PDT 24
Peak memory 202288 kb
Host smart-04d7b406-7949-4f45-8b97-09524600eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285641429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1285641429
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3462490778
Short name T128
Test name
Test status
Simulation time 500741898233 ps
CPU time 300.78 seconds
Started May 12 04:11:20 PM PDT 24
Finished May 12 04:16:21 PM PDT 24
Peak memory 202388 kb
Host smart-76c8b56c-053c-4b5b-8ed8-9f88523f1b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462490778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3462490778
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4147262347
Short name T57
Test name
Test status
Simulation time 317556968 ps
CPU time 1.82 seconds
Started May 12 04:08:43 PM PDT 24
Finished May 12 04:08:45 PM PDT 24
Peak memory 201512 kb
Host smart-f52daad5-4206-45a7-b814-227ed56f0c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147262347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4147262347
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2877379962
Short name T27
Test name
Test status
Simulation time 3763155417 ps
CPU time 8.54 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:09:27 PM PDT 24
Peak memory 217952 kb
Host smart-3e2ded06-885b-4f1b-a999-7d3fb8f3f5ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877379962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2877379962
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3507239729
Short name T14
Test name
Test status
Simulation time 552605496094 ps
CPU time 1261.28 seconds
Started May 12 04:11:21 PM PDT 24
Finished May 12 04:32:23 PM PDT 24
Peak memory 202372 kb
Host smart-67766654-e4b1-4351-a958-7cf39256acdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507239729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3507239729
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3679006096
Short name T148
Test name
Test status
Simulation time 550792597657 ps
CPU time 1232.42 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:29:48 PM PDT 24
Peak memory 202340 kb
Host smart-97eb4181-4c14-436b-afb8-e00a9eb0d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679006096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3679006096
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.827563271
Short name T185
Test name
Test status
Simulation time 330312882030 ps
CPU time 728.92 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:21:46 PM PDT 24
Peak memory 202292 kb
Host smart-993b02ab-57a2-4ded-a4a1-7bdb2df29ce5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827563271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.827563271
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1484336799
Short name T89
Test name
Test status
Simulation time 465536721 ps
CPU time 2.06 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201228 kb
Host smart-abad0f3f-2847-434c-bdd8-309b7689be8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484336799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1484336799
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3040160594
Short name T171
Test name
Test status
Simulation time 482671091931 ps
CPU time 1070.4 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:27:03 PM PDT 24
Peak memory 202320 kb
Host smart-fb264103-3117-4bf0-ad37-b763fe5567e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040160594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3040160594
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2561632357
Short name T17
Test name
Test status
Simulation time 744778285041 ps
CPU time 297.5 seconds
Started May 12 04:10:53 PM PDT 24
Finished May 12 04:15:51 PM PDT 24
Peak memory 210960 kb
Host smart-59d0d4cd-310c-4484-beeb-acd577af2d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561632357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2561632357
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3680810671
Short name T132
Test name
Test status
Simulation time 515382526164 ps
CPU time 1064.7 seconds
Started May 12 04:10:48 PM PDT 24
Finished May 12 04:28:33 PM PDT 24
Peak memory 202340 kb
Host smart-7a26710d-9858-4353-9c66-605fb8334069
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680810671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3680810671
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1770551710
Short name T197
Test name
Test status
Simulation time 323140317861 ps
CPU time 104.15 seconds
Started May 12 04:13:39 PM PDT 24
Finished May 12 04:15:24 PM PDT 24
Peak memory 202384 kb
Host smart-b56e0532-5e8b-4ce1-a45d-d09f5e024633
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770551710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1770551710
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1910883517
Short name T191
Test name
Test status
Simulation time 535216563353 ps
CPU time 1160.04 seconds
Started May 12 04:12:34 PM PDT 24
Finished May 12 04:31:55 PM PDT 24
Peak memory 202296 kb
Host smart-838ae3b4-6944-4f26-a208-28d23725a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910883517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1910883517
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3182115336
Short name T13
Test name
Test status
Simulation time 316034362428 ps
CPU time 153.52 seconds
Started May 12 04:11:09 PM PDT 24
Finished May 12 04:13:43 PM PDT 24
Peak memory 202420 kb
Host smart-a5d5eba8-81ef-4b1b-bc05-3746158e8580
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182115336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3182115336
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1422730111
Short name T170
Test name
Test status
Simulation time 226216519546 ps
CPU time 47.69 seconds
Started May 12 04:09:20 PM PDT 24
Finished May 12 04:10:08 PM PDT 24
Peak memory 210628 kb
Host smart-7dbad9e0-9066-434e-8136-ae55142ff415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422730111 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1422730111
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1341564927
Short name T183
Test name
Test status
Simulation time 354088158380 ps
CPU time 419.9 seconds
Started May 12 04:11:48 PM PDT 24
Finished May 12 04:18:48 PM PDT 24
Peak memory 202324 kb
Host smart-6adfa713-0a99-4dbf-88bb-0857b6888c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341564927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1341564927
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.756572662
Short name T134
Test name
Test status
Simulation time 557684417657 ps
CPU time 77.69 seconds
Started May 12 04:11:40 PM PDT 24
Finished May 12 04:12:58 PM PDT 24
Peak memory 202296 kb
Host smart-78e27feb-59e4-4f5e-86a0-b344cdd0b3f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756572662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.756572662
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2507152584
Short name T259
Test name
Test status
Simulation time 178482364577 ps
CPU time 383.37 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:15:59 PM PDT 24
Peak memory 202312 kb
Host smart-0fb1c382-821b-4c08-a2d7-87acfab27aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507152584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2507152584
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1790322940
Short name T210
Test name
Test status
Simulation time 592619279060 ps
CPU time 1268.79 seconds
Started May 12 04:14:37 PM PDT 24
Finished May 12 04:35:46 PM PDT 24
Peak memory 202308 kb
Host smart-109506f4-da7b-4287-b49d-4b9d1a55fb8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790322940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1790322940
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2950400853
Short name T311
Test name
Test status
Simulation time 7781314713 ps
CPU time 7.25 seconds
Started May 12 04:08:39 PM PDT 24
Finished May 12 04:08:47 PM PDT 24
Peak memory 201540 kb
Host smart-db4fc72d-3dad-4e87-b01a-e31ac547d575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950400853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2950400853
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3600619130
Short name T359
Test name
Test status
Simulation time 537284225 ps
CPU time 0.94 seconds
Started May 12 04:10:19 PM PDT 24
Finished May 12 04:10:20 PM PDT 24
Peak memory 201988 kb
Host smart-d2eecca7-3fb8-4a12-97b6-25a8fd5fb32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600619130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3600619130
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1158992398
Short name T194
Test name
Test status
Simulation time 414240146856 ps
CPU time 496.81 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:17:51 PM PDT 24
Peak memory 211000 kb
Host smart-679edd3b-18f1-45df-b763-6e70f2db4de6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158992398 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1158992398
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1972431688
Short name T33
Test name
Test status
Simulation time 139673619444 ps
CPU time 374.73 seconds
Started May 12 04:09:29 PM PDT 24
Finished May 12 04:15:44 PM PDT 24
Peak memory 210924 kb
Host smart-c9c5cbb3-db89-4398-aefb-47bdb1a8ebc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972431688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1972431688
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.679802947
Short name T232
Test name
Test status
Simulation time 535207903586 ps
CPU time 1320.67 seconds
Started May 12 04:09:31 PM PDT 24
Finished May 12 04:31:32 PM PDT 24
Peak memory 202304 kb
Host smart-3f3f6ac4-ecfc-40ae-af35-b9a36403b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679802947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.679802947
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2074582331
Short name T248
Test name
Test status
Simulation time 526786935586 ps
CPU time 608.9 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:19:57 PM PDT 24
Peak memory 202420 kb
Host smart-2c388c47-4dac-403e-b50c-6236731a3532
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074582331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2074582331
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3706078817
Short name T39
Test name
Test status
Simulation time 161744082487 ps
CPU time 150.12 seconds
Started May 12 04:09:51 PM PDT 24
Finished May 12 04:12:22 PM PDT 24
Peak memory 218456 kb
Host smart-65ac43af-d89e-419e-a68f-14405663414b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706078817 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3706078817
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3627020750
Short name T38
Test name
Test status
Simulation time 47811245828 ps
CPU time 89.15 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:10:42 PM PDT 24
Peak memory 217624 kb
Host smart-aad24e70-1b42-44db-9dcd-b1ce8d104a77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627020750 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3627020750
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4287965133
Short name T201
Test name
Test status
Simulation time 421022690869 ps
CPU time 230.34 seconds
Started May 12 04:12:54 PM PDT 24
Finished May 12 04:16:44 PM PDT 24
Peak memory 202300 kb
Host smart-7a967a1b-e02c-4ae1-afac-cec5204cba36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287965133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4287965133
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.448245419
Short name T142
Test name
Test status
Simulation time 487763289392 ps
CPU time 112.7 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:11:05 PM PDT 24
Peak memory 202352 kb
Host smart-c4e54b4d-3f3d-42aa-b0e6-a9e087f8cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448245419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.448245419
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3766278253
Short name T238
Test name
Test status
Simulation time 206736599334 ps
CPU time 217.09 seconds
Started May 12 04:11:23 PM PDT 24
Finished May 12 04:15:00 PM PDT 24
Peak memory 211232 kb
Host smart-0b521791-7d79-4ae2-a4ae-a39526ea0e2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766278253 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3766278253
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1436010076
Short name T131
Test name
Test status
Simulation time 165043859378 ps
CPU time 363.46 seconds
Started May 12 04:11:40 PM PDT 24
Finished May 12 04:17:44 PM PDT 24
Peak memory 202340 kb
Host smart-0c05d165-8386-44b9-bfad-57549974f3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436010076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1436010076
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.926061891
Short name T272
Test name
Test status
Simulation time 359749501422 ps
CPU time 291.25 seconds
Started May 12 04:11:46 PM PDT 24
Finished May 12 04:16:38 PM PDT 24
Peak memory 202332 kb
Host smart-17679aed-7b5d-4303-a4be-69f25de62bb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926061891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.926061891
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1664221832
Short name T255
Test name
Test status
Simulation time 336247351028 ps
CPU time 836.18 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:23:25 PM PDT 24
Peak memory 202396 kb
Host smart-27eb64fe-c934-45d1-b0e2-1bfa39f3cba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664221832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1664221832
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3907690906
Short name T137
Test name
Test status
Simulation time 337224041631 ps
CPU time 216.86 seconds
Started May 12 04:10:47 PM PDT 24
Finished May 12 04:14:24 PM PDT 24
Peak memory 202324 kb
Host smart-8db6b770-7d49-45be-bb0f-42c6266f75a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907690906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3907690906
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.902144353
Short name T797
Test name
Test status
Simulation time 350181846932 ps
CPU time 203.17 seconds
Started May 12 04:14:24 PM PDT 24
Finished May 12 04:17:48 PM PDT 24
Peak memory 202400 kb
Host smart-c44ea962-adc9-43ec-b308-7c2802b3b7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902144353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.902144353
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2749891142
Short name T203
Test name
Test status
Simulation time 181469324457 ps
CPU time 95.39 seconds
Started May 12 04:14:19 PM PDT 24
Finished May 12 04:15:54 PM PDT 24
Peak memory 202432 kb
Host smart-a94714ac-5e71-43b1-b378-d5610317e328
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749891142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2749891142
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.152308234
Short name T241
Test name
Test status
Simulation time 166426068972 ps
CPU time 384.45 seconds
Started May 12 04:10:51 PM PDT 24
Finished May 12 04:17:16 PM PDT 24
Peak memory 202336 kb
Host smart-b2f420af-6340-4faf-a70a-ccb42f33b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152308234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.152308234
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.202244894
Short name T835
Test name
Test status
Simulation time 621256759 ps
CPU time 4.08 seconds
Started May 12 04:08:52 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201484 kb
Host smart-a2a2ef4c-618f-4210-931a-dc65852b8d61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202244894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.202244894
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.900575961
Short name T305
Test name
Test status
Simulation time 525245357559 ps
CPU time 909.21 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:24:19 PM PDT 24
Peak memory 202332 kb
Host smart-cf038af7-c4a8-411b-bd56-3b2137351e27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900575961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.900575961
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.574460119
Short name T156
Test name
Test status
Simulation time 327557578518 ps
CPU time 731.46 seconds
Started May 12 04:11:12 PM PDT 24
Finished May 12 04:23:24 PM PDT 24
Peak memory 202312 kb
Host smart-595f37a4-4ed6-4419-9576-089521babbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574460119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.574460119
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2426160594
Short name T211
Test name
Test status
Simulation time 165145119923 ps
CPU time 94.78 seconds
Started May 12 04:11:23 PM PDT 24
Finished May 12 04:12:58 PM PDT 24
Peak memory 202516 kb
Host smart-58676bb9-b063-4ffe-95ae-9cb0f9434c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426160594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2426160594
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1437062672
Short name T246
Test name
Test status
Simulation time 523896936729 ps
CPU time 109.1 seconds
Started May 12 04:13:57 PM PDT 24
Finished May 12 04:15:47 PM PDT 24
Peak memory 202344 kb
Host smart-c118e945-35d7-4b2c-adf1-52f0322af532
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437062672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1437062672
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.256417083
Short name T271
Test name
Test status
Simulation time 503728463094 ps
CPU time 1054.71 seconds
Started May 12 04:10:04 PM PDT 24
Finished May 12 04:27:39 PM PDT 24
Peak memory 202328 kb
Host smart-e66d23ac-cf7c-4a68-9487-232a45c5dc9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256417083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.256417083
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2999780514
Short name T260
Test name
Test status
Simulation time 326361815555 ps
CPU time 480.36 seconds
Started May 12 04:12:08 PM PDT 24
Finished May 12 04:20:09 PM PDT 24
Peak memory 202284 kb
Host smart-172787bf-f3f9-4216-aacd-f7c50e11665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999780514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2999780514
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1864492458
Short name T277
Test name
Test status
Simulation time 356567384649 ps
CPU time 814.56 seconds
Started May 12 04:13:14 PM PDT 24
Finished May 12 04:26:49 PM PDT 24
Peak memory 202300 kb
Host smart-7a1ca693-e7e1-452b-a0b1-48c0ea336373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864492458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1864492458
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4260393189
Short name T279
Test name
Test status
Simulation time 337245264684 ps
CPU time 825.49 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:23:34 PM PDT 24
Peak memory 202328 kb
Host smart-dda07fe0-7991-40e6-bca6-b408b66a9d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260393189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4260393189
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2417953829
Short name T273
Test name
Test status
Simulation time 528774431229 ps
CPU time 1313.24 seconds
Started May 12 04:10:36 PM PDT 24
Finished May 12 04:32:30 PM PDT 24
Peak memory 202348 kb
Host smart-ecba82e0-ca53-4fc5-b5dd-a9d2b74d738d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417953829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2417953829
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2314582743
Short name T281
Test name
Test status
Simulation time 111140675403 ps
CPU time 286.39 seconds
Started May 12 04:11:07 PM PDT 24
Finished May 12 04:15:53 PM PDT 24
Peak memory 211060 kb
Host smart-ba9cbaa5-25fb-483d-830a-6e2a1b818860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314582743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2314582743
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2757176192
Short name T292
Test name
Test status
Simulation time 372444474194 ps
CPU time 225.92 seconds
Started May 12 04:12:38 PM PDT 24
Finished May 12 04:16:24 PM PDT 24
Peak memory 218288 kb
Host smart-fc2999dd-06d3-44a1-a1cb-5122dc9b9999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757176192 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2757176192
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3902510009
Short name T251
Test name
Test status
Simulation time 165604369233 ps
CPU time 392.8 seconds
Started May 12 04:14:08 PM PDT 24
Finished May 12 04:20:41 PM PDT 24
Peak memory 202288 kb
Host smart-a0668b6b-88b3-466c-9b25-aa4706fd4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902510009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3902510009
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.693027139
Short name T812
Test name
Test status
Simulation time 5190720882 ps
CPU time 9.39 seconds
Started May 12 04:08:41 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 201472 kb
Host smart-4c52e57b-c0f5-41ba-9644-f86f05bf5157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693027139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.693027139
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2613696325
Short name T319
Test name
Test status
Simulation time 143103322539 ps
CPU time 747.62 seconds
Started May 12 04:09:30 PM PDT 24
Finished May 12 04:21:58 PM PDT 24
Peak memory 202752 kb
Host smart-529c2316-7baa-4a82-a956-4bf1f8811b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613696325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2613696325
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2158719557
Short name T297
Test name
Test status
Simulation time 376193784922 ps
CPU time 228.89 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:13:26 PM PDT 24
Peak memory 202344 kb
Host smart-a1c36b45-4486-44b8-8f58-2cebae7f7dac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158719557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2158719557
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.353178490
Short name T225
Test name
Test status
Simulation time 381436386409 ps
CPU time 203.15 seconds
Started May 12 04:09:43 PM PDT 24
Finished May 12 04:13:07 PM PDT 24
Peak memory 202340 kb
Host smart-4d5eb898-8f7e-438d-b956-aa8a4f2ba5a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353178490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.353178490
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4078389963
Short name T321
Test name
Test status
Simulation time 99957658906 ps
CPU time 527.69 seconds
Started May 12 04:09:55 PM PDT 24
Finished May 12 04:18:43 PM PDT 24
Peak memory 202740 kb
Host smart-c042ea7a-499b-471d-a755-8e6a47e917df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078389963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4078389963
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1929261801
Short name T109
Test name
Test status
Simulation time 331383743838 ps
CPU time 581.08 seconds
Started May 12 04:10:22 PM PDT 24
Finished May 12 04:20:04 PM PDT 24
Peak memory 202384 kb
Host smart-9b3eb106-0d4f-4b20-ad95-7662a2d31f46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929261801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1929261801
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1889206828
Short name T165
Test name
Test status
Simulation time 122186416759 ps
CPU time 520.41 seconds
Started May 12 04:12:07 PM PDT 24
Finished May 12 04:20:48 PM PDT 24
Peak memory 202728 kb
Host smart-99738402-62a3-48cb-b8a9-0cb054062563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889206828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1889206828
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3397501306
Short name T67
Test name
Test status
Simulation time 8500725171 ps
CPU time 6.47 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:53 PM PDT 24
Peak memory 201464 kb
Host smart-6a073687-bda6-4415-b2a3-f2494cc8b3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397501306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3397501306
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1702987124
Short name T270
Test name
Test status
Simulation time 427672479915 ps
CPU time 558.69 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:18:29 PM PDT 24
Peak memory 202776 kb
Host smart-b5894e24-4943-40e0-add2-e33d7f945125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702987124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1702987124
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.4026070750
Short name T289
Test name
Test status
Simulation time 602769883824 ps
CPU time 1768.54 seconds
Started May 12 04:09:29 PM PDT 24
Finished May 12 04:38:58 PM PDT 24
Peak memory 210944 kb
Host smart-17e5b1c4-f7bd-403a-83ab-e3f18a68327d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026070750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.4026070750
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.292732918
Short name T161
Test name
Test status
Simulation time 484107247030 ps
CPU time 306.52 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:14:43 PM PDT 24
Peak memory 202284 kb
Host smart-39a22850-54ea-45bf-aad7-fc43ee9c4344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292732918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.292732918
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2355235380
Short name T139
Test name
Test status
Simulation time 493486134316 ps
CPU time 277.11 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:14:17 PM PDT 24
Peak memory 202304 kb
Host smart-8c1ebadc-02e3-45ac-ba4c-4f27b0c394c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355235380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2355235380
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3621764381
Short name T269
Test name
Test status
Simulation time 369835503593 ps
CPU time 875.28 seconds
Started May 12 04:09:45 PM PDT 24
Finished May 12 04:24:21 PM PDT 24
Peak memory 202380 kb
Host smart-56b4529a-0e22-4b9a-bcb8-34fc5bef1c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621764381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3621764381
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3419492247
Short name T247
Test name
Test status
Simulation time 496511123868 ps
CPU time 295.02 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:14:49 PM PDT 24
Peak memory 202308 kb
Host smart-81355dac-c810-4d46-a6f4-d6b21e65a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419492247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3419492247
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1948428861
Short name T307
Test name
Test status
Simulation time 387058588633 ps
CPU time 368.9 seconds
Started May 12 04:09:13 PM PDT 24
Finished May 12 04:15:22 PM PDT 24
Peak memory 202424 kb
Host smart-43390ec6-943e-4ef2-9e8f-eaad7ae6f62b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948428861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1948428861
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3477062908
Short name T284
Test name
Test status
Simulation time 490477433561 ps
CPU time 1180.36 seconds
Started May 12 04:10:18 PM PDT 24
Finished May 12 04:29:59 PM PDT 24
Peak memory 202352 kb
Host smart-ceafe7f2-bca6-4e0d-a3a4-2d3c0a7007cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477062908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3477062908
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2711943607
Short name T276
Test name
Test status
Simulation time 324459826396 ps
CPU time 727.02 seconds
Started May 12 04:11:44 PM PDT 24
Finished May 12 04:23:52 PM PDT 24
Peak memory 202348 kb
Host smart-46e53b4a-8447-4bab-9696-f39f63d3501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711943607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2711943607
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2413397445
Short name T280
Test name
Test status
Simulation time 164733378734 ps
CPU time 395.38 seconds
Started May 12 04:13:36 PM PDT 24
Finished May 12 04:20:12 PM PDT 24
Peak memory 202240 kb
Host smart-10b6ffda-6850-436b-804b-349e24608b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413397445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2413397445
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.936086676
Short name T254
Test name
Test status
Simulation time 335482331554 ps
CPU time 142.43 seconds
Started May 12 04:14:38 PM PDT 24
Finished May 12 04:17:01 PM PDT 24
Peak memory 202392 kb
Host smart-fe6d5f6e-9933-4f59-b65d-e1e5e5be9904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936086676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
936086676
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1906837970
Short name T229
Test name
Test status
Simulation time 172576795720 ps
CPU time 75.75 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:10:53 PM PDT 24
Peak memory 202428 kb
Host smart-a1d1d711-9a1a-4b75-857c-f2e278601060
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906837970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1906837970
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3733485950
Short name T7
Test name
Test status
Simulation time 129602830975 ps
CPU time 660.33 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:20:37 PM PDT 24
Peak memory 202764 kb
Host smart-0c30ab51-4910-46bf-8792-268337fed636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733485950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3733485950
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1017257792
Short name T195
Test name
Test status
Simulation time 335840657962 ps
CPU time 455.43 seconds
Started May 12 04:09:57 PM PDT 24
Finished May 12 04:17:33 PM PDT 24
Peak memory 202312 kb
Host smart-3c47abc2-3c1c-458f-94ed-98f951ab8126
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017257792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1017257792
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3887642793
Short name T23
Test name
Test status
Simulation time 283422693739 ps
CPU time 343.5 seconds
Started May 12 04:10:07 PM PDT 24
Finished May 12 04:15:51 PM PDT 24
Peak memory 211008 kb
Host smart-0b4e0367-bdea-4404-9eb1-843267264a30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887642793 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3887642793
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4142176408
Short name T325
Test name
Test status
Simulation time 456527682013 ps
CPU time 845.16 seconds
Started May 12 04:10:12 PM PDT 24
Finished May 12 04:24:18 PM PDT 24
Peak memory 202660 kb
Host smart-5a0c813c-309c-4165-a250-8ce0677342a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142176408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4142176408
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1388180991
Short name T769
Test name
Test status
Simulation time 81088700116 ps
CPU time 448.17 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:17:44 PM PDT 24
Peak memory 202652 kb
Host smart-fe1cb2ee-ca81-44b1-a465-7b3c6a234d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388180991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1388180991
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2330621928
Short name T193
Test name
Test status
Simulation time 486559555905 ps
CPU time 1348.95 seconds
Started May 12 04:10:35 PM PDT 24
Finished May 12 04:33:05 PM PDT 24
Peak memory 210964 kb
Host smart-1adfd918-3e7b-4c1e-8584-578ecd4a81dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330621928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2330621928
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.966763723
Short name T184
Test name
Test status
Simulation time 483613522175 ps
CPU time 183.68 seconds
Started May 12 04:11:30 PM PDT 24
Finished May 12 04:14:34 PM PDT 24
Peak memory 202336 kb
Host smart-24c99857-f1d1-412a-949b-42f83a7f4dbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966763723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.966763723
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.323264479
Short name T283
Test name
Test status
Simulation time 504566278015 ps
CPU time 584.67 seconds
Started May 12 04:13:44 PM PDT 24
Finished May 12 04:23:29 PM PDT 24
Peak memory 202284 kb
Host smart-7d8d003c-a10a-4316-b669-9e35d0f911a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323264479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.323264479
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.853059404
Short name T264
Test name
Test status
Simulation time 330630466169 ps
CPU time 142.1 seconds
Started May 12 04:14:23 PM PDT 24
Finished May 12 04:16:45 PM PDT 24
Peak memory 202296 kb
Host smart-c784115d-bab6-4af6-aa05-cdf6cd97690d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853059404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.853059404
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.460238726
Short name T323
Test name
Test status
Simulation time 126788319699 ps
CPU time 496.42 seconds
Started May 12 04:14:40 PM PDT 24
Finished May 12 04:22:57 PM PDT 24
Peak memory 202736 kb
Host smart-6a28d9e8-ada5-4e70-8ed4-5e1b0ddf6235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460238726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.460238726
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2971123432
Short name T242
Test name
Test status
Simulation time 280165495655 ps
CPU time 384.73 seconds
Started May 12 04:09:25 PM PDT 24
Finished May 12 04:15:51 PM PDT 24
Peak memory 211000 kb
Host smart-6dbcb32f-1d1e-4038-a7ad-83c33c719923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971123432 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2971123432
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3934760606
Short name T95
Test name
Test status
Simulation time 1320100239 ps
CPU time 2.97 seconds
Started May 12 04:08:40 PM PDT 24
Finished May 12 04:08:43 PM PDT 24
Peak memory 201492 kb
Host smart-b6cfb3c1-beff-4b79-9108-05f249b96310
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934760606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3934760606
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1349823350
Short name T98
Test name
Test status
Simulation time 42594466497 ps
CPU time 12.42 seconds
Started May 12 04:08:39 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 201652 kb
Host smart-4e77ba69-e1c4-4a53-948b-d4dd34fa9b57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349823350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1349823350
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2323610669
Short name T93
Test name
Test status
Simulation time 1332711339 ps
CPU time 4.13 seconds
Started May 12 04:08:36 PM PDT 24
Finished May 12 04:08:41 PM PDT 24
Peak memory 201260 kb
Host smart-340f8b3c-8241-4c99-821f-bb5286c076f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323610669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2323610669
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2170329699
Short name T817
Test name
Test status
Simulation time 711208134 ps
CPU time 1.22 seconds
Started May 12 04:08:38 PM PDT 24
Finished May 12 04:08:40 PM PDT 24
Peak memory 201300 kb
Host smart-464435f4-12e4-41cf-8bc8-a29f2f06d99d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170329699 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2170329699
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1351711711
Short name T910
Test name
Test status
Simulation time 495303781 ps
CPU time 1.2 seconds
Started May 12 04:08:40 PM PDT 24
Finished May 12 04:08:42 PM PDT 24
Peak memory 201248 kb
Host smart-7e5a95c8-9d28-4eb9-b538-99c71fa69e05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351711711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1351711711
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.266239757
Short name T801
Test name
Test status
Simulation time 524811016 ps
CPU time 0.89 seconds
Started May 12 04:08:36 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 201356 kb
Host smart-c68792b7-1d52-476a-b3c0-79e61c1e8663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266239757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.266239757
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2001168933
Short name T59
Test name
Test status
Simulation time 370803537 ps
CPU time 1.54 seconds
Started May 12 04:08:36 PM PDT 24
Finished May 12 04:08:39 PM PDT 24
Peak memory 201512 kb
Host smart-cd91f0fe-89a4-4eac-891d-91c8178cafa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001168933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2001168933
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.139964701
Short name T62
Test name
Test status
Simulation time 8683431094 ps
CPU time 22.13 seconds
Started May 12 04:08:35 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201576 kb
Host smart-81f089bc-e651-4dc0-b894-f500050cebca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139964701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.139964701
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1178301032
Short name T808
Test name
Test status
Simulation time 1170383675 ps
CPU time 3.55 seconds
Started May 12 04:08:44 PM PDT 24
Finished May 12 04:08:48 PM PDT 24
Peak memory 201424 kb
Host smart-83eb45c1-7202-4074-bcf7-ef2673b1ec7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178301032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1178301032
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2873865278
Short name T899
Test name
Test status
Simulation time 52148759913 ps
CPU time 125.47 seconds
Started May 12 04:08:44 PM PDT 24
Finished May 12 04:10:50 PM PDT 24
Peak memory 201520 kb
Host smart-89306404-fb18-4d15-9058-22d2c7687c58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873865278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2873865278
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1835429010
Short name T90
Test name
Test status
Simulation time 1374990448 ps
CPU time 1.62 seconds
Started May 12 04:08:38 PM PDT 24
Finished May 12 04:08:40 PM PDT 24
Peak memory 201208 kb
Host smart-2cb755f7-a28e-466e-a97b-b9ef594df51c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835429010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1835429010
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1102411999
Short name T889
Test name
Test status
Simulation time 427114831 ps
CPU time 1.3 seconds
Started May 12 04:08:39 PM PDT 24
Finished May 12 04:08:40 PM PDT 24
Peak memory 201292 kb
Host smart-07394eda-285f-4074-87a3-90d9b8b7a711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102411999 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1102411999
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3224227882
Short name T840
Test name
Test status
Simulation time 425819784 ps
CPU time 1.06 seconds
Started May 12 04:08:40 PM PDT 24
Finished May 12 04:08:42 PM PDT 24
Peak memory 201272 kb
Host smart-92f59f6f-ec30-4e82-87ed-619716b30739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224227882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3224227882
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3089878291
Short name T874
Test name
Test status
Simulation time 406376139 ps
CPU time 0.88 seconds
Started May 12 04:08:39 PM PDT 24
Finished May 12 04:08:40 PM PDT 24
Peak memory 201228 kb
Host smart-d9964679-c266-407b-9e19-6fe51f223931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089878291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3089878291
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2404660676
Short name T862
Test name
Test status
Simulation time 2058565161 ps
CPU time 3.33 seconds
Started May 12 04:08:43 PM PDT 24
Finished May 12 04:08:47 PM PDT 24
Peak memory 201212 kb
Host smart-bb094f76-19b5-429c-8536-0f0820f95a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404660676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2404660676
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4238816718
Short name T864
Test name
Test status
Simulation time 615561005 ps
CPU time 2.95 seconds
Started May 12 04:08:42 PM PDT 24
Finished May 12 04:08:46 PM PDT 24
Peak memory 201508 kb
Host smart-748e12df-1fe6-4616-9485-dc39befe354f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238816718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4238816718
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3659284987
Short name T913
Test name
Test status
Simulation time 4389921020 ps
CPU time 3.98 seconds
Started May 12 04:08:40 PM PDT 24
Finished May 12 04:08:45 PM PDT 24
Peak memory 201536 kb
Host smart-4198b486-8bf3-4d50-851a-d9e2d1a00252
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659284987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3659284987
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3392979440
Short name T849
Test name
Test status
Simulation time 417216896 ps
CPU time 1.28 seconds
Started May 12 04:09:04 PM PDT 24
Finished May 12 04:09:06 PM PDT 24
Peak memory 201212 kb
Host smart-a721318e-0c49-4062-bea8-421855736f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392979440 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3392979440
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.7156209
Short name T848
Test name
Test status
Simulation time 507637845 ps
CPU time 1 seconds
Started May 12 04:08:50 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 201192 kb
Host smart-7aab481a-9960-4322-ab1f-918edc45e0c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7156209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.7156209
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2497235602
Short name T909
Test name
Test status
Simulation time 334796411 ps
CPU time 1.05 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201168 kb
Host smart-381f7b52-572a-4226-badd-d6f7a03b0e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497235602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2497235602
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.904823595
Short name T884
Test name
Test status
Simulation time 4113820901 ps
CPU time 11.24 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:08 PM PDT 24
Peak memory 201560 kb
Host smart-b21a5701-9180-4d8e-8cf5-f9e3c1205409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904823595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.904823595
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4218194057
Short name T850
Test name
Test status
Simulation time 790482670 ps
CPU time 1.62 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 201488 kb
Host smart-c845f439-682d-416b-a528-d4a50d3d2274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218194057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4218194057
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4082769537
Short name T314
Test name
Test status
Simulation time 8739907074 ps
CPU time 7.61 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201520 kb
Host smart-33c6f3ba-5dfd-40d3-ac25-efd4f32bdc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082769537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4082769537
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3602435345
Short name T58
Test name
Test status
Simulation time 460634498 ps
CPU time 1.97 seconds
Started May 12 04:08:52 PM PDT 24
Finished May 12 04:08:55 PM PDT 24
Peak memory 201264 kb
Host smart-b8900aba-e2e3-4e2a-a654-a5b6655d7355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602435345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3602435345
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.458215448
Short name T97
Test name
Test status
Simulation time 519400740 ps
CPU time 1.39 seconds
Started May 12 04:08:52 PM PDT 24
Finished May 12 04:08:53 PM PDT 24
Peak memory 201256 kb
Host smart-6360ac9a-6359-4a87-8ec0-a15e5d355a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458215448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.458215448
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3732857220
Short name T816
Test name
Test status
Simulation time 448815484 ps
CPU time 1.78 seconds
Started May 12 04:08:54 PM PDT 24
Finished May 12 04:08:56 PM PDT 24
Peak memory 201216 kb
Host smart-36475f48-f584-4d8b-bdcb-a34d8383e6de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732857220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3732857220
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.306087854
Short name T47
Test name
Test status
Simulation time 2242921064 ps
CPU time 2.06 seconds
Started May 12 04:08:52 PM PDT 24
Finished May 12 04:08:54 PM PDT 24
Peak memory 201328 kb
Host smart-f42ebd2d-8c08-4ca2-81c1-f549fff19fd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306087854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.306087854
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2335652215
Short name T64
Test name
Test status
Simulation time 841728897 ps
CPU time 1.81 seconds
Started May 12 04:08:53 PM PDT 24
Finished May 12 04:08:56 PM PDT 24
Peak memory 201524 kb
Host smart-83c1bdcc-f9d5-4e9e-85ad-e9fb95db9100
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335652215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2335652215
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2465297772
Short name T843
Test name
Test status
Simulation time 8977406088 ps
CPU time 25.3 seconds
Started May 12 04:08:51 PM PDT 24
Finished May 12 04:09:17 PM PDT 24
Peak memory 201508 kb
Host smart-0d233f85-cebe-4baf-be0f-1eee72827d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465297772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2465297772
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4262725141
Short name T876
Test name
Test status
Simulation time 498948712 ps
CPU time 1.32 seconds
Started May 12 04:08:52 PM PDT 24
Finished May 12 04:08:54 PM PDT 24
Peak memory 201272 kb
Host smart-781ee025-c00c-42b3-b92b-032c85f42b2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262725141 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4262725141
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1282613508
Short name T853
Test name
Test status
Simulation time 529391968 ps
CPU time 2.11 seconds
Started May 12 04:08:54 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201236 kb
Host smart-396c24eb-a5b2-4589-a562-518ee45e9eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282613508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1282613508
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.705541280
Short name T811
Test name
Test status
Simulation time 425910812 ps
CPU time 1.21 seconds
Started May 12 04:09:02 PM PDT 24
Finished May 12 04:09:04 PM PDT 24
Peak memory 201176 kb
Host smart-670fb825-3e5e-4c44-9135-681c787f1cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705541280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.705541280
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3105900589
Short name T813
Test name
Test status
Simulation time 2323122122 ps
CPU time 3.66 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:08 PM PDT 24
Peak memory 201244 kb
Host smart-f79064a4-b539-4424-90e6-a5d470a51a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105900589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3105900589
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1308589998
Short name T875
Test name
Test status
Simulation time 519197295 ps
CPU time 3.53 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:07 PM PDT 24
Peak memory 217480 kb
Host smart-28dca4d1-2c3d-4b47-9a86-c516e583ced1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308589998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1308589998
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1369311151
Short name T66
Test name
Test status
Simulation time 4595422882 ps
CPU time 4.36 seconds
Started May 12 04:08:54 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201460 kb
Host smart-b0c96bf6-593c-4d06-bc10-f63b00f02a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369311151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1369311151
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.380317638
Short name T880
Test name
Test status
Simulation time 406405527 ps
CPU time 1.22 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201228 kb
Host smart-947354d0-756d-46a9-aeb8-a110f4d7c6df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380317638 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.380317638
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.48402276
Short name T92
Test name
Test status
Simulation time 352992377 ps
CPU time 1.69 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201192 kb
Host smart-6436adcd-51f5-4be6-b42a-a8e8d640765d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48402276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.48402276
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.105441484
Short name T916
Test name
Test status
Simulation time 338179009 ps
CPU time 0.81 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201172 kb
Host smart-82c1341e-f8db-4e67-b1cb-c7471e3a90eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105441484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.105441484
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1213217290
Short name T894
Test name
Test status
Simulation time 5120460262 ps
CPU time 7.53 seconds
Started May 12 04:09:02 PM PDT 24
Finished May 12 04:09:11 PM PDT 24
Peak memory 201452 kb
Host smart-bb35fe5f-bafe-4d4c-842f-86112749ca8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213217290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1213217290
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.866582598
Short name T312
Test name
Test status
Simulation time 7878654687 ps
CPU time 21.32 seconds
Started May 12 04:08:54 PM PDT 24
Finished May 12 04:09:16 PM PDT 24
Peak memory 201520 kb
Host smart-117c89b4-ca60-4c95-9bb2-5df1dbfcd3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866582598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.866582598
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.131264713
Short name T856
Test name
Test status
Simulation time 518331750 ps
CPU time 1.22 seconds
Started May 12 04:08:58 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201244 kb
Host smart-3fd18a1c-9433-461e-8c27-32ae32ee5819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131264713 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.131264713
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3085770374
Short name T104
Test name
Test status
Simulation time 552335031 ps
CPU time 1.11 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201252 kb
Host smart-fcf780c8-8b47-4a61-a82a-952eb5847252
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085770374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3085770374
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.724798663
Short name T839
Test name
Test status
Simulation time 472495385 ps
CPU time 0.88 seconds
Started May 12 04:08:55 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201264 kb
Host smart-d2248275-2374-4bf0-b8a7-ffde0dd85419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724798663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.724798663
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1206119454
Short name T896
Test name
Test status
Simulation time 2750509426 ps
CPU time 9.4 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:06 PM PDT 24
Peak memory 201300 kb
Host smart-28bebb6a-ea8a-45c9-a716-5cb05de4ecd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206119454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1206119454
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3461171677
Short name T823
Test name
Test status
Simulation time 490566546 ps
CPU time 2.26 seconds
Started May 12 04:08:54 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201516 kb
Host smart-5b124d9f-dd58-4bcd-80a7-b5c3e70f4a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461171677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3461171677
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1345464158
Short name T50
Test name
Test status
Simulation time 4383658612 ps
CPU time 11.07 seconds
Started May 12 04:08:50 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201524 kb
Host smart-b26ebac4-8adf-4f85-b3f4-3cc198b09e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345464158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1345464158
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1110560266
Short name T836
Test name
Test status
Simulation time 417960492 ps
CPU time 1.17 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201220 kb
Host smart-7fe72d96-6ea5-47f9-bc77-10f7c867474e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110560266 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1110560266
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1315908685
Short name T885
Test name
Test status
Simulation time 610135732 ps
CPU time 1 seconds
Started May 12 04:08:53 PM PDT 24
Finished May 12 04:08:55 PM PDT 24
Peak memory 201228 kb
Host smart-b7a6e2db-b92d-4a59-bb8b-0eb003547ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315908685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1315908685
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.542094185
Short name T879
Test name
Test status
Simulation time 486635332 ps
CPU time 0.94 seconds
Started May 12 04:09:01 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201228 kb
Host smart-d1c42eea-08bd-44d4-b7fa-fb76beecb6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542094185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.542094185
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3769839622
Short name T873
Test name
Test status
Simulation time 2807391111 ps
CPU time 8.88 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201320 kb
Host smart-dced3b10-5d17-4cc2-9d0c-932defdb57b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769839622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3769839622
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1798409934
Short name T65
Test name
Test status
Simulation time 429575878 ps
CPU time 2.85 seconds
Started May 12 04:09:01 PM PDT 24
Finished May 12 04:09:04 PM PDT 24
Peak memory 217820 kb
Host smart-f449dc1a-bee9-4b7c-93cb-bbd78da30680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798409934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1798409934
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1047310813
Short name T870
Test name
Test status
Simulation time 9043517436 ps
CPU time 7.98 seconds
Started May 12 04:08:55 PM PDT 24
Finished May 12 04:09:04 PM PDT 24
Peak memory 201504 kb
Host smart-08bdd935-3f74-4b56-9f16-a1c2f5707449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047310813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1047310813
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2623565798
Short name T895
Test name
Test status
Simulation time 478856505 ps
CPU time 1.84 seconds
Started May 12 04:08:55 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201300 kb
Host smart-4a8ed582-87b0-481a-b63d-7759cd16808e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623565798 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2623565798
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3636669719
Short name T94
Test name
Test status
Simulation time 566965791 ps
CPU time 1.16 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201184 kb
Host smart-23b47b98-7842-452e-8349-ef58e963c855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636669719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3636669719
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.818436486
Short name T882
Test name
Test status
Simulation time 385097424 ps
CPU time 1.38 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201260 kb
Host smart-b2c92bda-5f17-4d0c-a536-69927b9e6c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818436486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.818436486
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3389319606
Short name T911
Test name
Test status
Simulation time 4480850332 ps
CPU time 2 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201512 kb
Host smart-409d094c-9e31-4d33-b789-f26b81845db9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389319606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3389319606
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1053670754
Short name T54
Test name
Test status
Simulation time 349791796 ps
CPU time 1.38 seconds
Started May 12 04:09:02 PM PDT 24
Finished May 12 04:09:04 PM PDT 24
Peak memory 201424 kb
Host smart-6504e0d9-91b4-48bd-aab8-3da87e35cb93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053670754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1053670754
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2319729671
Short name T907
Test name
Test status
Simulation time 4340837570 ps
CPU time 7.09 seconds
Started May 12 04:08:58 PM PDT 24
Finished May 12 04:09:06 PM PDT 24
Peak memory 201504 kb
Host smart-de358368-fee5-4dfa-9e8d-475aa1550c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319729671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2319729671
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.441924886
Short name T869
Test name
Test status
Simulation time 511400950 ps
CPU time 2.26 seconds
Started May 12 04:08:55 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201296 kb
Host smart-f2b553c1-7980-4167-8164-6a1a4b304459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441924886 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.441924886
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1543704812
Short name T900
Test name
Test status
Simulation time 480085524 ps
CPU time 1.81 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201212 kb
Host smart-b6adafb8-88a2-474e-8a90-e0682842a18d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543704812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1543704812
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.260993896
Short name T807
Test name
Test status
Simulation time 352983850 ps
CPU time 1.46 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201256 kb
Host smart-36d9f9be-98f4-4457-ac7a-1973d94cc68a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260993896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.260993896
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2652397608
Short name T906
Test name
Test status
Simulation time 1773539220 ps
CPU time 3.03 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:09:01 PM PDT 24
Peak memory 201240 kb
Host smart-2ad094f3-4e35-483d-a1eb-b3744b26f96a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652397608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2652397608
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1891451798
Short name T53
Test name
Test status
Simulation time 655183713 ps
CPU time 4.12 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:01 PM PDT 24
Peak memory 217348 kb
Host smart-f4faea07-0b86-4bfb-800e-60ec0f5ce9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891451798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1891451798
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1935699354
Short name T890
Test name
Test status
Simulation time 4912225070 ps
CPU time 3.03 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:09:01 PM PDT 24
Peak memory 201524 kb
Host smart-1175fc6a-2be6-42e1-8139-147a934fce90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935699354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1935699354
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3630397811
Short name T892
Test name
Test status
Simulation time 362867537 ps
CPU time 0.97 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201288 kb
Host smart-ba804d04-ed89-4c9a-9006-edbccbbb263e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630397811 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3630397811
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.525850990
Short name T827
Test name
Test status
Simulation time 366851466 ps
CPU time 0.94 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201212 kb
Host smart-eac04685-deaa-45a3-ae3a-a94868886310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525850990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.525850990
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.29148696
Short name T815
Test name
Test status
Simulation time 332864453 ps
CPU time 0.85 seconds
Started May 12 04:09:00 PM PDT 24
Finished May 12 04:09:01 PM PDT 24
Peak memory 201212 kb
Host smart-61a43d91-ca5d-47e8-b73a-40c82f65b332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.29148696
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2032709270
Short name T902
Test name
Test status
Simulation time 2513727796 ps
CPU time 6.83 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201312 kb
Host smart-af64de53-759f-48cf-83d6-016c5caa5624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032709270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2032709270
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.711104538
Short name T855
Test name
Test status
Simulation time 538022741 ps
CPU time 1.79 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:10 PM PDT 24
Peak memory 201492 kb
Host smart-c41a39f6-9d42-4c81-8111-93e1f2fa48c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711104538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.711104538
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3458834407
Short name T904
Test name
Test status
Simulation time 4492392256 ps
CPU time 13.39 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:17 PM PDT 24
Peak memory 201516 kb
Host smart-35bc28a2-b2e2-4f11-b390-48bd328704cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458834407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3458834407
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.490072797
Short name T819
Test name
Test status
Simulation time 606220502 ps
CPU time 2.59 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:11 PM PDT 24
Peak memory 201316 kb
Host smart-ba234c44-1fe8-4a5c-a5ce-1e81c44c7141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490072797 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.490072797
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2009361869
Short name T802
Test name
Test status
Simulation time 474819744 ps
CPU time 0.92 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201276 kb
Host smart-1ae60837-16db-4da5-a383-e88b03a938b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009361869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2009361869
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3888186932
Short name T105
Test name
Test status
Simulation time 2272840795 ps
CPU time 8.45 seconds
Started May 12 04:09:00 PM PDT 24
Finished May 12 04:09:09 PM PDT 24
Peak memory 201312 kb
Host smart-9c24c2b1-402e-4cdc-8a8f-1869d6705ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888186932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3888186932
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2603293578
Short name T893
Test name
Test status
Simulation time 503388805 ps
CPU time 2.57 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:06 PM PDT 24
Peak memory 201512 kb
Host smart-07a64505-0077-482d-bbff-d032d74a4fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603293578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2603293578
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.308263192
Short name T315
Test name
Test status
Simulation time 8469934912 ps
CPU time 22.48 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:09:19 PM PDT 24
Peak memory 201564 kb
Host smart-9ecb3700-570d-45b9-957b-7b03f49d54f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308263192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.308263192
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.816069837
Short name T99
Test name
Test status
Simulation time 1237556995 ps
CPU time 2.6 seconds
Started May 12 04:08:40 PM PDT 24
Finished May 12 04:08:44 PM PDT 24
Peak memory 201472 kb
Host smart-b693d15e-6c1b-42c9-ae80-0ea677852f42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816069837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.816069837
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.766694350
Short name T102
Test name
Test status
Simulation time 49747112235 ps
CPU time 112.08 seconds
Started May 12 04:08:39 PM PDT 24
Finished May 12 04:10:32 PM PDT 24
Peak memory 201584 kb
Host smart-08cf1b14-9311-4c9b-9684-fd346db607af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766694350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.766694350
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.865911816
Short name T91
Test name
Test status
Simulation time 931497281 ps
CPU time 2.92 seconds
Started May 12 04:08:42 PM PDT 24
Finished May 12 04:08:45 PM PDT 24
Peak memory 201224 kb
Host smart-d456d295-7699-4873-835e-ba7781f32770
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865911816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.865911816
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.226135004
Short name T887
Test name
Test status
Simulation time 530088069 ps
CPU time 1.52 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:48 PM PDT 24
Peak memory 210804 kb
Host smart-a77359bb-3476-475a-81bb-4f72ef32d656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226135004 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.226135004
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1178326177
Short name T45
Test name
Test status
Simulation time 499953909 ps
CPU time 2.08 seconds
Started May 12 04:08:40 PM PDT 24
Finished May 12 04:08:43 PM PDT 24
Peak memory 201248 kb
Host smart-293d9ab0-e761-4c93-9687-eb5fc3d2aa4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178326177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1178326177
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2914506497
Short name T877
Test name
Test status
Simulation time 330716319 ps
CPU time 1.46 seconds
Started May 12 04:08:39 PM PDT 24
Finished May 12 04:08:41 PM PDT 24
Peak memory 201252 kb
Host smart-ea67f1de-7214-4935-aa1b-460d0161686b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914506497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2914506497
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1759246295
Short name T46
Test name
Test status
Simulation time 5352956627 ps
CPU time 12.69 seconds
Started May 12 04:08:41 PM PDT 24
Finished May 12 04:08:54 PM PDT 24
Peak memory 201604 kb
Host smart-b396787c-9557-4f5e-8452-52a2bb3f46ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759246295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1759246295
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1155112620
Short name T846
Test name
Test status
Simulation time 887140214 ps
CPU time 3.32 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 210684 kb
Host smart-3e42671d-d97e-4260-9ee2-7419e0f3be0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155112620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1155112620
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.21539707
Short name T897
Test name
Test status
Simulation time 452662146 ps
CPU time 0.95 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201224 kb
Host smart-76b3f360-3db8-4088-a523-c50a3a4d1666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.21539707
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2975632155
Short name T814
Test name
Test status
Simulation time 428023987 ps
CPU time 1.57 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:10 PM PDT 24
Peak memory 201252 kb
Host smart-b722b5f4-a9ad-4f50-82e0-739f6d40f806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975632155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2975632155
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3079325542
Short name T805
Test name
Test status
Simulation time 338192707 ps
CPU time 0.87 seconds
Started May 12 04:08:59 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201184 kb
Host smart-1265ea35-51e9-4eae-9582-be6e6330f5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079325542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3079325542
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3170194697
Short name T798
Test name
Test status
Simulation time 528728683 ps
CPU time 2.08 seconds
Started May 12 04:09:00 PM PDT 24
Finished May 12 04:09:03 PM PDT 24
Peak memory 201184 kb
Host smart-870c6c1c-9f6d-430b-8bae-71ca5432c0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170194697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3170194697
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.654902799
Short name T857
Test name
Test status
Simulation time 398454558 ps
CPU time 1.14 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:10 PM PDT 24
Peak memory 201048 kb
Host smart-184ce9bf-ccf5-4d0a-9522-86372247d151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654902799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.654902799
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.838658013
Short name T800
Test name
Test status
Simulation time 308976523 ps
CPU time 1.31 seconds
Started May 12 04:08:57 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201268 kb
Host smart-c908dd3d-dba9-407e-bbd0-bad9171d4acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838658013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.838658013
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3334562134
Short name T914
Test name
Test status
Simulation time 530132715 ps
CPU time 0.79 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:09 PM PDT 24
Peak memory 201136 kb
Host smart-ea146c2d-183f-4130-9d29-1c7e46a08294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334562134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3334562134
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1972831492
Short name T810
Test name
Test status
Simulation time 340989599 ps
CPU time 1.45 seconds
Started May 12 04:08:58 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201196 kb
Host smart-d9ac235a-0b32-4aa7-8fa0-2de7d4547e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972831492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1972831492
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.24297917
Short name T886
Test name
Test status
Simulation time 381261612 ps
CPU time 0.98 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201184 kb
Host smart-c060aa12-7bb5-476d-bb52-2dcbbf70df32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24297917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.24297917
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2768502953
Short name T830
Test name
Test status
Simulation time 498590983 ps
CPU time 1.22 seconds
Started May 12 04:08:58 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201240 kb
Host smart-7d35bc39-5ceb-4925-bc27-9bf60a3f6387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768502953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2768502953
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2220577038
Short name T107
Test name
Test status
Simulation time 954877742 ps
CPU time 3 seconds
Started May 12 04:08:41 PM PDT 24
Finished May 12 04:08:44 PM PDT 24
Peak memory 201364 kb
Host smart-a83a9c8f-3772-48a2-b101-481b788a7683
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220577038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2220577038
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2517556867
Short name T820
Test name
Test status
Simulation time 26492442645 ps
CPU time 11.95 seconds
Started May 12 04:08:44 PM PDT 24
Finished May 12 04:08:57 PM PDT 24
Peak memory 201456 kb
Host smart-a36e2929-6ac4-4e7c-b2f2-c814be93ea02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517556867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2517556867
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1434218645
Short name T881
Test name
Test status
Simulation time 980067929 ps
CPU time 0.91 seconds
Started May 12 04:08:41 PM PDT 24
Finished May 12 04:08:43 PM PDT 24
Peak memory 201268 kb
Host smart-262ee625-2e3f-4549-a321-dd755aa40f41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434218645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1434218645
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3895225550
Short name T872
Test name
Test status
Simulation time 453024090 ps
CPU time 1.12 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:46 PM PDT 24
Peak memory 201264 kb
Host smart-985d259c-aa3e-41c8-bce6-6310dbd7f0de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895225550 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3895225550
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1177306329
Short name T852
Test name
Test status
Simulation time 545105027 ps
CPU time 1.87 seconds
Started May 12 04:08:41 PM PDT 24
Finished May 12 04:08:44 PM PDT 24
Peak memory 201228 kb
Host smart-9bbfe90a-f932-4ffb-8db6-6d185cb09cc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177306329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1177306329
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2039573479
Short name T912
Test name
Test status
Simulation time 326270512 ps
CPU time 0.88 seconds
Started May 12 04:08:44 PM PDT 24
Finished May 12 04:08:45 PM PDT 24
Peak memory 201244 kb
Host smart-478b1252-8c3c-4581-bcc9-86d7de53fc45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039573479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2039573479
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3268168530
Short name T891
Test name
Test status
Simulation time 3073708341 ps
CPU time 7.86 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:54 PM PDT 24
Peak memory 201476 kb
Host smart-5c8fa7ca-cfe2-4d8f-a16d-ffa5bffd4f46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268168530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3268168530
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3769495159
Short name T51
Test name
Test status
Simulation time 9209542014 ps
CPU time 4.45 seconds
Started May 12 04:08:43 PM PDT 24
Finished May 12 04:08:48 PM PDT 24
Peak memory 201516 kb
Host smart-13c5cb85-7a00-414a-93a3-d610d4693d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769495159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3769495159
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3000535755
Short name T898
Test name
Test status
Simulation time 458150320 ps
CPU time 1.2 seconds
Started May 12 04:08:56 PM PDT 24
Finished May 12 04:08:59 PM PDT 24
Peak memory 201232 kb
Host smart-2d4b7e6c-b48a-4946-9e77-bfade03abe3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000535755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3000535755
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3720764346
Short name T871
Test name
Test status
Simulation time 396448220 ps
CPU time 0.88 seconds
Started May 12 04:09:06 PM PDT 24
Finished May 12 04:09:08 PM PDT 24
Peak memory 201212 kb
Host smart-1c72baaf-f329-4e49-b525-7933e2f55e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720764346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3720764346
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3402215861
Short name T858
Test name
Test status
Simulation time 427525725 ps
CPU time 1.67 seconds
Started May 12 04:09:02 PM PDT 24
Finished May 12 04:09:04 PM PDT 24
Peak memory 201236 kb
Host smart-06474213-0075-4f8f-b903-65f1c1db6121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402215861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3402215861
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.623989165
Short name T809
Test name
Test status
Simulation time 494515844 ps
CPU time 0.82 seconds
Started May 12 04:09:01 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201248 kb
Host smart-cab22089-8b67-4f4b-b1e4-87cad0f84fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623989165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.623989165
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.627899111
Short name T842
Test name
Test status
Simulation time 386339197 ps
CPU time 1.1 seconds
Started May 12 04:08:59 PM PDT 24
Finished May 12 04:09:01 PM PDT 24
Peak memory 201224 kb
Host smart-0a23e5dc-0110-4c12-a50a-cc836e887317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627899111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.627899111
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2086838270
Short name T905
Test name
Test status
Simulation time 423628937 ps
CPU time 0.7 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:12 PM PDT 24
Peak memory 201220 kb
Host smart-bbf5d344-1502-49bc-a124-dc2477b672ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086838270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2086838270
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.900082214
Short name T799
Test name
Test status
Simulation time 398705166 ps
CPU time 1.38 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:09:10 PM PDT 24
Peak memory 201256 kb
Host smart-1a5f8591-6e29-4b03-af38-7c35c859eace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900082214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.900082214
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.383882274
Short name T866
Test name
Test status
Simulation time 310496603 ps
CPU time 0.84 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:09 PM PDT 24
Peak memory 201244 kb
Host smart-832d4550-989f-49ca-8b85-e9d4bf694acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383882274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.383882274
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1793616244
Short name T861
Test name
Test status
Simulation time 310859938 ps
CPU time 1.02 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:09:10 PM PDT 24
Peak memory 201104 kb
Host smart-d918e821-350f-4ed4-b3b4-20b018e14529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793616244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1793616244
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3490257894
Short name T845
Test name
Test status
Simulation time 363457349 ps
CPU time 1.49 seconds
Started May 12 04:09:00 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201232 kb
Host smart-9b97c03b-b383-4abd-894d-29038cf0ab5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490257894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3490257894
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.379180538
Short name T915
Test name
Test status
Simulation time 590327977 ps
CPU time 2.06 seconds
Started May 12 04:08:43 PM PDT 24
Finished May 12 04:08:46 PM PDT 24
Peak memory 201472 kb
Host smart-70b44ba4-6940-47ce-9a3d-547d777fa3b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379180538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.379180538
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4041241212
Short name T101
Test name
Test status
Simulation time 53070816890 ps
CPU time 139.57 seconds
Started May 12 04:08:44 PM PDT 24
Finished May 12 04:11:04 PM PDT 24
Peak memory 201532 kb
Host smart-b76617be-d350-498e-a19f-e5e4b22574a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041241212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4041241212
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2146277866
Short name T883
Test name
Test status
Simulation time 1464988657 ps
CPU time 1.61 seconds
Started May 12 04:08:43 PM PDT 24
Finished May 12 04:08:45 PM PDT 24
Peak memory 201216 kb
Host smart-92218000-1a17-4693-9678-04a577c624f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146277866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2146277866
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2147502605
Short name T888
Test name
Test status
Simulation time 674527377 ps
CPU time 2.45 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:48 PM PDT 24
Peak memory 201284 kb
Host smart-f44001c1-1378-4c04-928f-96283472bf03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147502605 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2147502605
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1864616539
Short name T917
Test name
Test status
Simulation time 419869184 ps
CPU time 0.96 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:47 PM PDT 24
Peak memory 201272 kb
Host smart-f89e68cf-5a19-450d-a163-709b8dd4a770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864616539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1864616539
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3061129192
Short name T865
Test name
Test status
Simulation time 523761178 ps
CPU time 1.84 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:48 PM PDT 24
Peak memory 201236 kb
Host smart-af056830-8903-419a-a3db-a0f7656c4e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061129192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3061129192
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2479370530
Short name T831
Test name
Test status
Simulation time 2767867587 ps
CPU time 5.19 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 201300 kb
Host smart-3eefbb68-0bff-4c5a-9622-ae0474cc9aef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479370530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2479370530
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2129847599
Short name T901
Test name
Test status
Simulation time 563212847 ps
CPU time 3.57 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 217800 kb
Host smart-c2658ba4-0c6c-4663-90f2-609a88651c75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129847599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2129847599
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.350128373
Short name T867
Test name
Test status
Simulation time 9033764241 ps
CPU time 4.44 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 201444 kb
Host smart-b32e0a8e-45f3-4547-9543-3709bde27716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350128373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.350128373
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.438367181
Short name T829
Test name
Test status
Simulation time 490205486 ps
CPU time 1.17 seconds
Started May 12 04:09:01 PM PDT 24
Finished May 12 04:09:03 PM PDT 24
Peak memory 201208 kb
Host smart-5c2a614a-2e22-4c39-a78b-eddfe609dd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438367181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.438367181
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.18051718
Short name T806
Test name
Test status
Simulation time 457454056 ps
CPU time 1.16 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201220 kb
Host smart-0c286770-391e-4fda-a6ec-6476b41922f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18051718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.18051718
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2811790767
Short name T825
Test name
Test status
Simulation time 356877489 ps
CPU time 0.81 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:05 PM PDT 24
Peak memory 201212 kb
Host smart-80d084e3-2ad9-461a-a5f1-90a267d871b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811790767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2811790767
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3428703055
Short name T826
Test name
Test status
Simulation time 354438181 ps
CPU time 0.85 seconds
Started May 12 04:09:00 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201236 kb
Host smart-a0bc7e84-1433-4d37-988a-79de23b6cfa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428703055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3428703055
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.801273690
Short name T847
Test name
Test status
Simulation time 536760594 ps
CPU time 1.09 seconds
Started May 12 04:09:06 PM PDT 24
Finished May 12 04:09:07 PM PDT 24
Peak memory 201268 kb
Host smart-b5486c7f-782b-4827-a0d0-a84c35c12824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801273690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.801273690
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3918319600
Short name T834
Test name
Test status
Simulation time 521401003 ps
CPU time 1.87 seconds
Started May 12 04:08:58 PM PDT 24
Finished May 12 04:09:01 PM PDT 24
Peak memory 201260 kb
Host smart-42615795-e1e2-4a58-afa4-be7722cfe19f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918319600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3918319600
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3054607923
Short name T818
Test name
Test status
Simulation time 471815390 ps
CPU time 1.19 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:09 PM PDT 24
Peak memory 201236 kb
Host smart-1922a905-1f2f-44da-877f-9def9103e010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054607923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3054607923
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2252008888
Short name T863
Test name
Test status
Simulation time 446779860 ps
CPU time 1.17 seconds
Started May 12 04:09:00 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201232 kb
Host smart-5e7bb3e6-2b7c-404f-b20f-ad01b0312921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252008888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2252008888
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.504292624
Short name T804
Test name
Test status
Simulation time 325075703 ps
CPU time 0.83 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:09:11 PM PDT 24
Peak memory 201252 kb
Host smart-2e34fa9d-2537-4921-aa09-107dccf77d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504292624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.504292624
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2291367301
Short name T833
Test name
Test status
Simulation time 454595954 ps
CPU time 1.71 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:09:11 PM PDT 24
Peak memory 201216 kb
Host smart-48ab82f2-cef6-4bf5-bac3-1a16a5008e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291367301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2291367301
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1186980799
Short name T868
Test name
Test status
Simulation time 499091391 ps
CPU time 2.18 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201296 kb
Host smart-1de6b24f-f418-40c1-8c26-f118ce86e3fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186980799 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1186980799
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.762503452
Short name T100
Test name
Test status
Simulation time 324682101 ps
CPU time 0.99 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:47 PM PDT 24
Peak memory 201240 kb
Host smart-f72e85bd-5fd2-400e-a2f1-752fa8eb38e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762503452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.762503452
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3748402398
Short name T860
Test name
Test status
Simulation time 431954459 ps
CPU time 0.9 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:47 PM PDT 24
Peak memory 201236 kb
Host smart-0d7bb4a4-223b-475b-9bb8-b913735fbc24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748402398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3748402398
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4272883167
Short name T106
Test name
Test status
Simulation time 4905770653 ps
CPU time 10.73 seconds
Started May 12 04:08:47 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201484 kb
Host smart-9398029e-be73-4046-9306-76a13fd28729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272883167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4272883167
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1022046087
Short name T838
Test name
Test status
Simulation time 731350882 ps
CPU time 3.16 seconds
Started May 12 04:08:47 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 217520 kb
Host smart-32a4876c-b86a-4f6b-9232-20ec03e943a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022046087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1022046087
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.35467192
Short name T76
Test name
Test status
Simulation time 744144407 ps
CPU time 1.49 seconds
Started May 12 04:08:47 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201248 kb
Host smart-a27abd0b-6548-49f5-bb2b-89ab81f9645f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35467192 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.35467192
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3677590585
Short name T88
Test name
Test status
Simulation time 427541443 ps
CPU time 1.76 seconds
Started May 12 04:08:47 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201248 kb
Host smart-f12ced56-7d56-4ea3-81d7-c010e102e5ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677590585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3677590585
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2545340591
Short name T828
Test name
Test status
Simulation time 486185099 ps
CPU time 1 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:47 PM PDT 24
Peak memory 201240 kb
Host smart-42bfec5e-04ae-491a-9b38-a12c5ebb66fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545340591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2545340591
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4187729219
Short name T103
Test name
Test status
Simulation time 2600558479 ps
CPU time 5.22 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:55 PM PDT 24
Peak memory 201312 kb
Host smart-00b635fc-1310-4458-a574-152c93c64e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187729219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4187729219
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.842165719
Short name T841
Test name
Test status
Simulation time 578567956 ps
CPU time 3.04 seconds
Started May 12 04:08:45 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201484 kb
Host smart-6241efad-3cb3-4188-a8b7-bd40952a9b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842165719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.842165719
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2369333501
Short name T52
Test name
Test status
Simulation time 4422065485 ps
CPU time 4.58 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:54 PM PDT 24
Peak memory 201488 kb
Host smart-6e57377a-73dd-441e-853d-f9a8206e75df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369333501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2369333501
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2676101705
Short name T77
Test name
Test status
Simulation time 492706792 ps
CPU time 1.26 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201324 kb
Host smart-38dd49c7-e61b-4a50-898e-02381b2d3650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676101705 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2676101705
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1131901291
Short name T903
Test name
Test status
Simulation time 512401047 ps
CPU time 1.49 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201232 kb
Host smart-f4d83687-99f7-431d-92a9-801dbe5d242e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131901291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1131901291
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3052642696
Short name T878
Test name
Test status
Simulation time 452072385 ps
CPU time 0.87 seconds
Started May 12 04:08:46 PM PDT 24
Finished May 12 04:08:48 PM PDT 24
Peak memory 201252 kb
Host smart-3b9e93c8-43ed-45a5-9d11-caeac62f4c5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052642696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3052642696
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1589204155
Short name T832
Test name
Test status
Simulation time 2221876790 ps
CPU time 1.75 seconds
Started May 12 04:08:44 PM PDT 24
Finished May 12 04:08:46 PM PDT 24
Peak memory 201316 kb
Host smart-2506f496-b420-4737-b425-cb79e7c74fcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589204155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1589204155
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3171264199
Short name T63
Test name
Test status
Simulation time 348105230 ps
CPU time 1.6 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 201536 kb
Host smart-c5a060dd-dbe9-464f-a987-c355c99a093a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171264199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3171264199
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3879203921
Short name T844
Test name
Test status
Simulation time 4898337978 ps
CPU time 4.24 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:54 PM PDT 24
Peak memory 201464 kb
Host smart-a80a30db-0f9e-41a6-9cac-b0996c324e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879203921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3879203921
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1004619984
Short name T822
Test name
Test status
Simulation time 378566794 ps
CPU time 1.75 seconds
Started May 12 04:08:50 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 201284 kb
Host smart-dc7ee3ab-7b03-4f0c-ab36-7b15a84b6514
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004619984 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1004619984
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2798724972
Short name T96
Test name
Test status
Simulation time 435266113 ps
CPU time 0.97 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:50 PM PDT 24
Peak memory 201260 kb
Host smart-89f5fe71-35f6-4043-a771-703d44eb9d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798724972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2798724972
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.69147465
Short name T821
Test name
Test status
Simulation time 515415055 ps
CPU time 0.98 seconds
Started May 12 04:08:51 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 201168 kb
Host smart-b48eb2bd-5c44-4404-ae2e-3b9ac4c11dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69147465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.69147465
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3877795718
Short name T837
Test name
Test status
Simulation time 4465629174 ps
CPU time 10.73 seconds
Started May 12 04:08:48 PM PDT 24
Finished May 12 04:09:00 PM PDT 24
Peak memory 201436 kb
Host smart-85cde670-d552-43d9-b634-d775edabd0d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877795718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3877795718
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.946766438
Short name T824
Test name
Test status
Simulation time 394235976 ps
CPU time 2.2 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 201512 kb
Host smart-9a4636b3-68eb-47d9-bbb3-52a2b409ba75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946766438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.946766438
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1231560168
Short name T859
Test name
Test status
Simulation time 7907694717 ps
CPU time 6.65 seconds
Started May 12 04:09:03 PM PDT 24
Finished May 12 04:09:10 PM PDT 24
Peak memory 201416 kb
Host smart-c6b38e29-1c83-4d32-a1f2-26e93301fea9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231560168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1231560168
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1889883248
Short name T854
Test name
Test status
Simulation time 339742440 ps
CPU time 1.04 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:51 PM PDT 24
Peak memory 201332 kb
Host smart-95544a4d-37fd-4cfb-805f-71b8883c5ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889883248 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1889883248
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4156592229
Short name T87
Test name
Test status
Simulation time 583942954 ps
CPU time 1 seconds
Started May 12 04:08:47 PM PDT 24
Finished May 12 04:08:49 PM PDT 24
Peak memory 201288 kb
Host smart-57c7bcc3-4a92-405c-b3a5-6ef196d25462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156592229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4156592229
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.98253788
Short name T803
Test name
Test status
Simulation time 516141968 ps
CPU time 0.91 seconds
Started May 12 04:09:02 PM PDT 24
Finished May 12 04:09:04 PM PDT 24
Peak memory 201152 kb
Host smart-cc229a83-c236-414d-a5ee-3a7eb653fd95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98253788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.98253788
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2805059583
Short name T908
Test name
Test status
Simulation time 2290040693 ps
CPU time 9.62 seconds
Started May 12 04:08:47 PM PDT 24
Finished May 12 04:08:58 PM PDT 24
Peak memory 201260 kb
Host smart-608be548-e1bb-4af7-bfb2-4e326a6190ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805059583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2805059583
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1860728503
Short name T851
Test name
Test status
Simulation time 759734454 ps
CPU time 2.18 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:08:52 PM PDT 24
Peak memory 209688 kb
Host smart-56ad64c1-61a4-480e-b5f7-d45419b075ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860728503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1860728503
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2533660612
Short name T313
Test name
Test status
Simulation time 4378885941 ps
CPU time 12.08 seconds
Started May 12 04:08:49 PM PDT 24
Finished May 12 04:09:02 PM PDT 24
Peak memory 201636 kb
Host smart-6798aa07-01f6-4fd1-8e69-f5af8ab63bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533660612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2533660612
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2992428212
Short name T616
Test name
Test status
Simulation time 477358694 ps
CPU time 1.73 seconds
Started May 12 04:09:13 PM PDT 24
Finished May 12 04:09:15 PM PDT 24
Peak memory 201932 kb
Host smart-1d50dadf-2f90-44bc-8573-0b5bb0ff5c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992428212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2992428212
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3371887444
Short name T678
Test name
Test status
Simulation time 162553859008 ps
CPU time 106.5 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:10:57 PM PDT 24
Peak memory 202316 kb
Host smart-9bfb2b5e-e379-4c04-92bf-cecb8790b1ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371887444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3371887444
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3657243259
Short name T603
Test name
Test status
Simulation time 328681319418 ps
CPU time 197.52 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:12:28 PM PDT 24
Peak memory 202276 kb
Host smart-3e5788a9-a698-4df4-aefc-2d5a416ecb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657243259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3657243259
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1369228641
Short name T683
Test name
Test status
Simulation time 484627916594 ps
CPU time 363.96 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:15:22 PM PDT 24
Peak memory 202288 kb
Host smart-840b953f-fc80-4c0d-bbff-e7331abbe695
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369228641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1369228641
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4256297187
Short name T202
Test name
Test status
Simulation time 492630064408 ps
CPU time 1093.14 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:27:22 PM PDT 24
Peak memory 202388 kb
Host smart-fd16336c-00a1-4563-aa6c-5e0197dd56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256297187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4256297187
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1294226788
Short name T447
Test name
Test status
Simulation time 333815519168 ps
CPU time 412.06 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:15:59 PM PDT 24
Peak memory 202356 kb
Host smart-fefc5222-9646-439d-a6f7-53dff3708556
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294226788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1294226788
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4221449151
Short name T224
Test name
Test status
Simulation time 362868477551 ps
CPU time 180.55 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:12:09 PM PDT 24
Peak memory 202360 kb
Host smart-ae486372-cb0a-41e0-bed8-8dc4cf3e046d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221449151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4221449151
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2072811688
Short name T383
Test name
Test status
Simulation time 591665196607 ps
CPU time 617.17 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:19:35 PM PDT 24
Peak memory 202312 kb
Host smart-30923010-9f24-4ef7-9ca2-5232e7d8a467
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072811688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2072811688
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.917501641
Short name T548
Test name
Test status
Simulation time 126280495600 ps
CPU time 705.15 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:20:57 PM PDT 24
Peak memory 202752 kb
Host smart-f6af87bd-baaa-4bd7-8d31-09e4abed5028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917501641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.917501641
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2294720327
Short name T432
Test name
Test status
Simulation time 43808914365 ps
CPU time 25.79 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:09:41 PM PDT 24
Peak memory 202092 kb
Host smart-c7d02316-19d4-45c0-9577-cacbd592d9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294720327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2294720327
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4162879431
Short name T456
Test name
Test status
Simulation time 5500886721 ps
CPU time 13.03 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:09:22 PM PDT 24
Peak memory 202168 kb
Host smart-72b53ee7-eb08-4930-8907-5bd6d43b7ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162879431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4162879431
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2335200828
Short name T69
Test name
Test status
Simulation time 7359479626 ps
CPU time 5.02 seconds
Started May 12 04:09:06 PM PDT 24
Finished May 12 04:09:11 PM PDT 24
Peak memory 218856 kb
Host smart-23aa247c-fa10-4b53-931e-6ea77ce5d7b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335200828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2335200828
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.548457612
Short name T154
Test name
Test status
Simulation time 5838076949 ps
CPU time 7.69 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:09:17 PM PDT 24
Peak memory 202152 kb
Host smart-85702047-fb40-4e46-b07c-6e119ecb797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548457612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.548457612
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3500864547
Short name T162
Test name
Test status
Simulation time 678741106047 ps
CPU time 1386.2 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:32:20 PM PDT 24
Peak memory 202292 kb
Host smart-9d8ca1c1-e561-4c94-9e1c-873c4dbbc963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500864547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3500864547
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1774559761
Short name T631
Test name
Test status
Simulation time 13507501203 ps
CPU time 31.94 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:09:43 PM PDT 24
Peak memory 202440 kb
Host smart-de3d7dff-4967-4afb-926c-6a6b2e70d8c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774559761 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1774559761
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.476040248
Short name T738
Test name
Test status
Simulation time 294658898 ps
CPU time 1.37 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:09:19 PM PDT 24
Peak memory 202008 kb
Host smart-7d8801c0-e97b-4c39-b24a-cbd4d8292940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476040248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.476040248
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3915676573
Short name T268
Test name
Test status
Simulation time 512436804161 ps
CPU time 1124.26 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:27:57 PM PDT 24
Peak memory 202332 kb
Host smart-b1ccf216-b1c1-4fba-b827-2d28429aeba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915676573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3915676573
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3409290364
Short name T237
Test name
Test status
Simulation time 481806389926 ps
CPU time 1106.66 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:27:38 PM PDT 24
Peak memory 202316 kb
Host smart-7bf8034d-84e3-417d-af72-2453cfa037d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409290364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3409290364
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.650127651
Short name T730
Test name
Test status
Simulation time 502167005832 ps
CPU time 595.96 seconds
Started May 12 04:09:13 PM PDT 24
Finished May 12 04:19:10 PM PDT 24
Peak memory 202320 kb
Host smart-2a0c662b-5121-492c-9a58-a9e07fe8cbdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=650127651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.650127651
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2687058805
Short name T157
Test name
Test status
Simulation time 484973142175 ps
CPU time 87.19 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:10:39 PM PDT 24
Peak memory 202320 kb
Host smart-c01a6aa4-076c-4f6e-904d-b510f3c75082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687058805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2687058805
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3916732238
Short name T673
Test name
Test status
Simulation time 171566613468 ps
CPU time 374.59 seconds
Started May 12 04:09:04 PM PDT 24
Finished May 12 04:15:19 PM PDT 24
Peak memory 202340 kb
Host smart-5f153fac-b649-4300-b1d8-2bd993c1037a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916732238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3916732238
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1363529685
Short name T108
Test name
Test status
Simulation time 581021634789 ps
CPU time 331.71 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:14:44 PM PDT 24
Peak memory 202400 kb
Host smart-00f1389e-2118-4962-8d87-2af9ec6e95f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363529685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1363529685
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1631882059
Short name T655
Test name
Test status
Simulation time 204597483000 ps
CPU time 498.7 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:17:26 PM PDT 24
Peak memory 202336 kb
Host smart-0beb9075-0224-4ffd-98c4-56e71d06070b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631882059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1631882059
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2783085728
Short name T454
Test name
Test status
Simulation time 80695039089 ps
CPU time 302.05 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:14:13 PM PDT 24
Peak memory 202660 kb
Host smart-9ba30e64-5388-4150-993d-1a08764f5c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783085728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2783085728
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.376889568
Short name T10
Test name
Test status
Simulation time 36153380062 ps
CPU time 28.08 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:40 PM PDT 24
Peak memory 202152 kb
Host smart-2c3a1883-ea3c-4727-822f-5be330f61fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376889568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.376889568
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3004261325
Short name T480
Test name
Test status
Simulation time 5192271793 ps
CPU time 1.85 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:09:12 PM PDT 24
Peak memory 202100 kb
Host smart-1a73d356-b3a0-4aa0-8600-c9db148f555f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004261325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3004261325
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2342632097
Short name T700
Test name
Test status
Simulation time 6013803319 ps
CPU time 13.96 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:09:29 PM PDT 24
Peak memory 202064 kb
Host smart-077ebdba-02fc-49d2-945f-81537b227daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342632097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2342632097
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1319046184
Short name T205
Test name
Test status
Simulation time 71916042553 ps
CPU time 129.55 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:11:21 PM PDT 24
Peak memory 210716 kb
Host smart-f2421c43-26cb-4bb7-97c3-db1896b4ea1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319046184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1319046184
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1332104236
Short name T716
Test name
Test status
Simulation time 287065902 ps
CPU time 1.32 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:09:31 PM PDT 24
Peak memory 202200 kb
Host smart-e7f0c782-dc42-4e4b-b583-bf17dd29023f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332104236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1332104236
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4031713813
Short name T737
Test name
Test status
Simulation time 161266719817 ps
CPU time 373.48 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:15:37 PM PDT 24
Peak memory 202408 kb
Host smart-f9642343-75e8-4b10-bd3a-ab319d03a0fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031713813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4031713813
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2522619121
Short name T122
Test name
Test status
Simulation time 333861913986 ps
CPU time 797.93 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:22:47 PM PDT 24
Peak memory 202316 kb
Host smart-6f666d28-2c57-48f4-8f4e-3c390ffd6530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522619121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2522619121
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1448225135
Short name T257
Test name
Test status
Simulation time 329587754116 ps
CPU time 726.62 seconds
Started May 12 04:09:27 PM PDT 24
Finished May 12 04:21:34 PM PDT 24
Peak memory 202372 kb
Host smart-4d199d74-7a39-4c0d-bbbc-55476d6572e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448225135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1448225135
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3930210105
Short name T531
Test name
Test status
Simulation time 332577805539 ps
CPU time 388.66 seconds
Started May 12 04:09:26 PM PDT 24
Finished May 12 04:15:56 PM PDT 24
Peak memory 202300 kb
Host smart-c76f6a32-fd60-4745-933e-6735e1e104d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930210105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3930210105
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.754368055
Short name T418
Test name
Test status
Simulation time 327068406675 ps
CPU time 712.81 seconds
Started May 12 04:09:26 PM PDT 24
Finished May 12 04:21:20 PM PDT 24
Peak memory 202268 kb
Host smart-9b2b88b7-fbc9-402e-b230-a07bf068fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754368055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.754368055
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1324652957
Short name T380
Test name
Test status
Simulation time 493936212894 ps
CPU time 574.32 seconds
Started May 12 04:09:27 PM PDT 24
Finished May 12 04:19:03 PM PDT 24
Peak memory 202312 kb
Host smart-e2819012-5a50-4a99-a425-b12c71cd701c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324652957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1324652957
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2228021507
Short name T275
Test name
Test status
Simulation time 553983194466 ps
CPU time 310.65 seconds
Started May 12 04:09:27 PM PDT 24
Finished May 12 04:14:39 PM PDT 24
Peak memory 202388 kb
Host smart-32c9470c-531d-47d0-b093-cfedd8427c2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228021507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2228021507
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.376066781
Short name T780
Test name
Test status
Simulation time 598231352435 ps
CPU time 722.65 seconds
Started May 12 04:09:26 PM PDT 24
Finished May 12 04:21:29 PM PDT 24
Peak memory 202312 kb
Host smart-b7f16288-4047-4c33-8bdc-ba78e4cfa2c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376066781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.376066781
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3477127565
Short name T571
Test name
Test status
Simulation time 96754578662 ps
CPU time 438.06 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:16:52 PM PDT 24
Peak memory 202652 kb
Host smart-1ebf3b13-904d-4f3e-ad6c-b6923e8f774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477127565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3477127565
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2428155597
Short name T85
Test name
Test status
Simulation time 22421051103 ps
CPU time 51.73 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:10:26 PM PDT 24
Peak memory 202116 kb
Host smart-d14c7243-5c10-4538-ad23-cdc22826fdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428155597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2428155597
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.18776194
Short name T560
Test name
Test status
Simulation time 3863949523 ps
CPU time 4.43 seconds
Started May 12 04:09:30 PM PDT 24
Finished May 12 04:09:35 PM PDT 24
Peak memory 202088 kb
Host smart-09a6c65c-0032-4d91-ae45-76a18b16ef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18776194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.18776194
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.773165176
Short name T706
Test name
Test status
Simulation time 5753587817 ps
CPU time 6.27 seconds
Started May 12 04:09:26 PM PDT 24
Finished May 12 04:09:33 PM PDT 24
Peak memory 202176 kb
Host smart-60a11ff2-fd94-485e-ab7e-7aa6f083d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773165176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.773165176
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3228037018
Short name T421
Test name
Test status
Simulation time 334625015 ps
CPU time 1.38 seconds
Started May 12 04:09:31 PM PDT 24
Finished May 12 04:09:33 PM PDT 24
Peak memory 202040 kb
Host smart-5544c89f-ea2b-4b9a-98e4-12dd267f6d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228037018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3228037018
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2337878065
Short name T627
Test name
Test status
Simulation time 163603522167 ps
CPU time 381.11 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:15:57 PM PDT 24
Peak memory 202288 kb
Host smart-6967ca74-65b3-410a-ae60-13e335083e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337878065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2337878065
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.173230222
Short name T646
Test name
Test status
Simulation time 334824212688 ps
CPU time 366.56 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:15:42 PM PDT 24
Peak memory 202316 kb
Host smart-51e91451-550e-46f9-b92c-4bde1aecbf9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=173230222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.173230222
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2052940949
Short name T187
Test name
Test status
Simulation time 490427062505 ps
CPU time 1199.28 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:29:35 PM PDT 24
Peak memory 202336 kb
Host smart-c1e7c68d-70c0-46be-ba61-2522880eb444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052940949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2052940949
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2308429656
Short name T587
Test name
Test status
Simulation time 494554193835 ps
CPU time 1054.63 seconds
Started May 12 04:09:27 PM PDT 24
Finished May 12 04:27:03 PM PDT 24
Peak memory 202312 kb
Host smart-6157ccf1-2d09-4ce6-b0a7-1e9293f3bee2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308429656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2308429656
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3034310423
Short name T300
Test name
Test status
Simulation time 550407784264 ps
CPU time 1221.15 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:29:50 PM PDT 24
Peak memory 202388 kb
Host smart-90a5bede-f8fd-43a0-86bc-9e717244ee78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034310423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3034310423
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.945802804
Short name T786
Test name
Test status
Simulation time 412059342027 ps
CPU time 486.06 seconds
Started May 12 04:09:31 PM PDT 24
Finished May 12 04:17:37 PM PDT 24
Peak memory 202396 kb
Host smart-2ae819d6-1f35-4139-8df9-ae6bc1326bb5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945802804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.945802804
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1794621987
Short name T28
Test name
Test status
Simulation time 34145647056 ps
CPU time 33.56 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:10:08 PM PDT 24
Peak memory 202128 kb
Host smart-f0d16aaa-6187-4f28-9425-a1478db2933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794621987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1794621987
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.347628666
Short name T551
Test name
Test status
Simulation time 4777376591 ps
CPU time 3.75 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:09:33 PM PDT 24
Peak memory 202176 kb
Host smart-b192e2d0-0db5-4c29-96f2-92219dfb25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347628666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.347628666
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3486236645
Short name T385
Test name
Test status
Simulation time 5976283783 ps
CPU time 15.51 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:09:44 PM PDT 24
Peak memory 202156 kb
Host smart-ff83c1bb-c045-4e80-a43f-3f6ac46bdf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486236645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3486236645
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.593260779
Short name T694
Test name
Test status
Simulation time 482877757 ps
CPU time 1.7 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:09:39 PM PDT 24
Peak memory 201348 kb
Host smart-cb5cd17e-1dc4-4064-b92f-6ca75f9cefdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593260779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.593260779
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2058177326
Short name T720
Test name
Test status
Simulation time 497734906376 ps
CPU time 228.28 seconds
Started May 12 04:09:33 PM PDT 24
Finished May 12 04:13:21 PM PDT 24
Peak memory 202396 kb
Host smart-351cb73c-15ca-4dff-930b-a2a21f2d8183
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058177326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2058177326
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3771963204
Short name T180
Test name
Test status
Simulation time 158866694026 ps
CPU time 172.36 seconds
Started May 12 04:09:31 PM PDT 24
Finished May 12 04:12:24 PM PDT 24
Peak memory 202292 kb
Host smart-e7b240ec-bb54-492e-85d0-8029c283c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771963204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3771963204
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2290634331
Short name T585
Test name
Test status
Simulation time 492994814948 ps
CPU time 1056.41 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:27:15 PM PDT 24
Peak memory 202256 kb
Host smart-5bd1582f-0203-4060-a2a8-08427e27fd93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290634331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2290634331
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3764587026
Short name T659
Test name
Test status
Simulation time 163953353092 ps
CPU time 349.23 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:15:28 PM PDT 24
Peak memory 202336 kb
Host smart-6a0b8542-215e-4b5e-a4f0-856997f45082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764587026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3764587026
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.463769302
Short name T504
Test name
Test status
Simulation time 490227959491 ps
CPU time 1016.06 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:26:30 PM PDT 24
Peak memory 202396 kb
Host smart-ab074d61-607a-4d0b-b1bb-8710190b649b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463769302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.463769302
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3463269713
Short name T658
Test name
Test status
Simulation time 183279518893 ps
CPU time 112.46 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:11:29 PM PDT 24
Peak memory 202388 kb
Host smart-517d9e5f-0c05-4764-92cf-dcbb8869805c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463269713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3463269713
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1891240801
Short name T742
Test name
Test status
Simulation time 407007792852 ps
CPU time 851.48 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:23:51 PM PDT 24
Peak memory 202280 kb
Host smart-eee9ff46-aeab-4fbd-9b8f-904b7da21eba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891240801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1891240801
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4240789856
Short name T44
Test name
Test status
Simulation time 68001440073 ps
CPU time 352.07 seconds
Started May 12 04:09:33 PM PDT 24
Finished May 12 04:15:26 PM PDT 24
Peak memory 202652 kb
Host smart-754abd9e-8e4f-436f-a43c-a4b56c08efdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240789856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4240789856
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.852438725
Short name T674
Test name
Test status
Simulation time 21810230807 ps
CPU time 51.27 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:10:28 PM PDT 24
Peak memory 202120 kb
Host smart-a2113724-9b2a-47cf-b2fc-021e89381c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852438725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.852438725
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2451308921
Short name T71
Test name
Test status
Simulation time 3194079468 ps
CPU time 8.11 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:09:43 PM PDT 24
Peak memory 202084 kb
Host smart-18c3eabf-99ad-47f9-8b5e-9f31d4e0f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451308921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2451308921
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2326076557
Short name T136
Test name
Test status
Simulation time 5938240634 ps
CPU time 7.53 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:09:44 PM PDT 24
Peak memory 202120 kb
Host smart-cc8c1b37-6708-492f-8a4c-6eaa75e73094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326076557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2326076557
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2120716761
Short name T31
Test name
Test status
Simulation time 234925526825 ps
CPU time 82.84 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:10:59 PM PDT 24
Peak memory 202292 kb
Host smart-c8b9062e-49cc-4543-a037-5a2d21832312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120716761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2120716761
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3580560717
Short name T35
Test name
Test status
Simulation time 66734024318 ps
CPU time 49.72 seconds
Started May 12 04:09:32 PM PDT 24
Finished May 12 04:10:22 PM PDT 24
Peak memory 210952 kb
Host smart-82501b66-c705-44d0-8dd7-472b04ca64f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580560717 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3580560717
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3880955650
Short name T360
Test name
Test status
Simulation time 358049919 ps
CPU time 0.74 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:09:39 PM PDT 24
Peak memory 201976 kb
Host smart-7e57f1ce-2798-4bc3-add4-d0271aa78e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880955650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3880955650
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3734898249
Short name T140
Test name
Test status
Simulation time 526334990824 ps
CPU time 311.58 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:14:50 PM PDT 24
Peak memory 202352 kb
Host smart-219acc08-e060-4fa0-9c6e-88d8cf1a5b40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734898249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3734898249
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3160868956
Short name T600
Test name
Test status
Simulation time 376641541474 ps
CPU time 224.09 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:13:21 PM PDT 24
Peak memory 202276 kb
Host smart-fcbd42bb-d559-4139-a457-892fc4c0f5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160868956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3160868956
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3776556663
Short name T291
Test name
Test status
Simulation time 325473775169 ps
CPU time 221.77 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:13:16 PM PDT 24
Peak memory 202332 kb
Host smart-7093b951-73b6-41a2-be49-087dc630cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776556663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3776556663
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3542920842
Short name T522
Test name
Test status
Simulation time 161360722390 ps
CPU time 333.57 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:15:13 PM PDT 24
Peak memory 202276 kb
Host smart-957f8653-c3d1-45a5-a77e-b3c1bd54a1dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542920842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3542920842
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3113110595
Short name T160
Test name
Test status
Simulation time 495222393263 ps
CPU time 611.13 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:19:48 PM PDT 24
Peak memory 201532 kb
Host smart-255088f2-0a10-4a5f-b68d-477134e64a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113110595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3113110595
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1360044869
Short name T621
Test name
Test status
Simulation time 327436733858 ps
CPU time 806.52 seconds
Started May 12 04:09:32 PM PDT 24
Finished May 12 04:22:59 PM PDT 24
Peak memory 202312 kb
Host smart-5ecce0d3-e1eb-4f1c-92a3-b6dacde43c6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360044869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1360044869
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4134496177
Short name T222
Test name
Test status
Simulation time 363866869935 ps
CPU time 845.39 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:23:43 PM PDT 24
Peak memory 202348 kb
Host smart-75dc9b59-51ec-4dae-b6de-1ab4a32a51c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134496177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4134496177
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1856280880
Short name T449
Test name
Test status
Simulation time 624993651310 ps
CPU time 732.04 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:21:49 PM PDT 24
Peak memory 202256 kb
Host smart-2045010a-a7ba-4464-aecf-b37e99743793
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856280880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1856280880
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3975898564
Short name T538
Test name
Test status
Simulation time 59914626073 ps
CPU time 238.27 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:13:34 PM PDT 24
Peak memory 202676 kb
Host smart-9270f58c-73f0-4186-b575-16283eee3e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975898564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3975898564
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1258359214
Short name T485
Test name
Test status
Simulation time 23643880476 ps
CPU time 29.76 seconds
Started May 12 04:09:31 PM PDT 24
Finished May 12 04:10:01 PM PDT 24
Peak memory 202136 kb
Host smart-e52c0fd5-4266-47a5-8863-75327f39572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258359214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1258359214
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.145653728
Short name T639
Test name
Test status
Simulation time 5084043080 ps
CPU time 12.05 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:09:48 PM PDT 24
Peak memory 202072 kb
Host smart-be4e81e7-4afd-4290-bf68-ed543dbc972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145653728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.145653728
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2995525032
Short name T723
Test name
Test status
Simulation time 6018288253 ps
CPU time 7.44 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:09:44 PM PDT 24
Peak memory 202080 kb
Host smart-8ee7c3e2-8a25-41ec-8aac-38100ac1cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995525032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2995525032
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3421191933
Short name T611
Test name
Test status
Simulation time 201413809899 ps
CPU time 112.51 seconds
Started May 12 04:09:40 PM PDT 24
Finished May 12 04:11:33 PM PDT 24
Peak memory 202496 kb
Host smart-151f7b02-0440-4f0c-906e-21f53e88f845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421191933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3421191933
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.862511910
Short name T725
Test name
Test status
Simulation time 25318454452 ps
CPU time 19.94 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:09:58 PM PDT 24
Peak memory 202380 kb
Host smart-575786e0-edd7-4ea8-b548-4ca26c68f3a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862511910 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.862511910
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4047018133
Short name T568
Test name
Test status
Simulation time 479004267 ps
CPU time 0.94 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:09:38 PM PDT 24
Peak memory 202020 kb
Host smart-f0aa1426-900e-41ff-ac2c-6e714926e1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047018133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4047018133
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3264062856
Short name T747
Test name
Test status
Simulation time 164991358081 ps
CPU time 43.29 seconds
Started May 12 04:09:37 PM PDT 24
Finished May 12 04:10:21 PM PDT 24
Peak memory 202316 kb
Host smart-1992d13c-d104-4627-80e8-5bee7cd3773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264062856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3264062856
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3257692882
Short name T155
Test name
Test status
Simulation time 163746404088 ps
CPU time 110.54 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:11:28 PM PDT 24
Peak memory 202384 kb
Host smart-56bad8e8-a483-4242-8489-0c273aebf374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257692882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3257692882
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2128598356
Short name T762
Test name
Test status
Simulation time 161667885728 ps
CPU time 97.08 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:11:14 PM PDT 24
Peak memory 202340 kb
Host smart-fad58ae6-40d6-4f2c-b7c5-ce3e91a2ab38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128598356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2128598356
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1925494687
Short name T239
Test name
Test status
Simulation time 166824401261 ps
CPU time 94.46 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:11:09 PM PDT 24
Peak memory 202372 kb
Host smart-38a362a4-741e-47ad-be4e-138ce18950ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925494687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1925494687
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1664485109
Short name T793
Test name
Test status
Simulation time 321963916109 ps
CPU time 398.05 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:16:15 PM PDT 24
Peak memory 202312 kb
Host smart-c5b15969-b4e9-40d4-9221-b87491075921
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664485109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1664485109
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3671161078
Short name T235
Test name
Test status
Simulation time 592734903138 ps
CPU time 709.67 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:21:27 PM PDT 24
Peak memory 202368 kb
Host smart-d8116260-22f0-4048-84b1-f13c12560f7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671161078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3671161078
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2064090906
Short name T711
Test name
Test status
Simulation time 45698542036 ps
CPU time 110.26 seconds
Started May 12 04:09:37 PM PDT 24
Finished May 12 04:11:28 PM PDT 24
Peak memory 202164 kb
Host smart-68f8ea36-f294-4b4d-82b2-fd8f2d5da1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064090906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2064090906
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2011808794
Short name T586
Test name
Test status
Simulation time 2866887040 ps
CPU time 7.23 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:09:44 PM PDT 24
Peak memory 202148 kb
Host smart-460b7e5f-21e5-4bfb-82e6-63407b85aa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011808794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2011808794
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.355857180
Short name T669
Test name
Test status
Simulation time 5755342419 ps
CPU time 7.14 seconds
Started May 12 04:09:36 PM PDT 24
Finished May 12 04:09:44 PM PDT 24
Peak memory 202140 kb
Host smart-2e9ace62-d92e-448d-b9f4-7cd8bd21713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355857180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.355857180
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2387363714
Short name T764
Test name
Test status
Simulation time 349957178702 ps
CPU time 650.83 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:20:27 PM PDT 24
Peak memory 211020 kb
Host smart-de698385-a893-40bb-96f2-ed21dd4f6714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387363714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2387363714
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2102573190
Short name T532
Test name
Test status
Simulation time 408777447 ps
CPU time 0.87 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:09:41 PM PDT 24
Peak memory 202012 kb
Host smart-c105f7ac-c771-4888-9464-84fd21966e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102573190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2102573190
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.15468963
Short name T147
Test name
Test status
Simulation time 177234849427 ps
CPU time 63.39 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:10:42 PM PDT 24
Peak memory 202424 kb
Host smart-9208868a-92e5-4cd2-99b9-3f09ee1cc598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15468963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.15468963
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2755853016
Short name T179
Test name
Test status
Simulation time 497259529191 ps
CPU time 581.74 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:19:17 PM PDT 24
Peak memory 202272 kb
Host smart-4b593233-14e1-4845-9347-8121e4e05b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755853016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2755853016
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.97031904
Short name T395
Test name
Test status
Simulation time 169465114620 ps
CPU time 184.09 seconds
Started May 12 04:09:37 PM PDT 24
Finished May 12 04:12:42 PM PDT 24
Peak memory 202236 kb
Host smart-bf81fedd-54f0-40e1-8eb3-42e703624e9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=97031904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt
_fixed.97031904
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.628061140
Short name T124
Test name
Test status
Simulation time 327798128452 ps
CPU time 405.77 seconds
Started May 12 04:09:37 PM PDT 24
Finished May 12 04:16:24 PM PDT 24
Peak memory 202404 kb
Host smart-1eb23e92-2678-4bdf-967d-7e454e6023cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628061140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.628061140
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2096926849
Short name T681
Test name
Test status
Simulation time 491350047019 ps
CPU time 1039.5 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:26:55 PM PDT 24
Peak memory 202360 kb
Host smart-dd167b6b-7161-434a-bab9-ed5006640fa7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096926849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2096926849
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.391576609
Short name T310
Test name
Test status
Simulation time 179130023491 ps
CPU time 103.12 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:11:19 PM PDT 24
Peak memory 202372 kb
Host smart-fab5eebe-6d86-40c2-a5ae-842e30f90be6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391576609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.391576609
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3548334795
Short name T392
Test name
Test status
Simulation time 389417660605 ps
CPU time 63.19 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:10:39 PM PDT 24
Peak memory 202324 kb
Host smart-ce0f753c-f8d7-4446-a11d-c4d7fc38ee94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548334795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3548334795
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.904127773
Short name T597
Test name
Test status
Simulation time 66693268351 ps
CPU time 228.96 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:13:27 PM PDT 24
Peak memory 202688 kb
Host smart-342c0fbf-bac3-428f-af2d-a07b2ab3c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904127773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.904127773
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.4263263179
Short name T375
Test name
Test status
Simulation time 31856527146 ps
CPU time 36.45 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:10:15 PM PDT 24
Peak memory 202124 kb
Host smart-303796a4-6476-4c5d-9db1-bf1a75205814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263263179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.4263263179
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2931585477
Short name T569
Test name
Test status
Simulation time 3714621655 ps
CPU time 9.55 seconds
Started May 12 04:09:38 PM PDT 24
Finished May 12 04:09:49 PM PDT 24
Peak memory 202136 kb
Host smart-0d302436-3f92-46f0-bae6-efe9707be807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931585477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2931585477
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.194202423
Short name T378
Test name
Test status
Simulation time 5670721841 ps
CPU time 13.14 seconds
Started May 12 04:09:37 PM PDT 24
Finished May 12 04:09:51 PM PDT 24
Peak memory 202160 kb
Host smart-a9039cdf-e096-48ac-8792-fb069dce8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194202423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.194202423
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1481971361
Short name T41
Test name
Test status
Simulation time 406354618650 ps
CPU time 981.7 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:26:01 PM PDT 24
Peak memory 211068 kb
Host smart-2e896f9b-2678-4279-abc5-e6f40ac06c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481971361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1481971361
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1249174023
Short name T227
Test name
Test status
Simulation time 442783697900 ps
CPU time 438.23 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:16:58 PM PDT 24
Peak memory 218260 kb
Host smart-cc996ae4-fa91-4d6e-9cd3-2413df529b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249174023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1249174023
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2722041770
Short name T794
Test name
Test status
Simulation time 497442300 ps
CPU time 1.82 seconds
Started May 12 04:09:49 PM PDT 24
Finished May 12 04:09:51 PM PDT 24
Peak memory 201988 kb
Host smart-75c6b34c-146a-4a5e-842d-fe0de9376275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722041770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2722041770
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3936477854
Short name T230
Test name
Test status
Simulation time 492028246193 ps
CPU time 298.17 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:14:47 PM PDT 24
Peak memory 202264 kb
Host smart-67b3b5d8-db4a-4d17-9ce0-1c434c57f226
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936477854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3936477854
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1953742363
Short name T208
Test name
Test status
Simulation time 504211646457 ps
CPU time 323.02 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:15:02 PM PDT 24
Peak memory 202292 kb
Host smart-98198084-9f7e-435a-aca6-5c9389675962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953742363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1953742363
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.11947160
Short name T670
Test name
Test status
Simulation time 166446512569 ps
CPU time 89.65 seconds
Started May 12 04:09:44 PM PDT 24
Finished May 12 04:11:15 PM PDT 24
Peak memory 202252 kb
Host smart-9bd65520-d332-45c9-9824-3fd7fa5706b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt
_fixed.11947160
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1482948905
Short name T352
Test name
Test status
Simulation time 327995308488 ps
CPU time 160.21 seconds
Started May 12 04:09:39 PM PDT 24
Finished May 12 04:12:20 PM PDT 24
Peak memory 202288 kb
Host smart-e35fb147-861a-4ac3-b128-2d822495ca62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482948905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1482948905
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3623300500
Short name T365
Test name
Test status
Simulation time 585829747889 ps
CPU time 1444.17 seconds
Started May 12 04:09:45 PM PDT 24
Finished May 12 04:33:50 PM PDT 24
Peak memory 202328 kb
Host smart-5519cff6-0a50-4b4b-a502-4dee38cccad3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623300500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3623300500
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2401879374
Short name T372
Test name
Test status
Simulation time 79139895304 ps
CPU time 432.28 seconds
Started May 12 04:09:45 PM PDT 24
Finished May 12 04:16:58 PM PDT 24
Peak memory 202672 kb
Host smart-34fb30cb-aeda-4040-ae91-da5cad7c6764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401879374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2401879374
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3992942886
Short name T754
Test name
Test status
Simulation time 40731578263 ps
CPU time 23.79 seconds
Started May 12 04:09:45 PM PDT 24
Finished May 12 04:10:10 PM PDT 24
Peak memory 202140 kb
Host smart-dc63057d-150c-4f22-8557-6222e5cbeaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992942886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3992942886
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1642581305
Short name T668
Test name
Test status
Simulation time 3977976602 ps
CPU time 10.22 seconds
Started May 12 04:09:44 PM PDT 24
Finished May 12 04:09:55 PM PDT 24
Peak memory 202140 kb
Host smart-9006e329-773c-477f-820f-a6ab35bfaa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642581305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1642581305
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3256046716
Short name T490
Test name
Test status
Simulation time 6080485871 ps
CPU time 3.03 seconds
Started May 12 04:09:41 PM PDT 24
Finished May 12 04:09:44 PM PDT 24
Peak memory 202128 kb
Host smart-029993dd-d01e-49a4-aeb9-5f9eff8d741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256046716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3256046716
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2769979081
Short name T309
Test name
Test status
Simulation time 230403095072 ps
CPU time 59.56 seconds
Started May 12 04:09:47 PM PDT 24
Finished May 12 04:10:47 PM PDT 24
Peak memory 202436 kb
Host smart-d4b95171-1410-44a7-bd2c-4738e54a7e68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769979081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2769979081
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.838523991
Short name T575
Test name
Test status
Simulation time 528016402 ps
CPU time 1.88 seconds
Started May 12 04:09:49 PM PDT 24
Finished May 12 04:09:51 PM PDT 24
Peak memory 201984 kb
Host smart-5cb4aa0d-8d2c-4f91-ab79-f20b3ca8a698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838523991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.838523991
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2490742538
Short name T508
Test name
Test status
Simulation time 347896104530 ps
CPU time 225.3 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:13:34 PM PDT 24
Peak memory 202208 kb
Host smart-dd3e6f4a-481c-464b-8773-a4e224efd46c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490742538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2490742538
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1550326925
Short name T595
Test name
Test status
Simulation time 327561589994 ps
CPU time 487.57 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:17:56 PM PDT 24
Peak memory 202248 kb
Host smart-a109bb1d-ec9b-4861-a241-b046f17b7917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550326925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1550326925
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3157923062
Short name T505
Test name
Test status
Simulation time 325863416654 ps
CPU time 202.52 seconds
Started May 12 04:09:46 PM PDT 24
Finished May 12 04:13:10 PM PDT 24
Peak memory 202328 kb
Host smart-00cffbe7-85c5-483d-840b-ebd622f21e24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157923062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3157923062
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1055938689
Short name T158
Test name
Test status
Simulation time 494903341876 ps
CPU time 137.24 seconds
Started May 12 04:09:52 PM PDT 24
Finished May 12 04:12:10 PM PDT 24
Peak memory 202308 kb
Host smart-fd32bae1-ed21-4fb5-ae37-8dd710c0f529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055938689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1055938689
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3708073495
Short name T361
Test name
Test status
Simulation time 498215941097 ps
CPU time 575.5 seconds
Started May 12 04:09:44 PM PDT 24
Finished May 12 04:19:20 PM PDT 24
Peak memory 202280 kb
Host smart-a5962f63-1212-42e4-b43a-64496cb2a4ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708073495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3708073495
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3972080681
Short name T288
Test name
Test status
Simulation time 378535190913 ps
CPU time 237.04 seconds
Started May 12 04:09:44 PM PDT 24
Finished May 12 04:13:42 PM PDT 24
Peak memory 202408 kb
Host smart-beda019d-af1f-4d37-aa12-cc86d3849bf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972080681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3972080681
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2953051522
Short name T513
Test name
Test status
Simulation time 382594523571 ps
CPU time 475.49 seconds
Started May 12 04:09:49 PM PDT 24
Finished May 12 04:17:45 PM PDT 24
Peak memory 202252 kb
Host smart-2b2331af-7f60-45d1-86cd-2a7f864a7b02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953051522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2953051522
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2601025108
Short name T42
Test name
Test status
Simulation time 64064989884 ps
CPU time 258.28 seconds
Started May 12 04:09:47 PM PDT 24
Finished May 12 04:14:06 PM PDT 24
Peak memory 202692 kb
Host smart-91f534ee-eb66-4a6b-b1f6-f3a596f7a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601025108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2601025108
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2747687585
Short name T414
Test name
Test status
Simulation time 40689540341 ps
CPU time 47.89 seconds
Started May 12 04:09:51 PM PDT 24
Finished May 12 04:10:39 PM PDT 24
Peak memory 202124 kb
Host smart-566e3336-c854-41aa-993b-459abbd9a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747687585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2747687585
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2674246844
Short name T693
Test name
Test status
Simulation time 4829096243 ps
CPU time 12.81 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:10:01 PM PDT 24
Peak memory 202108 kb
Host smart-279f899b-1cd0-47e7-8dcf-737f5359def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674246844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2674246844
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2111318616
Short name T717
Test name
Test status
Simulation time 5609199621 ps
CPU time 7.92 seconds
Started May 12 04:09:45 PM PDT 24
Finished May 12 04:09:54 PM PDT 24
Peak memory 202120 kb
Host smart-96699db9-169e-4a80-afba-5361aa3bf525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111318616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2111318616
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3103866018
Short name T735
Test name
Test status
Simulation time 107492195983 ps
CPU time 497.64 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:18:12 PM PDT 24
Peak memory 210880 kb
Host smart-4cd16e76-8f21-42b7-8fcb-6089b562b2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103866018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3103866018
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2266945023
Short name T634
Test name
Test status
Simulation time 45422774823 ps
CPU time 119.08 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:11:47 PM PDT 24
Peak memory 211724 kb
Host smart-37c23bb1-71af-4d52-8a7a-15fe3b340fd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266945023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2266945023
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4196043486
Short name T792
Test name
Test status
Simulation time 360945675 ps
CPU time 0.84 seconds
Started May 12 04:09:50 PM PDT 24
Finished May 12 04:09:51 PM PDT 24
Peak memory 202012 kb
Host smart-2a5a6790-9434-428a-85b7-f47bc95c0103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196043486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4196043486
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.503531560
Short name T278
Test name
Test status
Simulation time 168453548549 ps
CPU time 218.67 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:13:33 PM PDT 24
Peak memory 202404 kb
Host smart-449188bc-c795-42fe-9d19-69f7e6e35a43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503531560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.503531560
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2816826242
Short name T690
Test name
Test status
Simulation time 164110226932 ps
CPU time 121.89 seconds
Started May 12 04:09:50 PM PDT 24
Finished May 12 04:11:53 PM PDT 24
Peak memory 202304 kb
Host smart-84df679e-1437-4a8e-bf46-20c8c7944382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816826242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2816826242
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.300765225
Short name T494
Test name
Test status
Simulation time 496885902205 ps
CPU time 1200.55 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:29:55 PM PDT 24
Peak memory 202312 kb
Host smart-43e7d21a-0bdc-4781-aa2e-26807c470a22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=300765225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.300765225
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3152212372
Short name T712
Test name
Test status
Simulation time 491114283752 ps
CPU time 281.57 seconds
Started May 12 04:09:51 PM PDT 24
Finished May 12 04:14:33 PM PDT 24
Peak memory 202272 kb
Host smart-d31e502b-7dae-4e5a-9e0f-e62f82ac6680
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152212372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3152212372
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2294795464
Short name T404
Test name
Test status
Simulation time 205888124717 ps
CPU time 264.72 seconds
Started May 12 04:09:48 PM PDT 24
Finished May 12 04:14:14 PM PDT 24
Peak memory 202252 kb
Host smart-d50408fd-537f-4ecb-93cc-7cc76f819e5f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294795464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2294795464
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2837327997
Short name T318
Test name
Test status
Simulation time 103753313238 ps
CPU time 381.72 seconds
Started May 12 04:09:49 PM PDT 24
Finished May 12 04:16:11 PM PDT 24
Peak memory 202760 kb
Host smart-ff5032cb-8b05-4e96-9d09-780d752cdecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837327997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2837327997
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.569195131
Short name T354
Test name
Test status
Simulation time 37684154853 ps
CPU time 15.45 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:10:10 PM PDT 24
Peak memory 202344 kb
Host smart-d8c02ce7-ce63-4a36-948b-a34a073e88bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569195131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.569195131
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2593778682
Short name T339
Test name
Test status
Simulation time 3525826701 ps
CPU time 4.78 seconds
Started May 12 04:09:55 PM PDT 24
Finished May 12 04:10:01 PM PDT 24
Peak memory 202152 kb
Host smart-b11df91b-d726-4cd0-b62d-40ce16b97686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593778682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2593778682
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3818786122
Short name T714
Test name
Test status
Simulation time 5522574579 ps
CPU time 7.01 seconds
Started May 12 04:09:47 PM PDT 24
Finished May 12 04:09:55 PM PDT 24
Peak memory 202116 kb
Host smart-8c659b45-1237-41bc-a434-a3859f75e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818786122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3818786122
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1895461663
Short name T645
Test name
Test status
Simulation time 143896002959 ps
CPU time 564.73 seconds
Started May 12 04:09:56 PM PDT 24
Finished May 12 04:19:21 PM PDT 24
Peak memory 210884 kb
Host smart-49397da8-c58f-418b-976e-e7736343bb93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895461663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1895461663
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2589165124
Short name T212
Test name
Test status
Simulation time 57738334349 ps
CPU time 138.84 seconds
Started May 12 04:09:49 PM PDT 24
Finished May 12 04:12:08 PM PDT 24
Peak memory 218360 kb
Host smart-ff381d9f-77df-4503-bf9b-d92d8d3491e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589165124 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2589165124
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3031110350
Short name T501
Test name
Test status
Simulation time 503464116 ps
CPU time 1.21 seconds
Started May 12 04:09:56 PM PDT 24
Finished May 12 04:09:58 PM PDT 24
Peak memory 202028 kb
Host smart-b4b96ae6-29ae-473c-9be2-c7bf0ec8f6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031110350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3031110350
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.762812602
Short name T500
Test name
Test status
Simulation time 169765559049 ps
CPU time 41.46 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:10:36 PM PDT 24
Peak memory 202328 kb
Host smart-1060cbdb-b294-4d4c-91d2-0ec92bad88e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762812602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.762812602
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.841078866
Short name T150
Test name
Test status
Simulation time 168162162382 ps
CPU time 57.74 seconds
Started May 12 04:09:53 PM PDT 24
Finished May 12 04:10:51 PM PDT 24
Peak memory 202372 kb
Host smart-448fdc31-d7e3-4c74-95ff-bcb012b1378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841078866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.841078866
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2994398047
Short name T173
Test name
Test status
Simulation time 164437855759 ps
CPU time 189.67 seconds
Started May 12 04:09:53 PM PDT 24
Finished May 12 04:13:03 PM PDT 24
Peak memory 202320 kb
Host smart-9ce98db6-0680-40a5-a40d-b866562fe325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994398047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2994398047
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1844628846
Short name T728
Test name
Test status
Simulation time 476825123149 ps
CPU time 248.58 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:14:04 PM PDT 24
Peak memory 202316 kb
Host smart-a180982c-f828-402c-a367-473000e1614c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844628846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1844628846
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1821041561
Short name T78
Test name
Test status
Simulation time 493453981224 ps
CPU time 1099.59 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:28:15 PM PDT 24
Peak memory 202592 kb
Host smart-79d86709-8a02-4f62-9a4b-919bc88f3fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821041561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1821041561
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1787462334
Short name T751
Test name
Test status
Simulation time 166159693920 ps
CPU time 94.27 seconds
Started May 12 04:09:55 PM PDT 24
Finished May 12 04:11:30 PM PDT 24
Peak memory 202292 kb
Host smart-a71432ff-29ca-49d3-b0ec-cdb64416e016
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787462334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1787462334
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1164849322
Short name T256
Test name
Test status
Simulation time 195160035322 ps
CPU time 435.49 seconds
Started May 12 04:09:53 PM PDT 24
Finished May 12 04:17:09 PM PDT 24
Peak memory 202324 kb
Host smart-60ddf183-cad6-4a6f-9af6-0ae7ff217a1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164849322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1164849322
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1507135757
Short name T521
Test name
Test status
Simulation time 386982155479 ps
CPU time 853.99 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:24:08 PM PDT 24
Peak memory 202296 kb
Host smart-b4e854f9-87d1-4b48-b3d8-c1c9cbad45eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507135757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1507135757
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1765092661
Short name T445
Test name
Test status
Simulation time 23417486467 ps
CPU time 55.01 seconds
Started May 12 04:09:52 PM PDT 24
Finished May 12 04:10:48 PM PDT 24
Peak memory 202168 kb
Host smart-911bdcca-12f7-4b3e-81e6-dbda54f37ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765092661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1765092661
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1941890207
Short name T467
Test name
Test status
Simulation time 4353287850 ps
CPU time 10.63 seconds
Started May 12 04:09:54 PM PDT 24
Finished May 12 04:10:06 PM PDT 24
Peak memory 202152 kb
Host smart-220e08d4-fb32-4f27-8bb7-58c81fcd9e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941890207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1941890207
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1807203332
Short name T772
Test name
Test status
Simulation time 5818435163 ps
CPU time 10.73 seconds
Started May 12 04:09:55 PM PDT 24
Finished May 12 04:10:07 PM PDT 24
Peak memory 202156 kb
Host smart-30338d74-c47d-4140-a319-1b6774cabe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807203332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1807203332
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2967739538
Short name T337
Test name
Test status
Simulation time 50474064287 ps
CPU time 34.69 seconds
Started May 12 04:09:53 PM PDT 24
Finished May 12 04:10:28 PM PDT 24
Peak memory 202316 kb
Host smart-b821ab43-c046-4533-9297-c9eacd7897ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967739538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2967739538
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2783105452
Short name T374
Test name
Test status
Simulation time 459955224 ps
CPU time 0.93 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:09:15 PM PDT 24
Peak memory 201932 kb
Host smart-42888812-87b6-43ff-a06a-e8ea42f89202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783105452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2783105452
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3553489051
Short name T576
Test name
Test status
Simulation time 204016176946 ps
CPU time 426.59 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:16:22 PM PDT 24
Peak memory 201924 kb
Host smart-612ea400-c046-4516-927a-9d156d54af21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553489051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3553489051
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3166742977
Short name T182
Test name
Test status
Simulation time 486669019426 ps
CPU time 1074.99 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:27:13 PM PDT 24
Peak memory 202412 kb
Host smart-8bd1a3ff-a466-45ad-a419-72b91732e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166742977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3166742977
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3957821419
Short name T262
Test name
Test status
Simulation time 165807346242 ps
CPU time 105.93 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:11:00 PM PDT 24
Peak memory 202312 kb
Host smart-141e5955-008c-4093-931f-5c0650a27108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957821419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3957821419
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.185058147
Short name T599
Test name
Test status
Simulation time 331323552444 ps
CPU time 755.58 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:21:44 PM PDT 24
Peak memory 202296 kb
Host smart-4290c576-f7e6-4cef-bc82-c7ccfc164783
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=185058147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.185058147
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.962025698
Short name T696
Test name
Test status
Simulation time 328619317589 ps
CPU time 795.45 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:22:27 PM PDT 24
Peak memory 202364 kb
Host smart-0dcf9003-737a-4b12-8740-b751c3d7f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962025698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.962025698
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1866412585
Short name T79
Test name
Test status
Simulation time 488493796544 ps
CPU time 610.89 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:19:23 PM PDT 24
Peak memory 202296 kb
Host smart-8cd53ab0-1a55-4987-ad95-cb5b0fe90a8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866412585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1866412585
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2896804908
Short name T426
Test name
Test status
Simulation time 595514033864 ps
CPU time 1390.83 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:32:20 PM PDT 24
Peak memory 202396 kb
Host smart-c0625fd4-52e5-45ab-9431-df5c27ddefd4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896804908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2896804908
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3223898734
Short name T699
Test name
Test status
Simulation time 111329823004 ps
CPU time 305.73 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:14:14 PM PDT 24
Peak memory 202712 kb
Host smart-faa2d84c-0c7f-4306-9317-441a1dfde1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223898734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3223898734
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3390153386
Short name T684
Test name
Test status
Simulation time 35476282802 ps
CPU time 20.01 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:31 PM PDT 24
Peak memory 202116 kb
Host smart-48e91b65-22fa-4963-8351-50b922cdaf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390153386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3390153386
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2200054943
Short name T347
Test name
Test status
Simulation time 5250998708 ps
CPU time 5.54 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:17 PM PDT 24
Peak memory 202144 kb
Host smart-c1aada1c-006b-4e21-95bf-94cd128f928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200054943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2200054943
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.290180388
Short name T55
Test name
Test status
Simulation time 3910526691 ps
CPU time 5.97 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:09:17 PM PDT 24
Peak memory 217976 kb
Host smart-c8478dd9-c027-4b79-b1ed-c0c64f0c4778
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290180388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.290180388
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3988817086
Short name T640
Test name
Test status
Simulation time 5624405738 ps
CPU time 4.1 seconds
Started May 12 04:09:16 PM PDT 24
Finished May 12 04:09:21 PM PDT 24
Peak memory 202156 kb
Host smart-b2075947-7ca4-49e7-8aa6-1e9a1cf05070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988817086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3988817086
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1182913187
Short name T787
Test name
Test status
Simulation time 249232495267 ps
CPU time 854.89 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:23:26 PM PDT 24
Peak memory 213360 kb
Host smart-66cb9fa3-3e50-4e63-9de4-c3190d73eff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182913187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1182913187
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3626557265
Short name T384
Test name
Test status
Simulation time 332380129 ps
CPU time 1.36 seconds
Started May 12 04:10:00 PM PDT 24
Finished May 12 04:10:02 PM PDT 24
Peak memory 201980 kb
Host smart-6712b621-ae65-4795-a720-ec8b645afd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626557265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3626557265
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.804545761
Short name T710
Test name
Test status
Simulation time 371103277676 ps
CPU time 227.72 seconds
Started May 12 04:09:56 PM PDT 24
Finished May 12 04:13:45 PM PDT 24
Peak memory 202316 kb
Host smart-a01631b5-491c-4432-bf1a-fd0dc37a41be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804545761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.804545761
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4108050205
Short name T228
Test name
Test status
Simulation time 488426069957 ps
CPU time 1212.67 seconds
Started May 12 04:10:01 PM PDT 24
Finished May 12 04:30:14 PM PDT 24
Peak memory 202500 kb
Host smart-9db4bfff-b074-4daa-8fa6-fa68ec5266f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108050205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4108050205
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.130764980
Short name T506
Test name
Test status
Simulation time 331681665552 ps
CPU time 216.66 seconds
Started May 12 04:10:01 PM PDT 24
Finished May 12 04:13:38 PM PDT 24
Peak memory 202488 kb
Host smart-ed9335be-9732-4930-b19a-e259b410d018
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=130764980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.130764980
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.408433511
Short name T2
Test name
Test status
Simulation time 330060192303 ps
CPU time 786.89 seconds
Started May 12 04:09:58 PM PDT 24
Finished May 12 04:23:05 PM PDT 24
Peak memory 202236 kb
Host smart-a5eda6de-69a1-41f8-a4b4-e73cf431d86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408433511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.408433511
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3744554780
Short name T610
Test name
Test status
Simulation time 332745956384 ps
CPU time 338.95 seconds
Started May 12 04:09:57 PM PDT 24
Finished May 12 04:15:37 PM PDT 24
Peak memory 202208 kb
Host smart-8c020798-85ca-4464-9971-45cca02b5bf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744554780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3744554780
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2912238696
Short name T12
Test name
Test status
Simulation time 338324386012 ps
CPU time 197.37 seconds
Started May 12 04:09:57 PM PDT 24
Finished May 12 04:13:15 PM PDT 24
Peak memory 202328 kb
Host smart-fa1e8ad3-9d0e-40df-9aca-3a8512fe27c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912238696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2912238696
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3631896233
Short name T470
Test name
Test status
Simulation time 406504374111 ps
CPU time 892.46 seconds
Started May 12 04:09:56 PM PDT 24
Finished May 12 04:24:49 PM PDT 24
Peak memory 202316 kb
Host smart-743ce278-4496-44ef-8e6e-487fdd213077
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631896233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3631896233
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3183099090
Short name T334
Test name
Test status
Simulation time 103379073231 ps
CPU time 338.34 seconds
Started May 12 04:10:00 PM PDT 24
Finished May 12 04:15:39 PM PDT 24
Peak memory 202732 kb
Host smart-b548a70f-9a45-437b-9114-7dd47a987249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183099090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3183099090
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3689012482
Short name T416
Test name
Test status
Simulation time 26939337042 ps
CPU time 28.43 seconds
Started May 12 04:10:01 PM PDT 24
Finished May 12 04:10:30 PM PDT 24
Peak memory 202176 kb
Host smart-05f06490-e57e-4d71-85cf-7bc2fc722112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689012482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3689012482
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2534999264
Short name T336
Test name
Test status
Simulation time 3590778674 ps
CPU time 3.1 seconds
Started May 12 04:09:56 PM PDT 24
Finished May 12 04:10:00 PM PDT 24
Peak memory 202132 kb
Host smart-cc3de56d-3f06-4251-8398-89cb263eafcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534999264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2534999264
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1079705545
Short name T469
Test name
Test status
Simulation time 5868772737 ps
CPU time 7.88 seconds
Started May 12 04:09:55 PM PDT 24
Finished May 12 04:10:03 PM PDT 24
Peak memory 202152 kb
Host smart-8f94503c-9517-4e29-a2cc-629059747038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079705545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1079705545
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1539444077
Short name T561
Test name
Test status
Simulation time 188301748163 ps
CPU time 75.18 seconds
Started May 12 04:09:59 PM PDT 24
Finished May 12 04:11:14 PM PDT 24
Peak memory 202328 kb
Host smart-77e3db44-6076-4de1-afbc-96373cf8382c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539444077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1539444077
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1218836118
Short name T18
Test name
Test status
Simulation time 77423952485 ps
CPU time 43.3 seconds
Started May 12 04:09:59 PM PDT 24
Finished May 12 04:10:43 PM PDT 24
Peak memory 210764 kb
Host smart-3d87009c-da8d-40b7-a9de-412858613ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218836118 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1218836118
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1033103959
Short name T397
Test name
Test status
Simulation time 309530088 ps
CPU time 1.33 seconds
Started May 12 04:10:06 PM PDT 24
Finished May 12 04:10:08 PM PDT 24
Peak memory 202200 kb
Host smart-7c17865d-1df7-40d9-9e5e-d18b02bbb881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033103959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1033103959
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3681006772
Short name T252
Test name
Test status
Simulation time 164860092587 ps
CPU time 97.42 seconds
Started May 12 04:10:03 PM PDT 24
Finished May 12 04:11:41 PM PDT 24
Peak memory 202516 kb
Host smart-3d50e659-2280-4a66-a7b1-aa2e9a18cf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681006772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3681006772
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2780197036
Short name T181
Test name
Test status
Simulation time 160497753862 ps
CPU time 190.92 seconds
Started May 12 04:10:02 PM PDT 24
Finished May 12 04:13:14 PM PDT 24
Peak memory 202396 kb
Host smart-94555165-2ca5-431c-b6e4-29e38c3190c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780197036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2780197036
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4195964197
Short name T701
Test name
Test status
Simulation time 326393757992 ps
CPU time 186.38 seconds
Started May 12 04:10:04 PM PDT 24
Finished May 12 04:13:11 PM PDT 24
Peak memory 202308 kb
Host smart-adc0100a-9f4f-4df6-88cb-65b7195077bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195964197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4195964197
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1882982341
Short name T302
Test name
Test status
Simulation time 492218825825 ps
CPU time 1020.77 seconds
Started May 12 04:10:03 PM PDT 24
Finished May 12 04:27:04 PM PDT 24
Peak memory 202260 kb
Host smart-b102cf4b-a380-40d4-a6d7-22afb37a0d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882982341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1882982341
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1869109492
Short name T356
Test name
Test status
Simulation time 335448698442 ps
CPU time 46.91 seconds
Started May 12 04:10:03 PM PDT 24
Finished May 12 04:10:51 PM PDT 24
Peak memory 202272 kb
Host smart-2b7b7499-0c70-45e7-9fa8-f58df289614e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869109492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1869109492
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1258814962
Short name T304
Test name
Test status
Simulation time 346446326730 ps
CPU time 59.62 seconds
Started May 12 04:10:03 PM PDT 24
Finished May 12 04:11:03 PM PDT 24
Peak memory 202320 kb
Host smart-3e9d6621-27e6-4f4e-a615-473fa4a8efa6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258814962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1258814962
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3640680404
Short name T630
Test name
Test status
Simulation time 190179788272 ps
CPU time 243.99 seconds
Started May 12 04:10:04 PM PDT 24
Finished May 12 04:14:08 PM PDT 24
Peak memory 202288 kb
Host smart-796ee44e-30bb-4c4b-b305-277a10ceef59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640680404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3640680404
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.541683030
Short name T579
Test name
Test status
Simulation time 113774771581 ps
CPU time 610.17 seconds
Started May 12 04:10:06 PM PDT 24
Finished May 12 04:20:16 PM PDT 24
Peak memory 202700 kb
Host smart-db954489-59ab-4e58-8fb7-928ce0313c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541683030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.541683030
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1915454126
Short name T419
Test name
Test status
Simulation time 39905533669 ps
CPU time 16.58 seconds
Started May 12 04:10:08 PM PDT 24
Finished May 12 04:10:25 PM PDT 24
Peak memory 202132 kb
Host smart-cdce79e6-61c4-4b39-a537-dcba59ff125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915454126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1915454126
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.440778035
Short name T535
Test name
Test status
Simulation time 3609731304 ps
CPU time 8.58 seconds
Started May 12 04:10:04 PM PDT 24
Finished May 12 04:10:13 PM PDT 24
Peak memory 202104 kb
Host smart-2b3fc8e3-138b-4331-a1d1-0ffa7dc89a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440778035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.440778035
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2866291258
Short name T381
Test name
Test status
Simulation time 5710621695 ps
CPU time 6.28 seconds
Started May 12 04:10:03 PM PDT 24
Finished May 12 04:10:10 PM PDT 24
Peak memory 202112 kb
Host smart-851bba58-0988-454b-aa90-f3a73fb55bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866291258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2866291258
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3803249993
Short name T662
Test name
Test status
Simulation time 440526683225 ps
CPU time 1386.48 seconds
Started May 12 04:10:06 PM PDT 24
Finished May 12 04:33:13 PM PDT 24
Peak memory 202696 kb
Host smart-88b51fb4-5cb9-4017-94c6-fac93ed9b02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803249993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3803249993
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2449589584
Short name T759
Test name
Test status
Simulation time 390776374 ps
CPU time 0.85 seconds
Started May 12 04:10:11 PM PDT 24
Finished May 12 04:10:12 PM PDT 24
Peak memory 202036 kb
Host smart-ff5abec9-e9b9-40cc-bbfa-b87591e52060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449589584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2449589584
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3812067652
Short name T166
Test name
Test status
Simulation time 172263426475 ps
CPU time 269 seconds
Started May 12 04:10:08 PM PDT 24
Finished May 12 04:14:38 PM PDT 24
Peak memory 202420 kb
Host smart-c277177f-17ba-464c-a3f5-c702929e880c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812067652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3812067652
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1657622598
Short name T81
Test name
Test status
Simulation time 338557756975 ps
CPU time 809.16 seconds
Started May 12 04:10:12 PM PDT 24
Finished May 12 04:23:41 PM PDT 24
Peak memory 202336 kb
Host smart-cd2ea1bf-e22b-48bb-bb2f-634c4d6bc767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657622598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1657622598
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2849561834
Short name T607
Test name
Test status
Simulation time 160159413720 ps
CPU time 60.92 seconds
Started May 12 04:10:09 PM PDT 24
Finished May 12 04:11:11 PM PDT 24
Peak memory 202372 kb
Host smart-ce9bb23d-3c8d-46de-a522-1a77e8aadfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849561834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2849561834
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.277934086
Short name T420
Test name
Test status
Simulation time 164207861041 ps
CPU time 355.39 seconds
Started May 12 04:10:09 PM PDT 24
Finished May 12 04:16:04 PM PDT 24
Peak memory 202340 kb
Host smart-a33a2e43-9869-4c3c-9e18-6ac7fb621524
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=277934086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.277934086
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3622182256
Short name T562
Test name
Test status
Simulation time 331112217822 ps
CPU time 790.84 seconds
Started May 12 04:10:09 PM PDT 24
Finished May 12 04:23:21 PM PDT 24
Peak memory 202232 kb
Host smart-16efbbe5-bdd3-484e-a889-b8a8890d98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622182256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3622182256
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.4218097409
Short name T369
Test name
Test status
Simulation time 159998569101 ps
CPU time 91.67 seconds
Started May 12 04:10:11 PM PDT 24
Finished May 12 04:11:43 PM PDT 24
Peak memory 202280 kb
Host smart-9520e325-b3dc-4bd6-a08d-fb8ffc6ea65c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218097409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.4218097409
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3041712527
Short name T198
Test name
Test status
Simulation time 355616011254 ps
CPU time 750.51 seconds
Started May 12 04:10:11 PM PDT 24
Finished May 12 04:22:42 PM PDT 24
Peak memory 202404 kb
Host smart-85aa3184-e497-4417-bc3b-4677cf51f195
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041712527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3041712527
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3710686576
Short name T425
Test name
Test status
Simulation time 399698755232 ps
CPU time 707.99 seconds
Started May 12 04:10:10 PM PDT 24
Finished May 12 04:21:58 PM PDT 24
Peak memory 202400 kb
Host smart-ad9faad9-70b3-4d3c-9018-4a2acca4a47d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710686576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3710686576
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.901157320
Short name T411
Test name
Test status
Simulation time 119895601411 ps
CPU time 645.07 seconds
Started May 12 04:10:12 PM PDT 24
Finished May 12 04:20:57 PM PDT 24
Peak memory 202692 kb
Host smart-19a41c26-9bf9-48e5-9464-f5b0275fcb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901157320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.901157320
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.817545871
Short name T619
Test name
Test status
Simulation time 45615541434 ps
CPU time 59 seconds
Started May 12 04:10:12 PM PDT 24
Finished May 12 04:11:11 PM PDT 24
Peak memory 202168 kb
Host smart-e83648d0-8a15-4da3-bb76-35409fc1ccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817545871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.817545871
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3009435600
Short name T583
Test name
Test status
Simulation time 3998236414 ps
CPU time 10.44 seconds
Started May 12 04:10:12 PM PDT 24
Finished May 12 04:10:23 PM PDT 24
Peak memory 202172 kb
Host smart-362394c0-5451-4607-af64-4f1fe8679db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009435600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3009435600
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1416485244
Short name T656
Test name
Test status
Simulation time 6202414070 ps
CPU time 15.99 seconds
Started May 12 04:10:07 PM PDT 24
Finished May 12 04:10:23 PM PDT 24
Peak memory 202148 kb
Host smart-cbd1f91a-3bb1-4f25-9671-dd40379079d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416485244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1416485244
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1205996964
Short name T21
Test name
Test status
Simulation time 119175881345 ps
CPU time 114.24 seconds
Started May 12 04:10:11 PM PDT 24
Finished May 12 04:12:06 PM PDT 24
Peak memory 218492 kb
Host smart-2c9e3f11-140c-4a23-9a8d-f215e624a160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205996964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1205996964
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.4072331822
Short name T702
Test name
Test status
Simulation time 530425018239 ps
CPU time 110.27 seconds
Started May 12 04:10:16 PM PDT 24
Finished May 12 04:12:06 PM PDT 24
Peak memory 202416 kb
Host smart-6bed662c-6cab-483d-8a81-aa6fb514bb32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072331822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.4072331822
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.159912576
Short name T497
Test name
Test status
Simulation time 476186550476 ps
CPU time 1047.31 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:27:43 PM PDT 24
Peak memory 202392 kb
Host smart-8abd5df0-7478-47ef-9830-5526bf9dddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159912576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.159912576
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.47284432
Short name T542
Test name
Test status
Simulation time 325523707569 ps
CPU time 113.77 seconds
Started May 12 04:10:16 PM PDT 24
Finished May 12 04:12:10 PM PDT 24
Peak memory 202344 kb
Host smart-e77c1239-4f21-493b-9521-3e7cf2ddc701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47284432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.47284432
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.434476574
Short name T590
Test name
Test status
Simulation time 333483693915 ps
CPU time 757.49 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:22:53 PM PDT 24
Peak memory 202300 kb
Host smart-a5603a8e-1f11-4741-8680-9d01e2dfef5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=434476574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.434476574
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4236134345
Short name T744
Test name
Test status
Simulation time 496799414903 ps
CPU time 1195.19 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:30:11 PM PDT 24
Peak memory 202316 kb
Host smart-472885f9-febd-4d55-ab86-f240c29bcb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236134345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4236134345
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3916167919
Short name T784
Test name
Test status
Simulation time 161038131556 ps
CPU time 182.04 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:13:18 PM PDT 24
Peak memory 202324 kb
Host smart-c551176b-0bb3-428a-a3c3-bda1c691d778
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916167919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3916167919
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1036072378
Short name T220
Test name
Test status
Simulation time 542357641480 ps
CPU time 1253.38 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:31:08 PM PDT 24
Peak memory 202352 kb
Host smart-3d8593b2-6cbe-4010-881d-25910a7e0cdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036072378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1036072378
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3028840335
Short name T777
Test name
Test status
Simulation time 197802052226 ps
CPU time 114.09 seconds
Started May 12 04:10:18 PM PDT 24
Finished May 12 04:12:13 PM PDT 24
Peak memory 202296 kb
Host smart-43617479-997e-48e8-8c32-c3ffb8feeebc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028840335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3028840335
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2242437400
Short name T455
Test name
Test status
Simulation time 22455116586 ps
CPU time 38.86 seconds
Started May 12 04:10:15 PM PDT 24
Finished May 12 04:10:54 PM PDT 24
Peak memory 202164 kb
Host smart-b604eaf4-8504-4f1f-9909-2103813dc694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242437400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2242437400
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.281273268
Short name T135
Test name
Test status
Simulation time 3510495730 ps
CPU time 2.54 seconds
Started May 12 04:10:16 PM PDT 24
Finished May 12 04:10:19 PM PDT 24
Peak memory 202096 kb
Host smart-63b2639c-1516-4d56-878d-284591ca6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281273268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.281273268
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3943914511
Short name T514
Test name
Test status
Simulation time 5967281859 ps
CPU time 4.27 seconds
Started May 12 04:10:13 PM PDT 24
Finished May 12 04:10:18 PM PDT 24
Peak memory 202180 kb
Host smart-ab2788b7-123a-4344-a749-ae69c055fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943914511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3943914511
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.4258759142
Short name T331
Test name
Test status
Simulation time 560192338765 ps
CPU time 881.71 seconds
Started May 12 04:10:21 PM PDT 24
Finished May 12 04:25:03 PM PDT 24
Peak memory 202640 kb
Host smart-109855cc-386f-45fa-8c1a-d7e05ec64785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258759142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.4258759142
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2128583097
Short name T429
Test name
Test status
Simulation time 500065836 ps
CPU time 0.91 seconds
Started May 12 04:10:24 PM PDT 24
Finished May 12 04:10:26 PM PDT 24
Peak memory 201996 kb
Host smart-f5bf7ad6-6a57-41fe-836e-c6eb3ab74ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128583097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2128583097
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4171978324
Short name T286
Test name
Test status
Simulation time 481583053078 ps
CPU time 1168.26 seconds
Started May 12 04:10:18 PM PDT 24
Finished May 12 04:29:47 PM PDT 24
Peak memory 202320 kb
Host smart-7dcc3363-0a2c-4b87-9db2-28d9d83b1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171978324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4171978324
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2880548868
Short name T457
Test name
Test status
Simulation time 488244100718 ps
CPU time 582.78 seconds
Started May 12 04:10:21 PM PDT 24
Finished May 12 04:20:04 PM PDT 24
Peak memory 202296 kb
Host smart-1f72ca47-6148-4098-8c8e-5ecada22d74b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880548868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2880548868
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1314161018
Short name T439
Test name
Test status
Simulation time 162690495201 ps
CPU time 399.86 seconds
Started May 12 04:10:18 PM PDT 24
Finished May 12 04:16:59 PM PDT 24
Peak memory 202252 kb
Host smart-f18fcedd-184a-409d-9175-26ce0e6cd21e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314161018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1314161018
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3865683022
Short name T111
Test name
Test status
Simulation time 443524367353 ps
CPU time 273.27 seconds
Started May 12 04:10:21 PM PDT 24
Finished May 12 04:14:54 PM PDT 24
Peak memory 202356 kb
Host smart-dc306f53-c6c9-4191-8cf1-534faec1250b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865683022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3865683022
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3887119512
Short name T796
Test name
Test status
Simulation time 213191863162 ps
CPU time 532.1 seconds
Started May 12 04:10:23 PM PDT 24
Finished May 12 04:19:15 PM PDT 24
Peak memory 202268 kb
Host smart-065d2cde-3b52-4cb3-8247-f61e8525651f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887119512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3887119512
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.83884811
Short name T729
Test name
Test status
Simulation time 81997462830 ps
CPU time 357.9 seconds
Started May 12 04:10:25 PM PDT 24
Finished May 12 04:16:24 PM PDT 24
Peak memory 202768 kb
Host smart-3fe4dd0e-95c5-47f0-b165-32cbd3044fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83884811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.83884811
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2561577930
Short name T376
Test name
Test status
Simulation time 39911956871 ps
CPU time 25.1 seconds
Started May 12 04:10:23 PM PDT 24
Finished May 12 04:10:49 PM PDT 24
Peak memory 202140 kb
Host smart-912754fe-d2d7-4586-b3e7-09c8adf79df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561577930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2561577930
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1480836659
Short name T606
Test name
Test status
Simulation time 3138176068 ps
CPU time 7.12 seconds
Started May 12 04:10:23 PM PDT 24
Finished May 12 04:10:31 PM PDT 24
Peak memory 202136 kb
Host smart-74820487-2cfa-4a33-a8dd-506dcc89c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480836659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1480836659
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4189435785
Short name T86
Test name
Test status
Simulation time 5922900494 ps
CPU time 5.03 seconds
Started May 12 04:10:20 PM PDT 24
Finished May 12 04:10:25 PM PDT 24
Peak memory 202120 kb
Host smart-10bd44e3-6cff-4192-9713-95e9c1432b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189435785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4189435785
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1441761560
Short name T574
Test name
Test status
Simulation time 391152564561 ps
CPU time 123.23 seconds
Started May 12 04:10:25 PM PDT 24
Finished May 12 04:12:28 PM PDT 24
Peak memory 202408 kb
Host smart-56648134-0d33-44ca-b6b2-361dbd1d09e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441761560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1441761560
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.680858708
Short name T689
Test name
Test status
Simulation time 247962412231 ps
CPU time 158.96 seconds
Started May 12 04:10:23 PM PDT 24
Finished May 12 04:13:03 PM PDT 24
Peak memory 219148 kb
Host smart-6b937289-2224-4359-8b0f-8771a82ece9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680858708 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.680858708
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.661444320
Short name T413
Test name
Test status
Simulation time 363751324 ps
CPU time 1.44 seconds
Started May 12 04:10:35 PM PDT 24
Finished May 12 04:10:36 PM PDT 24
Peak memory 201988 kb
Host smart-6fb2b1d3-4beb-403c-81a7-8e96ad855ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661444320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.661444320
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2813703000
Short name T4
Test name
Test status
Simulation time 335484618221 ps
CPU time 613.74 seconds
Started May 12 04:10:35 PM PDT 24
Finished May 12 04:20:49 PM PDT 24
Peak memory 202332 kb
Host smart-baf1bf68-e2fa-4360-a65b-8dd3d3d35447
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813703000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2813703000
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1833699066
Short name T190
Test name
Test status
Simulation time 196018064818 ps
CPU time 475.92 seconds
Started May 12 04:10:30 PM PDT 24
Finished May 12 04:18:26 PM PDT 24
Peak memory 202316 kb
Host smart-af1e70e5-c64b-46f5-9146-c753d9888484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833699066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1833699066
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3284268204
Short name T119
Test name
Test status
Simulation time 487573308583 ps
CPU time 1002.46 seconds
Started May 12 04:10:28 PM PDT 24
Finished May 12 04:27:11 PM PDT 24
Peak memory 202272 kb
Host smart-d85038f4-5b44-4b62-b84a-84cbb109ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284268204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3284268204
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2927642378
Short name T601
Test name
Test status
Simulation time 498942990544 ps
CPU time 300.23 seconds
Started May 12 04:10:30 PM PDT 24
Finished May 12 04:15:30 PM PDT 24
Peak memory 202280 kb
Host smart-5e4e5559-96f6-4106-bc62-0745a752bbea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927642378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2927642378
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1417687088
Short name T545
Test name
Test status
Simulation time 331513176296 ps
CPU time 152.94 seconds
Started May 12 04:10:25 PM PDT 24
Finished May 12 04:12:59 PM PDT 24
Peak memory 202280 kb
Host smart-6156607b-dc2f-4703-972b-17d24c2fda0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417687088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1417687088
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3311505946
Short name T733
Test name
Test status
Simulation time 166968201489 ps
CPU time 96.9 seconds
Started May 12 04:10:30 PM PDT 24
Finished May 12 04:12:07 PM PDT 24
Peak memory 202256 kb
Host smart-9db32dbf-8b1e-4fde-838c-6c50ccba8293
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311505946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3311505946
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2894950554
Short name T779
Test name
Test status
Simulation time 558402560554 ps
CPU time 1077.2 seconds
Started May 12 04:10:31 PM PDT 24
Finished May 12 04:28:29 PM PDT 24
Peak memory 202440 kb
Host smart-cd363ba7-3c4c-457e-9f95-bf90fc5519a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894950554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2894950554
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.666815900
Short name T565
Test name
Test status
Simulation time 412112548769 ps
CPU time 256.73 seconds
Started May 12 04:10:30 PM PDT 24
Finished May 12 04:14:47 PM PDT 24
Peak memory 202348 kb
Host smart-26d2bfb7-e42c-4850-beaa-8c3cd3b928fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666815900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.666815900
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2474036632
Short name T567
Test name
Test status
Simulation time 85336087848 ps
CPU time 416.84 seconds
Started May 12 04:10:31 PM PDT 24
Finished May 12 04:17:29 PM PDT 24
Peak memory 202752 kb
Host smart-0c278f84-fdff-4aa0-8115-eaf027653bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474036632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2474036632
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3088514107
Short name T410
Test name
Test status
Simulation time 43770417107 ps
CPU time 105.99 seconds
Started May 12 04:10:32 PM PDT 24
Finished May 12 04:12:19 PM PDT 24
Peak memory 202140 kb
Host smart-01796193-3b05-46df-b929-438ec6465112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088514107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3088514107
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3868577503
Short name T488
Test name
Test status
Simulation time 4222067097 ps
CPU time 10.2 seconds
Started May 12 04:10:32 PM PDT 24
Finished May 12 04:10:43 PM PDT 24
Peak memory 202324 kb
Host smart-539e7e75-3ad8-439c-bbf3-d3c5cff04d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868577503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3868577503
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3021751354
Short name T654
Test name
Test status
Simulation time 5781957349 ps
CPU time 14.83 seconds
Started May 12 04:10:25 PM PDT 24
Finished May 12 04:10:40 PM PDT 24
Peak memory 202148 kb
Host smart-daa46caf-215e-4b3e-bc2c-1e9bcd2a0964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021751354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3021751354
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.569315298
Short name T758
Test name
Test status
Simulation time 110917518782 ps
CPU time 162.21 seconds
Started May 12 04:10:33 PM PDT 24
Finished May 12 04:13:15 PM PDT 24
Peak memory 211432 kb
Host smart-6d15ffd8-2a95-4424-91bb-ea429d310a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569315298 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.569315298
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1970234906
Short name T344
Test name
Test status
Simulation time 353052412 ps
CPU time 0.97 seconds
Started May 12 04:10:45 PM PDT 24
Finished May 12 04:10:46 PM PDT 24
Peak memory 202208 kb
Host smart-bc456eca-8ca4-440e-afec-10cb76afee58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970234906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1970234906
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1850509652
Short name T573
Test name
Test status
Simulation time 357227626667 ps
CPU time 214.49 seconds
Started May 12 04:10:37 PM PDT 24
Finished May 12 04:14:12 PM PDT 24
Peak memory 202248 kb
Host smart-d30fd750-42d0-443f-87d2-c85ddd0d36dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850509652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1850509652
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1261013216
Short name T641
Test name
Test status
Simulation time 332201848498 ps
CPU time 193.61 seconds
Started May 12 04:10:39 PM PDT 24
Finished May 12 04:13:53 PM PDT 24
Peak memory 202316 kb
Host smart-b9453179-169a-40e5-b49f-a4a882157143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261013216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1261013216
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1003739383
Short name T726
Test name
Test status
Simulation time 164609805754 ps
CPU time 194.75 seconds
Started May 12 04:10:38 PM PDT 24
Finished May 12 04:13:54 PM PDT 24
Peak memory 202264 kb
Host smart-7e2a1970-8cc3-4a63-824f-6c7d62da9ade
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003739383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1003739383
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.916213447
Short name T133
Test name
Test status
Simulation time 489691018758 ps
CPU time 126.46 seconds
Started May 12 04:10:37 PM PDT 24
Finished May 12 04:12:44 PM PDT 24
Peak memory 202384 kb
Host smart-5e0dc627-d6e2-4a8c-87d9-7b90465809c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916213447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.916213447
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.933789946
Short name T121
Test name
Test status
Simulation time 333618991857 ps
CPU time 65.89 seconds
Started May 12 04:10:33 PM PDT 24
Finished May 12 04:11:39 PM PDT 24
Peak memory 202328 kb
Host smart-72311334-c188-49bd-826f-56c1a8e98fb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=933789946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.933789946
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2109686452
Short name T578
Test name
Test status
Simulation time 190906369300 ps
CPU time 45.82 seconds
Started May 12 04:10:38 PM PDT 24
Finished May 12 04:11:24 PM PDT 24
Peak memory 202404 kb
Host smart-a30c46e7-4dfd-4775-986e-2bae9dbd62d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109686452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2109686452
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2588907309
Short name T326
Test name
Test status
Simulation time 62955124811 ps
CPU time 372.72 seconds
Started May 12 04:10:39 PM PDT 24
Finished May 12 04:16:52 PM PDT 24
Peak memory 202744 kb
Host smart-046812f3-97ea-4981-83cc-e96a587d2c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588907309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2588907309
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2529802147
Short name T399
Test name
Test status
Simulation time 35835428056 ps
CPU time 89.17 seconds
Started May 12 04:10:41 PM PDT 24
Finished May 12 04:12:11 PM PDT 24
Peak memory 202152 kb
Host smart-51e4d07e-07e5-494b-b490-f14ed90c682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529802147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2529802147
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1842167049
Short name T512
Test name
Test status
Simulation time 5116336171 ps
CPU time 13.2 seconds
Started May 12 04:10:41 PM PDT 24
Finished May 12 04:10:54 PM PDT 24
Peak memory 202136 kb
Host smart-295dec6c-a41d-4224-97e3-a768ee055aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842167049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1842167049
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3350706648
Short name T528
Test name
Test status
Simulation time 5919106685 ps
CPU time 3.95 seconds
Started May 12 04:10:34 PM PDT 24
Finished May 12 04:10:38 PM PDT 24
Peak memory 202160 kb
Host smart-73ec2262-35c3-4bd1-97f3-1d25be18a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350706648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3350706648
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3045761658
Short name T207
Test name
Test status
Simulation time 173747423356 ps
CPU time 376.65 seconds
Started May 12 04:10:42 PM PDT 24
Finished May 12 04:17:00 PM PDT 24
Peak memory 202384 kb
Host smart-bdcbd3e4-0ccd-475e-acad-378d42376f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045761658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3045761658
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3321274632
Short name T75
Test name
Test status
Simulation time 129587514607 ps
CPU time 249.1 seconds
Started May 12 04:10:43 PM PDT 24
Finished May 12 04:14:52 PM PDT 24
Peak memory 217056 kb
Host smart-12496ec8-9ac5-465d-a16a-1fc19e0f63fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321274632 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3321274632
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3923056259
Short name T15
Test name
Test status
Simulation time 372823863 ps
CPU time 1.41 seconds
Started May 12 04:10:53 PM PDT 24
Finished May 12 04:10:55 PM PDT 24
Peak memory 202048 kb
Host smart-65a23a4d-8ffb-4202-8256-4cfe08fc87ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923056259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3923056259
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3556141487
Short name T149
Test name
Test status
Simulation time 605110453069 ps
CPU time 250.53 seconds
Started May 12 04:10:48 PM PDT 24
Finished May 12 04:14:59 PM PDT 24
Peak memory 202276 kb
Host smart-30402e9c-5236-47d5-bb34-8a9ac4086c71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556141487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3556141487
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4090549709
Short name T605
Test name
Test status
Simulation time 164478162891 ps
CPU time 340.73 seconds
Started May 12 04:10:52 PM PDT 24
Finished May 12 04:16:33 PM PDT 24
Peak memory 202328 kb
Host smart-b214e704-0d76-4d7c-a039-388ce915f648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090549709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4090549709
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3483195198
Short name T635
Test name
Test status
Simulation time 324317167101 ps
CPU time 753.01 seconds
Started May 12 04:10:46 PM PDT 24
Finished May 12 04:23:19 PM PDT 24
Peak memory 202324 kb
Host smart-ac8d923e-c7f9-418f-b910-7cd17deaa0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483195198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3483195198
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2718611466
Short name T766
Test name
Test status
Simulation time 483295042934 ps
CPU time 857.6 seconds
Started May 12 04:10:47 PM PDT 24
Finished May 12 04:25:05 PM PDT 24
Peak memory 202256 kb
Host smart-5ff94e42-6725-403a-8bbe-d37b79c5a48b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718611466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2718611466
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1075985658
Short name T435
Test name
Test status
Simulation time 388919604247 ps
CPU time 871.7 seconds
Started May 12 04:10:52 PM PDT 24
Finished May 12 04:25:24 PM PDT 24
Peak memory 202332 kb
Host smart-0bcebf22-9545-450c-8252-6f1118f1ba11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075985658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1075985658
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2452514300
Short name T329
Test name
Test status
Simulation time 127871940488 ps
CPU time 636.73 seconds
Started May 12 04:10:52 PM PDT 24
Finished May 12 04:21:29 PM PDT 24
Peak memory 202744 kb
Host smart-f4ed9090-45d4-4f5f-a9fe-7cf9c9e6316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452514300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2452514300
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2264434680
Short name T145
Test name
Test status
Simulation time 32465791377 ps
CPU time 15.11 seconds
Started May 12 04:10:53 PM PDT 24
Finished May 12 04:11:09 PM PDT 24
Peak memory 202088 kb
Host smart-a3aabc44-1fe6-4b85-b6f9-c17dae138320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264434680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2264434680
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1759484329
Short name T412
Test name
Test status
Simulation time 3359753194 ps
CPU time 8.8 seconds
Started May 12 04:10:48 PM PDT 24
Finished May 12 04:10:58 PM PDT 24
Peak memory 202172 kb
Host smart-ff8460be-4300-4c6f-ab36-bf372e026239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759484329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1759484329
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2853875053
Short name T441
Test name
Test status
Simulation time 5610569430 ps
CPU time 14.84 seconds
Started May 12 04:10:44 PM PDT 24
Finished May 12 04:11:00 PM PDT 24
Peak memory 202144 kb
Host smart-1b4c32f6-59ea-4002-bd20-21f3db095b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853875053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2853875053
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2680938195
Short name T267
Test name
Test status
Simulation time 345642797677 ps
CPU time 206.44 seconds
Started May 12 04:10:51 PM PDT 24
Finished May 12 04:14:18 PM PDT 24
Peak memory 202368 kb
Host smart-2d1192bd-8856-4b83-9584-29dcb77e8964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680938195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2680938195
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3818157376
Short name T666
Test name
Test status
Simulation time 323832970 ps
CPU time 1.4 seconds
Started May 12 04:11:01 PM PDT 24
Finished May 12 04:11:03 PM PDT 24
Peak memory 202048 kb
Host smart-325fa1b3-93b7-407f-b3e4-1b70a3604b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818157376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3818157376
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2112212654
Short name T213
Test name
Test status
Simulation time 198732446392 ps
CPU time 59.34 seconds
Started May 12 04:10:56 PM PDT 24
Finished May 12 04:11:55 PM PDT 24
Peak memory 202280 kb
Host smart-1781ced8-45ea-43c5-80fa-8f4574798710
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112212654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2112212654
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1501549849
Short name T152
Test name
Test status
Simulation time 322732497728 ps
CPU time 199.65 seconds
Started May 12 04:10:56 PM PDT 24
Finished May 12 04:14:16 PM PDT 24
Peak memory 202380 kb
Host smart-a3b1d3c9-9903-4b77-8f70-c362ab49a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501549849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1501549849
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3390754863
Short name T671
Test name
Test status
Simulation time 333275887947 ps
CPU time 804.18 seconds
Started May 12 04:10:55 PM PDT 24
Finished May 12 04:24:20 PM PDT 24
Peak memory 202352 kb
Host smart-b7329142-d662-4661-b512-c3f779ca9dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390754863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3390754863
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.988949858
Short name T424
Test name
Test status
Simulation time 325096269868 ps
CPU time 608.73 seconds
Started May 12 04:10:55 PM PDT 24
Finished May 12 04:21:04 PM PDT 24
Peak memory 202312 kb
Host smart-eaf7f8ce-bc03-4ace-bdd9-b4c1646450bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=988949858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.988949858
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.766677377
Short name T72
Test name
Test status
Simulation time 323251345719 ps
CPU time 687.29 seconds
Started May 12 04:10:55 PM PDT 24
Finished May 12 04:22:23 PM PDT 24
Peak memory 202292 kb
Host smart-f58ab14d-f645-46b3-b813-623a5ff7fe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766677377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.766677377
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3526430505
Short name T349
Test name
Test status
Simulation time 495667751333 ps
CPU time 1163.07 seconds
Started May 12 04:10:57 PM PDT 24
Finished May 12 04:30:20 PM PDT 24
Peak memory 202320 kb
Host smart-e4d79650-c845-48b1-8e16-f0ac5033d8c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526430505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3526430505
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2160075533
Short name T748
Test name
Test status
Simulation time 550276854681 ps
CPU time 1060.85 seconds
Started May 12 04:10:56 PM PDT 24
Finished May 12 04:28:37 PM PDT 24
Peak memory 202368 kb
Host smart-b390da11-a75c-4e7d-b134-9a74d8f2e59d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160075533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2160075533
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.4150874572
Short name T130
Test name
Test status
Simulation time 202383338632 ps
CPU time 422.31 seconds
Started May 12 04:10:56 PM PDT 24
Finished May 12 04:17:59 PM PDT 24
Peak memory 202276 kb
Host smart-fe8192f3-e778-47fa-8db1-bc27bc383232
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150874572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.4150874572
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2386544285
Short name T715
Test name
Test status
Simulation time 90149139076 ps
CPU time 309.88 seconds
Started May 12 04:10:56 PM PDT 24
Finished May 12 04:16:06 PM PDT 24
Peak memory 202632 kb
Host smart-645fcdb1-c40a-48b3-8ec0-374a97ac6ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386544285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2386544285
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.611372804
Short name T338
Test name
Test status
Simulation time 28700083703 ps
CPU time 16.99 seconds
Started May 12 04:10:54 PM PDT 24
Finished May 12 04:11:11 PM PDT 24
Peak memory 202164 kb
Host smart-2f494613-399d-4c6c-9413-426a4ac1f02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611372804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.611372804
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2253019264
Short name T760
Test name
Test status
Simulation time 2794706652 ps
CPU time 7.17 seconds
Started May 12 04:10:55 PM PDT 24
Finished May 12 04:11:02 PM PDT 24
Peak memory 202024 kb
Host smart-07e24ebd-2d16-4161-8aee-baf44ce7bd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253019264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2253019264
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3294182621
Short name T25
Test name
Test status
Simulation time 5865454759 ps
CPU time 3.79 seconds
Started May 12 04:10:52 PM PDT 24
Finished May 12 04:10:57 PM PDT 24
Peak memory 202036 kb
Host smart-fca3e1e0-bfe9-404e-abdd-28145e265910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294182621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3294182621
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1869165362
Short name T118
Test name
Test status
Simulation time 338424586936 ps
CPU time 801.41 seconds
Started May 12 04:10:59 PM PDT 24
Finished May 12 04:24:21 PM PDT 24
Peak memory 202384 kb
Host smart-ecbdfc3f-f40a-4ef9-9b62-c701b38c7e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869165362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1869165362
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3336155377
Short name T22
Test name
Test status
Simulation time 231978045604 ps
CPU time 293.36 seconds
Started May 12 04:10:57 PM PDT 24
Finished May 12 04:15:51 PM PDT 24
Peak memory 211060 kb
Host smart-d1f42239-20d6-449f-b353-df1c35bbed5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336155377 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3336155377
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2870893006
Short name T482
Test name
Test status
Simulation time 531885124 ps
CPU time 1.71 seconds
Started May 12 04:11:10 PM PDT 24
Finished May 12 04:11:12 PM PDT 24
Peak memory 202200 kb
Host smart-646a95ed-a5bb-4f61-8591-9d9d461231f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870893006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2870893006
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.150335506
Short name T612
Test name
Test status
Simulation time 189162066685 ps
CPU time 114.92 seconds
Started May 12 04:11:03 PM PDT 24
Finished May 12 04:12:58 PM PDT 24
Peak memory 202388 kb
Host smart-a484e76a-7ef0-4ea8-b5f1-3e2c921e909c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150335506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.150335506
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3464333081
Short name T243
Test name
Test status
Simulation time 491387226947 ps
CPU time 621.69 seconds
Started May 12 04:11:02 PM PDT 24
Finished May 12 04:21:24 PM PDT 24
Peak memory 202316 kb
Host smart-64741f58-a08f-4ae6-992f-a2a3d2f918bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464333081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3464333081
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.873118748
Short name T775
Test name
Test status
Simulation time 491320340554 ps
CPU time 602.01 seconds
Started May 12 04:11:04 PM PDT 24
Finished May 12 04:21:06 PM PDT 24
Peak memory 202376 kb
Host smart-6238a992-4f86-48e8-b737-609cd6beed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873118748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.873118748
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.191343469
Short name T526
Test name
Test status
Simulation time 165038054024 ps
CPU time 107.58 seconds
Started May 12 04:11:03 PM PDT 24
Finished May 12 04:12:51 PM PDT 24
Peak memory 202268 kb
Host smart-83606618-34d0-4f6e-bedb-8071bd6870d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=191343469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.191343469
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.4175515929
Short name T141
Test name
Test status
Simulation time 488808264320 ps
CPU time 271.07 seconds
Started May 12 04:11:05 PM PDT 24
Finished May 12 04:15:37 PM PDT 24
Peak memory 202296 kb
Host smart-27da4490-c872-40c9-b69e-a354ce396823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175515929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4175515929
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1909609074
Short name T554
Test name
Test status
Simulation time 487291592998 ps
CPU time 1088.99 seconds
Started May 12 04:11:03 PM PDT 24
Finished May 12 04:29:13 PM PDT 24
Peak memory 202304 kb
Host smart-477467cd-180a-40ea-87ca-2b7cb2f4ccf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909609074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1909609074
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.689678661
Short name T741
Test name
Test status
Simulation time 348143366997 ps
CPU time 104.31 seconds
Started May 12 04:11:04 PM PDT 24
Finished May 12 04:12:49 PM PDT 24
Peak memory 202320 kb
Host smart-53d6458b-1e14-4f7b-8f40-f3933e4a1949
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689678661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.689678661
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1365843605
Short name T382
Test name
Test status
Simulation time 210919247765 ps
CPU time 131.06 seconds
Started May 12 04:11:02 PM PDT 24
Finished May 12 04:13:13 PM PDT 24
Peak memory 202280 kb
Host smart-4b967ed9-f20f-439c-b38d-8cf6d16e9e29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365843605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1365843605
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1075283894
Short name T624
Test name
Test status
Simulation time 104528400191 ps
CPU time 339.64 seconds
Started May 12 04:11:07 PM PDT 24
Finished May 12 04:16:47 PM PDT 24
Peak memory 202716 kb
Host smart-7d3da758-2cca-4cc1-9e59-fe52d2c2ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075283894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1075283894
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3637165317
Short name T492
Test name
Test status
Simulation time 34373984161 ps
CPU time 8.37 seconds
Started May 12 04:11:05 PM PDT 24
Finished May 12 04:11:14 PM PDT 24
Peak memory 202176 kb
Host smart-0ac292c9-c908-4d1e-961f-98c4801406f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637165317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3637165317
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.646100225
Short name T789
Test name
Test status
Simulation time 5043072856 ps
CPU time 7.2 seconds
Started May 12 04:11:07 PM PDT 24
Finished May 12 04:11:14 PM PDT 24
Peak memory 202112 kb
Host smart-3af0b3d4-b696-4ff4-ad63-7f0ba8a819be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646100225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.646100225
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1798548057
Short name T493
Test name
Test status
Simulation time 5702858874 ps
CPU time 4.1 seconds
Started May 12 04:11:04 PM PDT 24
Finished May 12 04:11:08 PM PDT 24
Peak memory 202136 kb
Host smart-fb50cd11-2289-498b-a7d6-a0ced274a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798548057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1798548057
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2897715431
Short name T298
Test name
Test status
Simulation time 336653886177 ps
CPU time 753.25 seconds
Started May 12 04:11:06 PM PDT 24
Finished May 12 04:23:40 PM PDT 24
Peak memory 202392 kb
Host smart-a4f94707-2abb-4a03-ac14-679a022fc41e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897715431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2897715431
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3570885018
Short name T622
Test name
Test status
Simulation time 293385930 ps
CPU time 0.95 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:09:13 PM PDT 24
Peak memory 201928 kb
Host smart-1c216a8d-f89f-4946-bc7b-f2beb373397e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570885018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3570885018
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2657536665
Short name T290
Test name
Test status
Simulation time 210284782411 ps
CPU time 9.67 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:09:18 PM PDT 24
Peak memory 202312 kb
Host smart-e81e0cd8-30fe-4b6c-a9f7-531f1f0e173b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657536665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2657536665
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1701836140
Short name T294
Test name
Test status
Simulation time 185763420512 ps
CPU time 238.99 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:13:11 PM PDT 24
Peak memory 202340 kb
Host smart-2860ae8f-3d20-4441-9da0-7eec19bc6192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701836140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1701836140
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4158125794
Short name T127
Test name
Test status
Simulation time 495331832584 ps
CPU time 149.82 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:11:42 PM PDT 24
Peak memory 202320 kb
Host smart-d57d01f5-9e32-40b2-88e0-295e845445a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158125794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4158125794
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2143400544
Short name T409
Test name
Test status
Simulation time 328508171263 ps
CPU time 202.25 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:12:35 PM PDT 24
Peak memory 202252 kb
Host smart-2f868c4f-1b7b-45a3-ae45-ac81a45e0639
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143400544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2143400544
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1143407524
Short name T428
Test name
Test status
Simulation time 488842139001 ps
CPU time 241.65 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:13:12 PM PDT 24
Peak memory 202300 kb
Host smart-39cd757f-8eb5-42b4-a26c-bd4aacd90739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143407524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1143407524
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3538561276
Short name T389
Test name
Test status
Simulation time 326487547978 ps
CPU time 373.58 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:15:24 PM PDT 24
Peak memory 202372 kb
Host smart-3b5b5d3d-676a-474d-a28f-118f5acf31c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538561276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3538561276
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3722170803
Short name T721
Test name
Test status
Simulation time 531953561805 ps
CPU time 288.11 seconds
Started May 12 04:09:07 PM PDT 24
Finished May 12 04:13:56 PM PDT 24
Peak memory 202428 kb
Host smart-14cdffb8-8cf7-48ba-9812-58cf06b06029
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722170803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3722170803
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1205613475
Short name T366
Test name
Test status
Simulation time 594679756942 ps
CPU time 655.11 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:20:11 PM PDT 24
Peak memory 201916 kb
Host smart-8169a3ee-a67b-4aa1-80d7-53ce5a3d8def
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205613475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1205613475
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.553082322
Short name T396
Test name
Test status
Simulation time 136345095952 ps
CPU time 577.41 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:18:50 PM PDT 24
Peak memory 202696 kb
Host smart-d8672690-f32e-432b-bd71-fb83b2895535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553082322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.553082322
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.229628051
Short name T83
Test name
Test status
Simulation time 29149374701 ps
CPU time 68.21 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:10:17 PM PDT 24
Peak memory 202012 kb
Host smart-cc9f045c-3ed9-4992-8189-329ff89fd895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229628051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.229628051
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2596841902
Short name T614
Test name
Test status
Simulation time 3753471249 ps
CPU time 2.81 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:09:12 PM PDT 24
Peak memory 202160 kb
Host smart-3b8c62fd-b280-4a8c-a2d3-ff8e0d8f97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596841902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2596841902
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3973566049
Short name T68
Test name
Test status
Simulation time 8180202947 ps
CPU time 20.37 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:09:33 PM PDT 24
Peak memory 218908 kb
Host smart-8e2870f4-da69-4885-a73f-7db4c5cccfa8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973566049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3973566049
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1914171576
Short name T650
Test name
Test status
Simulation time 5780099555 ps
CPU time 4.35 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:09:15 PM PDT 24
Peak memory 202156 kb
Host smart-0fcd107b-0f88-4d1b-8b09-864dfb99bea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914171576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1914171576
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.933159805
Short name T460
Test name
Test status
Simulation time 161790153722 ps
CPU time 195.12 seconds
Started May 12 04:09:08 PM PDT 24
Finished May 12 04:12:24 PM PDT 24
Peak memory 202308 kb
Host smart-e852a725-70db-4cc2-896f-7d0e436b6929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933159805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.933159805
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3878541297
Short name T266
Test name
Test status
Simulation time 96692149991 ps
CPU time 225.01 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:12:58 PM PDT 24
Peak memory 211948 kb
Host smart-775d3f9c-295b-4375-8af6-38373c5350a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878541297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3878541297
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.401979566
Short name T61
Test name
Test status
Simulation time 374065632 ps
CPU time 0.8 seconds
Started May 12 04:11:18 PM PDT 24
Finished May 12 04:11:19 PM PDT 24
Peak memory 201984 kb
Host smart-b4a1c40b-0c61-49dc-98cb-cf3b69021eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401979566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.401979566
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3105932624
Short name T722
Test name
Test status
Simulation time 497049664559 ps
CPU time 1203.79 seconds
Started May 12 04:11:09 PM PDT 24
Finished May 12 04:31:14 PM PDT 24
Peak memory 202308 kb
Host smart-45d198e2-2809-492b-9b53-eeec0367c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105932624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3105932624
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2898086571
Short name T644
Test name
Test status
Simulation time 489301166310 ps
CPU time 1220.87 seconds
Started May 12 04:11:08 PM PDT 24
Finished May 12 04:31:29 PM PDT 24
Peak memory 202332 kb
Host smart-b184d9bf-2b6e-492e-adb0-5471be86876c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898086571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2898086571
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.880019092
Short name T406
Test name
Test status
Simulation time 164058816901 ps
CPU time 370.71 seconds
Started May 12 04:11:09 PM PDT 24
Finished May 12 04:17:21 PM PDT 24
Peak memory 202288 kb
Host smart-818ababb-06b1-4822-ad96-8441e0f7f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880019092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.880019092
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.684733074
Short name T391
Test name
Test status
Simulation time 487431647420 ps
CPU time 526.54 seconds
Started May 12 04:11:11 PM PDT 24
Finished May 12 04:19:58 PM PDT 24
Peak memory 202300 kb
Host smart-1f22a2f1-700d-4c4a-9eb8-77f8cbf54648
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684733074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.684733074
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.913652796
Short name T464
Test name
Test status
Simulation time 182758552078 ps
CPU time 116.38 seconds
Started May 12 04:11:11 PM PDT 24
Finished May 12 04:13:08 PM PDT 24
Peak memory 202396 kb
Host smart-ba2d9ae2-5fb3-4415-b609-5aaf7b7735a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913652796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.913652796
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3790422832
Short name T388
Test name
Test status
Simulation time 596440842259 ps
CPU time 194.78 seconds
Started May 12 04:11:13 PM PDT 24
Finished May 12 04:14:28 PM PDT 24
Peak memory 202252 kb
Host smart-55d440fe-e9b2-4cd3-962e-c44758ba67b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790422832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3790422832
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2643528866
Short name T653
Test name
Test status
Simulation time 135018487004 ps
CPU time 439.32 seconds
Started May 12 04:11:13 PM PDT 24
Finished May 12 04:18:32 PM PDT 24
Peak memory 202660 kb
Host smart-ba2501a0-46aa-47fc-bc79-51605aa3f3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643528866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2643528866
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2217414511
Short name T465
Test name
Test status
Simulation time 31688237049 ps
CPU time 19.62 seconds
Started May 12 04:11:12 PM PDT 24
Finished May 12 04:11:32 PM PDT 24
Peak memory 202152 kb
Host smart-de3744e2-4bef-4d2e-abb2-0fbe276d23a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217414511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2217414511
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.297339117
Short name T648
Test name
Test status
Simulation time 4766339668 ps
CPU time 3.91 seconds
Started May 12 04:11:13 PM PDT 24
Finished May 12 04:11:17 PM PDT 24
Peak memory 202120 kb
Host smart-1c26edab-b3c4-4ec8-8fa7-fe0a3a80e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297339117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.297339117
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.706524341
Short name T479
Test name
Test status
Simulation time 5647290749 ps
CPU time 9.89 seconds
Started May 12 04:11:11 PM PDT 24
Finished May 12 04:11:22 PM PDT 24
Peak memory 202092 kb
Host smart-1878da4c-0db5-4dc5-8af0-177f3d52df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706524341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.706524341
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3592833655
Short name T519
Test name
Test status
Simulation time 96916145305 ps
CPU time 329.69 seconds
Started May 12 04:11:13 PM PDT 24
Finished May 12 04:16:43 PM PDT 24
Peak memory 210844 kb
Host smart-51a8724f-2e3d-4abb-abc6-830e301ad83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592833655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3592833655
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2164060419
Short name T520
Test name
Test status
Simulation time 55850029120 ps
CPU time 134.2 seconds
Started May 12 04:11:12 PM PDT 24
Finished May 12 04:13:27 PM PDT 24
Peak memory 211976 kb
Host smart-a8cfaf96-aadd-4982-8978-908f2dcf1859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164060419 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2164060419
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1494815002
Short name T680
Test name
Test status
Simulation time 528017402 ps
CPU time 1.72 seconds
Started May 12 04:11:29 PM PDT 24
Finished May 12 04:11:31 PM PDT 24
Peak memory 202204 kb
Host smart-c318e0a7-9cfa-4765-8683-d9826dc4ce5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494815002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1494815002
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.28812694
Short name T495
Test name
Test status
Simulation time 190701473237 ps
CPU time 162.26 seconds
Started May 12 04:11:21 PM PDT 24
Finished May 12 04:14:04 PM PDT 24
Peak memory 202376 kb
Host smart-e766f854-ae2b-4cea-9d2b-ba38ba070e92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28812694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gatin
g.28812694
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3803284586
Short name T489
Test name
Test status
Simulation time 164263051913 ps
CPU time 364.91 seconds
Started May 12 04:11:20 PM PDT 24
Finished May 12 04:17:25 PM PDT 24
Peak memory 202480 kb
Host smart-ab3d4451-a96f-46b6-845d-b2baeaa992a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803284586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3803284586
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2762546641
Short name T698
Test name
Test status
Simulation time 483760606750 ps
CPU time 1071.3 seconds
Started May 12 04:11:16 PM PDT 24
Finished May 12 04:29:07 PM PDT 24
Peak memory 202392 kb
Host smart-7ff1d23f-41e5-449d-9e59-ceb6c16b9bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762546641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2762546641
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1320003821
Short name T476
Test name
Test status
Simulation time 157632010500 ps
CPU time 183.97 seconds
Started May 12 04:11:17 PM PDT 24
Finished May 12 04:14:21 PM PDT 24
Peak memory 202264 kb
Host smart-fa8661a5-8f4e-43e8-9361-295b5a2c8c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320003821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1320003821
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1963369732
Short name T357
Test name
Test status
Simulation time 612861936248 ps
CPU time 374.63 seconds
Started May 12 04:11:21 PM PDT 24
Finished May 12 04:17:36 PM PDT 24
Peak memory 202304 kb
Host smart-7763b4c8-f6a1-4ec9-978d-7e3e69141aec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963369732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1963369732
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2577189068
Short name T317
Test name
Test status
Simulation time 107938690254 ps
CPU time 365.57 seconds
Started May 12 04:11:25 PM PDT 24
Finished May 12 04:17:31 PM PDT 24
Peak memory 202772 kb
Host smart-45134131-dc0a-4749-ab45-490e1f8a9089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577189068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2577189068
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3531069527
Short name T785
Test name
Test status
Simulation time 30574050460 ps
CPU time 18.14 seconds
Started May 12 04:11:25 PM PDT 24
Finished May 12 04:11:43 PM PDT 24
Peak memory 202328 kb
Host smart-62314e5b-9b97-4a05-8439-f054210340a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531069527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3531069527
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3626004926
Short name T26
Test name
Test status
Simulation time 4431601499 ps
CPU time 2 seconds
Started May 12 04:11:24 PM PDT 24
Finished May 12 04:11:27 PM PDT 24
Peak memory 202148 kb
Host smart-540014d0-e06b-4178-b023-5b36dc144fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626004926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3626004926
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3278759826
Short name T422
Test name
Test status
Simulation time 5893391315 ps
CPU time 1.85 seconds
Started May 12 04:11:15 PM PDT 24
Finished May 12 04:11:17 PM PDT 24
Peak memory 202164 kb
Host smart-21307bc1-beea-4596-bcca-1033bb3ea6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278759826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3278759826
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1208013008
Short name T330
Test name
Test status
Simulation time 124020070000 ps
CPU time 410.19 seconds
Started May 12 04:11:28 PM PDT 24
Finished May 12 04:18:18 PM PDT 24
Peak memory 202640 kb
Host smart-b009d8f3-13d7-4494-93a8-1804b17ea9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208013008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1208013008
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1667443966
Short name T437
Test name
Test status
Simulation time 320345004 ps
CPU time 1.37 seconds
Started May 12 04:11:32 PM PDT 24
Finished May 12 04:11:34 PM PDT 24
Peak memory 201996 kb
Host smart-f9435d65-a466-4d0b-884f-a5dabd4cd700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667443966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1667443966
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.304756551
Short name T676
Test name
Test status
Simulation time 343392579307 ps
CPU time 815.61 seconds
Started May 12 04:11:33 PM PDT 24
Finished May 12 04:25:10 PM PDT 24
Peak memory 202396 kb
Host smart-81d37bfe-4e31-43d7-b586-e4ec208164a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304756551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.304756551
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.209260829
Short name T306
Test name
Test status
Simulation time 497142305055 ps
CPU time 320 seconds
Started May 12 04:11:30 PM PDT 24
Finished May 12 04:16:51 PM PDT 24
Peak memory 202344 kb
Host smart-5328377e-9b5f-4dbc-89a8-4ca1187dd6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209260829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.209260829
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2548323418
Short name T638
Test name
Test status
Simulation time 328700267651 ps
CPU time 195.92 seconds
Started May 12 04:11:30 PM PDT 24
Finished May 12 04:14:47 PM PDT 24
Peak memory 202324 kb
Host smart-1b409eab-b12f-49cf-a0d1-8fe54d386cee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548323418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2548323418
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4189255316
Short name T708
Test name
Test status
Simulation time 165231745164 ps
CPU time 94.47 seconds
Started May 12 04:11:28 PM PDT 24
Finished May 12 04:13:03 PM PDT 24
Peak memory 202396 kb
Host smart-1d5296ae-8cda-4afd-b5a2-c33155202335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189255316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4189255316
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2357720783
Short name T509
Test name
Test status
Simulation time 326518396334 ps
CPU time 698.52 seconds
Started May 12 04:11:28 PM PDT 24
Finished May 12 04:23:07 PM PDT 24
Peak memory 202292 kb
Host smart-637d05ef-eb1b-41a5-a8a3-799d14ef52d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357720783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2357720783
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4189219084
Short name T633
Test name
Test status
Simulation time 201809476498 ps
CPU time 495.79 seconds
Started May 12 04:11:29 PM PDT 24
Finished May 12 04:19:45 PM PDT 24
Peak memory 202432 kb
Host smart-b50d241f-077c-4121-adf5-2f9978ccbea0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189219084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4189219084
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1031360207
Short name T459
Test name
Test status
Simulation time 206922374851 ps
CPU time 221.43 seconds
Started May 12 04:11:28 PM PDT 24
Finished May 12 04:15:10 PM PDT 24
Peak memory 202320 kb
Host smart-f6a89359-2987-4121-baf1-047d641d9d6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031360207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1031360207
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1067466004
Short name T620
Test name
Test status
Simulation time 99612027748 ps
CPU time 586.13 seconds
Started May 12 04:11:35 PM PDT 24
Finished May 12 04:21:22 PM PDT 24
Peak memory 202656 kb
Host smart-22a9c618-8eb4-4d0c-a6fb-994b503d9afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067466004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1067466004
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2146667063
Short name T781
Test name
Test status
Simulation time 25502737297 ps
CPU time 35.85 seconds
Started May 12 04:11:37 PM PDT 24
Finished May 12 04:12:13 PM PDT 24
Peak memory 202176 kb
Host smart-96914836-e1a3-4c7d-8c24-d66fdc46a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146667063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2146667063
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.598438027
Short name T340
Test name
Test status
Simulation time 4119268128 ps
CPU time 2.96 seconds
Started May 12 04:11:33 PM PDT 24
Finished May 12 04:11:37 PM PDT 24
Peak memory 202172 kb
Host smart-7b351b14-110a-45cb-a813-a8309e8365f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598438027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.598438027
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.4035953826
Short name T448
Test name
Test status
Simulation time 6245679659 ps
CPU time 1.74 seconds
Started May 12 04:11:27 PM PDT 24
Finished May 12 04:11:29 PM PDT 24
Peak memory 202136 kb
Host smart-77398434-e3f6-44e7-8fcd-b2c6b370a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035953826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.4035953826
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1979277639
Short name T322
Test name
Test status
Simulation time 1759156206020 ps
CPU time 4272 seconds
Started May 12 04:11:37 PM PDT 24
Finished May 12 05:22:50 PM PDT 24
Peak memory 219108 kb
Host smart-a8c121f3-be63-4230-9500-b8c31bfbb878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979277639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1979277639
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3221575037
Short name T393
Test name
Test status
Simulation time 29848367545 ps
CPU time 103.85 seconds
Started May 12 04:11:34 PM PDT 24
Finished May 12 04:13:18 PM PDT 24
Peak memory 210864 kb
Host smart-ed5444ec-a7ad-4f0b-96a7-59a26b19de95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221575037 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3221575037
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3723619958
Short name T466
Test name
Test status
Simulation time 297926753 ps
CPU time 1.33 seconds
Started May 12 04:11:42 PM PDT 24
Finished May 12 04:11:44 PM PDT 24
Peak memory 202020 kb
Host smart-fb7aa16c-f76e-4941-9a38-df51a71beb48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723619958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3723619958
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.214618474
Short name T265
Test name
Test status
Simulation time 167375096740 ps
CPU time 390.09 seconds
Started May 12 04:11:40 PM PDT 24
Finished May 12 04:18:10 PM PDT 24
Peak memory 202388 kb
Host smart-dd6451cc-fb51-4c6d-8393-c6ce0f40fa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214618474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.214618474
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.22245579
Short name T400
Test name
Test status
Simulation time 486305467768 ps
CPU time 317.33 seconds
Started May 12 04:11:40 PM PDT 24
Finished May 12 04:16:58 PM PDT 24
Peak memory 202300 kb
Host smart-61c6eec1-b712-43c8-8d09-499093a6607a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt
_fixed.22245579
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.359908624
Short name T713
Test name
Test status
Simulation time 164223605522 ps
CPU time 184.09 seconds
Started May 12 04:11:37 PM PDT 24
Finished May 12 04:14:41 PM PDT 24
Peak memory 202308 kb
Host smart-c43e246b-1a7e-4a10-bc72-efc86b81a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359908624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.359908624
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2682570152
Short name T452
Test name
Test status
Simulation time 493001983894 ps
CPU time 592.42 seconds
Started May 12 04:11:36 PM PDT 24
Finished May 12 04:21:29 PM PDT 24
Peak memory 202300 kb
Host smart-a887695d-f48a-4003-b42a-4d0f72f71b94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682570152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2682570152
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2392732264
Short name T217
Test name
Test status
Simulation time 352598074490 ps
CPU time 225.25 seconds
Started May 12 04:11:39 PM PDT 24
Finished May 12 04:15:25 PM PDT 24
Peak memory 202408 kb
Host smart-6894d0b4-6225-4fa1-806b-060bbd5afeeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392732264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2392732264
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.576117762
Short name T727
Test name
Test status
Simulation time 619968630413 ps
CPU time 1329.65 seconds
Started May 12 04:11:39 PM PDT 24
Finished May 12 04:33:49 PM PDT 24
Peak memory 202316 kb
Host smart-3950e078-81c3-40c1-b61b-fd5f5a0bbd3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576117762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.576117762
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1119725751
Short name T746
Test name
Test status
Simulation time 66866570399 ps
CPU time 344.89 seconds
Started May 12 04:11:43 PM PDT 24
Finished May 12 04:17:29 PM PDT 24
Peak memory 202684 kb
Host smart-1050a42d-6fb6-4f23-9188-e06cef901188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119725751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1119725751
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4237016334
Short name T3
Test name
Test status
Simulation time 41082363895 ps
CPU time 12.76 seconds
Started May 12 04:11:43 PM PDT 24
Finished May 12 04:11:57 PM PDT 24
Peak memory 202172 kb
Host smart-89badd5c-1cc7-48f9-b9d7-fbede346486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237016334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4237016334
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3820669711
Short name T550
Test name
Test status
Simulation time 3579823797 ps
CPU time 5.1 seconds
Started May 12 04:11:45 PM PDT 24
Finished May 12 04:11:50 PM PDT 24
Peak memory 202084 kb
Host smart-96519e8e-502f-4f47-b54e-8d9de0d88afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820669711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3820669711
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2074195964
Short name T363
Test name
Test status
Simulation time 5900101704 ps
CPU time 4.46 seconds
Started May 12 04:11:37 PM PDT 24
Finished May 12 04:11:42 PM PDT 24
Peak memory 202180 kb
Host smart-0d19d68a-c27b-452f-8ecb-1dc0c0dbc95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074195964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2074195964
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.598301476
Short name T555
Test name
Test status
Simulation time 277472384678 ps
CPU time 428.4 seconds
Started May 12 04:11:44 PM PDT 24
Finished May 12 04:18:53 PM PDT 24
Peak memory 210888 kb
Host smart-a3d74e81-0f4e-498a-89f4-1a6bd784fe3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598301476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
598301476
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2771102880
Short name T628
Test name
Test status
Simulation time 81592603931 ps
CPU time 240.89 seconds
Started May 12 04:11:43 PM PDT 24
Finished May 12 04:15:45 PM PDT 24
Peak memory 218632 kb
Host smart-e261cbe5-5d73-4c92-a4cd-6abb56be1202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771102880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2771102880
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.977386876
Short name T771
Test name
Test status
Simulation time 466680991 ps
CPU time 0.75 seconds
Started May 12 04:11:52 PM PDT 24
Finished May 12 04:11:53 PM PDT 24
Peak memory 202024 kb
Host smart-14c6f032-aad3-4829-a7be-a55bb6b89136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977386876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.977386876
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.488447193
Short name T215
Test name
Test status
Simulation time 178021316020 ps
CPU time 415 seconds
Started May 12 04:11:46 PM PDT 24
Finished May 12 04:18:42 PM PDT 24
Peak memory 202332 kb
Host smart-6df7bbc2-4265-4c75-80e3-f32b6fde98ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488447193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.488447193
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3998773386
Short name T234
Test name
Test status
Simulation time 491056665679 ps
CPU time 1033.67 seconds
Started May 12 04:11:45 PM PDT 24
Finished May 12 04:28:59 PM PDT 24
Peak memory 202244 kb
Host smart-eb10a7e6-cb79-47db-a1c7-80f3456b8c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998773386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3998773386
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2638120063
Short name T483
Test name
Test status
Simulation time 326444516604 ps
CPU time 373.76 seconds
Started May 12 04:11:47 PM PDT 24
Finished May 12 04:18:01 PM PDT 24
Peak memory 202472 kb
Host smart-93004e4c-2ba7-46f8-8d3f-7599a8f9778d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638120063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2638120063
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.239179721
Short name T499
Test name
Test status
Simulation time 328197617146 ps
CPU time 97.18 seconds
Started May 12 04:11:45 PM PDT 24
Finished May 12 04:13:22 PM PDT 24
Peak memory 202412 kb
Host smart-6eabb499-b2cc-41e1-b396-711cb0e03f30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=239179721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.239179721
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1730009951
Short name T386
Test name
Test status
Simulation time 196233444438 ps
CPU time 225.54 seconds
Started May 12 04:11:46 PM PDT 24
Finished May 12 04:15:32 PM PDT 24
Peak memory 202280 kb
Host smart-6fd9bad0-55be-4b93-95ce-44eeef1e5c07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730009951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1730009951
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2154124842
Short name T472
Test name
Test status
Simulation time 96830299491 ps
CPU time 330.58 seconds
Started May 12 04:11:49 PM PDT 24
Finished May 12 04:17:20 PM PDT 24
Peak memory 202672 kb
Host smart-802bb21b-5b91-4e59-9265-58a45d541011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154124842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2154124842
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3796607204
Short name T430
Test name
Test status
Simulation time 24776752183 ps
CPU time 8.99 seconds
Started May 12 04:11:50 PM PDT 24
Finished May 12 04:11:59 PM PDT 24
Peak memory 202152 kb
Host smart-9fc21f98-4fed-457d-9a7b-f2f14c8d5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796607204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3796607204
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3259456129
Short name T552
Test name
Test status
Simulation time 4462081067 ps
CPU time 3.06 seconds
Started May 12 04:11:50 PM PDT 24
Finished May 12 04:11:53 PM PDT 24
Peak memory 202172 kb
Host smart-c6607aad-c783-4bce-92a8-4a1609a0eaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259456129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3259456129
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4248721452
Short name T541
Test name
Test status
Simulation time 5600057145 ps
CPU time 3.85 seconds
Started May 12 04:11:44 PM PDT 24
Finished May 12 04:11:48 PM PDT 24
Peak memory 202172 kb
Host smart-ea4ae6ed-f584-4331-ac4c-e60d288ac625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248721452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4248721452
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.229144492
Short name T778
Test name
Test status
Simulation time 363193017772 ps
CPU time 90.84 seconds
Started May 12 04:11:54 PM PDT 24
Finished May 12 04:13:25 PM PDT 24
Peak memory 202280 kb
Host smart-baf22c70-b6ef-4638-b1ba-bfbaee2a74ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229144492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
229144492
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3802294848
Short name T692
Test name
Test status
Simulation time 45690031611 ps
CPU time 204.7 seconds
Started May 12 04:11:51 PM PDT 24
Finished May 12 04:15:16 PM PDT 24
Peak memory 210924 kb
Host smart-a4419c40-03eb-453b-b6d4-9beeed7868cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802294848 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3802294848
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1331179177
Short name T594
Test name
Test status
Simulation time 489676147 ps
CPU time 0.77 seconds
Started May 12 04:12:00 PM PDT 24
Finished May 12 04:12:01 PM PDT 24
Peak memory 202040 kb
Host smart-5ba3cb20-7b4c-4929-a265-b456a3c691d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331179177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1331179177
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3107888371
Short name T776
Test name
Test status
Simulation time 169132820294 ps
CPU time 64.45 seconds
Started May 12 04:11:59 PM PDT 24
Finished May 12 04:13:04 PM PDT 24
Peak memory 202332 kb
Host smart-e207c953-ddee-410c-bcb9-ee6f5fbe5079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107888371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3107888371
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1825013459
Short name T186
Test name
Test status
Simulation time 325491655690 ps
CPU time 206.97 seconds
Started May 12 04:11:58 PM PDT 24
Finished May 12 04:15:25 PM PDT 24
Peak memory 202316 kb
Host smart-6a784119-9744-49dc-9f06-19125e20015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825013459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1825013459
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1408799618
Short name T577
Test name
Test status
Simulation time 492131133081 ps
CPU time 294.71 seconds
Started May 12 04:11:57 PM PDT 24
Finished May 12 04:16:52 PM PDT 24
Peak memory 202352 kb
Host smart-14c4c96b-e9bb-4969-8c10-33e1a63ada91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408799618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1408799618
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3912813396
Short name T718
Test name
Test status
Simulation time 486048711440 ps
CPU time 296.01 seconds
Started May 12 04:11:56 PM PDT 24
Finished May 12 04:16:53 PM PDT 24
Peak memory 202332 kb
Host smart-4c7131c2-4442-4240-ab1f-cfcfae764eb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912813396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3912813396
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1690063123
Short name T615
Test name
Test status
Simulation time 329493083811 ps
CPU time 406.27 seconds
Started May 12 04:11:53 PM PDT 24
Finished May 12 04:18:40 PM PDT 24
Peak memory 202264 kb
Host smart-ef0e1d05-33b8-4bf3-a657-c1db50a9c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690063123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1690063123
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3930142185
Short name T462
Test name
Test status
Simulation time 484586247481 ps
CPU time 600.93 seconds
Started May 12 04:11:57 PM PDT 24
Finished May 12 04:21:58 PM PDT 24
Peak memory 202264 kb
Host smart-258e4f99-7ad3-482e-9681-cd97a94de558
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930142185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3930142185
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2342172683
Short name T250
Test name
Test status
Simulation time 353108906809 ps
CPU time 364.39 seconds
Started May 12 04:11:56 PM PDT 24
Finished May 12 04:18:01 PM PDT 24
Peak memory 202300 kb
Host smart-0d39ff73-1ca7-4b7a-97cf-8b9041e6c905
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342172683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2342172683
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.294705530
Short name T745
Test name
Test status
Simulation time 608945487232 ps
CPU time 728.96 seconds
Started May 12 04:11:56 PM PDT 24
Finished May 12 04:24:06 PM PDT 24
Peak memory 202304 kb
Host smart-524626bb-3cc9-4537-88b6-094956449719
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294705530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.294705530
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.4264327952
Short name T333
Test name
Test status
Simulation time 90110142792 ps
CPU time 339.83 seconds
Started May 12 04:11:59 PM PDT 24
Finished May 12 04:17:39 PM PDT 24
Peak memory 202688 kb
Host smart-d5b47646-264a-435c-bd4a-524ba9512861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264327952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4264327952
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2625068154
Short name T773
Test name
Test status
Simulation time 41148551015 ps
CPU time 49.43 seconds
Started May 12 04:12:01 PM PDT 24
Finished May 12 04:12:50 PM PDT 24
Peak memory 202176 kb
Host smart-271257c2-be07-4e54-a572-579f11379323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625068154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2625068154
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1499132928
Short name T752
Test name
Test status
Simulation time 3461799902 ps
CPU time 2.95 seconds
Started May 12 04:12:00 PM PDT 24
Finished May 12 04:12:03 PM PDT 24
Peak memory 202084 kb
Host smart-bf1e41d9-990b-4080-89bc-bf40739c61e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499132928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1499132928
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4123551250
Short name T6
Test name
Test status
Simulation time 5801613998 ps
CPU time 13.42 seconds
Started May 12 04:11:52 PM PDT 24
Finished May 12 04:12:06 PM PDT 24
Peak memory 202168 kb
Host smart-875d0e90-a4dd-47e6-a5e5-063043facfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123551250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4123551250
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.141988521
Short name T609
Test name
Test status
Simulation time 126257937460 ps
CPU time 574.82 seconds
Started May 12 04:12:00 PM PDT 24
Finished May 12 04:21:35 PM PDT 24
Peak memory 202688 kb
Host smart-7e590890-9edf-45fe-8de6-cded8d106d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141988521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
141988521
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3007413410
Short name T24
Test name
Test status
Simulation time 72515463878 ps
CPU time 42.29 seconds
Started May 12 04:11:59 PM PDT 24
Finished May 12 04:12:42 PM PDT 24
Peak memory 212492 kb
Host smart-616baa66-d34e-4bd4-85a7-6184ee0de9d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007413410 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3007413410
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2722164055
Short name T473
Test name
Test status
Simulation time 508113730 ps
CPU time 0.8 seconds
Started May 12 04:12:12 PM PDT 24
Finished May 12 04:12:14 PM PDT 24
Peak memory 202044 kb
Host smart-c4971b22-68e3-41d3-8e7a-b9764a0e0984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722164055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2722164055
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.103924907
Short name T214
Test name
Test status
Simulation time 357853027871 ps
CPU time 429.37 seconds
Started May 12 04:12:07 PM PDT 24
Finished May 12 04:19:17 PM PDT 24
Peak memory 202316 kb
Host smart-4f77c611-abf4-40e7-82fd-6ac2812054a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103924907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.103924907
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1468746943
Short name T556
Test name
Test status
Simulation time 168623660889 ps
CPU time 396.63 seconds
Started May 12 04:12:12 PM PDT 24
Finished May 12 04:18:50 PM PDT 24
Peak memory 201676 kb
Host smart-ff4e305c-3e84-446f-8679-1b0ce633ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468746943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1468746943
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3352561408
Short name T440
Test name
Test status
Simulation time 330583314010 ps
CPU time 703.14 seconds
Started May 12 04:12:03 PM PDT 24
Finished May 12 04:23:46 PM PDT 24
Peak memory 202296 kb
Host smart-91a1d12b-6508-4a21-98ed-3a0a05b81ffe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352561408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3352561408
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2729733133
Short name T402
Test name
Test status
Simulation time 486626028907 ps
CPU time 1157.52 seconds
Started May 12 04:12:02 PM PDT 24
Finished May 12 04:31:20 PM PDT 24
Peak memory 202412 kb
Host smart-2ca6eab8-e455-4e9d-ae46-1e39ad3b65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729733133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2729733133
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4155411146
Short name T451
Test name
Test status
Simulation time 165283816570 ps
CPU time 34.53 seconds
Started May 12 04:12:04 PM PDT 24
Finished May 12 04:12:38 PM PDT 24
Peak memory 202284 kb
Host smart-1b332f37-1b81-4165-80f9-ef8eb1a2b573
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155411146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4155411146
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1255465089
Short name T765
Test name
Test status
Simulation time 197030055824 ps
CPU time 249.4 seconds
Started May 12 04:12:07 PM PDT 24
Finished May 12 04:16:16 PM PDT 24
Peak memory 202392 kb
Host smart-a8189c34-be41-44dc-b584-33e3039eff62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255465089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1255465089
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1463610622
Short name T446
Test name
Test status
Simulation time 402198789883 ps
CPU time 857.51 seconds
Started May 12 04:12:09 PM PDT 24
Finished May 12 04:26:27 PM PDT 24
Peak memory 202360 kb
Host smart-14993cfd-4ead-4141-bac1-31658aa19142
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463610622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1463610622
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2762799156
Short name T544
Test name
Test status
Simulation time 34814838723 ps
CPU time 21.66 seconds
Started May 12 04:12:08 PM PDT 24
Finished May 12 04:12:30 PM PDT 24
Peak memory 202144 kb
Host smart-04d330e7-0e5b-4bdd-a7ec-67be89152435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762799156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2762799156
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1404367006
Short name T757
Test name
Test status
Simulation time 5202716551 ps
CPU time 11.83 seconds
Started May 12 04:12:12 PM PDT 24
Finished May 12 04:12:25 PM PDT 24
Peak memory 201464 kb
Host smart-da4a6c70-0575-42ea-8341-a8aa6d669ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404367006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1404367006
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2683308249
Short name T608
Test name
Test status
Simulation time 6023970355 ps
CPU time 15.47 seconds
Started May 12 04:12:08 PM PDT 24
Finished May 12 04:12:24 PM PDT 24
Peak memory 202112 kb
Host smart-4927c13a-f52c-406f-b4ff-524f053c097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683308249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2683308249
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2695029595
Short name T503
Test name
Test status
Simulation time 310458420066 ps
CPU time 591.94 seconds
Started May 12 04:12:11 PM PDT 24
Finished May 12 04:22:03 PM PDT 24
Peak memory 210852 kb
Host smart-57f8a063-e81d-4d5b-8ff5-f13129b4ff6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695029595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2695029595
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.4074453317
Short name T743
Test name
Test status
Simulation time 137291723836 ps
CPU time 424.94 seconds
Started May 12 04:12:12 PM PDT 24
Finished May 12 04:19:18 PM PDT 24
Peak memory 218188 kb
Host smart-65aa8ad6-8b67-40dc-9347-7ccb5044f443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074453317 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.4074453317
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2941391698
Short name T401
Test name
Test status
Simulation time 430402116 ps
CPU time 0.92 seconds
Started May 12 04:12:24 PM PDT 24
Finished May 12 04:12:25 PM PDT 24
Peak memory 202024 kb
Host smart-26ae5276-551d-4adc-b4c3-5a9eb6b0ae89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941391698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2941391698
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1668355214
Short name T164
Test name
Test status
Simulation time 525736847395 ps
CPU time 146.19 seconds
Started May 12 04:12:18 PM PDT 24
Finished May 12 04:14:44 PM PDT 24
Peak memory 202336 kb
Host smart-9ef3291e-1637-4d0f-b09a-f5f9a12628ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668355214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1668355214
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.315677629
Short name T110
Test name
Test status
Simulation time 166155678955 ps
CPU time 286.01 seconds
Started May 12 04:12:16 PM PDT 24
Finished May 12 04:17:03 PM PDT 24
Peak memory 202348 kb
Host smart-9a763dee-7512-4184-93d1-80be482baf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315677629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.315677629
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.523202963
Short name T368
Test name
Test status
Simulation time 328082041427 ps
CPU time 738.29 seconds
Started May 12 04:12:16 PM PDT 24
Finished May 12 04:24:34 PM PDT 24
Peak memory 202380 kb
Host smart-17dd56c4-0efe-485d-9167-ad92bd47c6e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=523202963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.523202963
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2067964262
Short name T537
Test name
Test status
Simulation time 333547211876 ps
CPU time 186.73 seconds
Started May 12 04:12:16 PM PDT 24
Finished May 12 04:15:23 PM PDT 24
Peak memory 202220 kb
Host smart-eecc0205-eb44-4c13-b17c-2598ab9202f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067964262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2067964262
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2352898578
Short name T559
Test name
Test status
Simulation time 167966546003 ps
CPU time 110.76 seconds
Started May 12 04:12:18 PM PDT 24
Finished May 12 04:14:09 PM PDT 24
Peak memory 202492 kb
Host smart-ba31ab42-8a6a-4b15-ac34-735498d2d60a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352898578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2352898578
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2573894894
Short name T218
Test name
Test status
Simulation time 537055150907 ps
CPU time 631.09 seconds
Started May 12 04:12:18 PM PDT 24
Finished May 12 04:22:50 PM PDT 24
Peak memory 202508 kb
Host smart-9c9bf3c1-6360-4e17-be58-bc1d353c9dde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573894894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2573894894
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2865649110
Short name T591
Test name
Test status
Simulation time 410622139213 ps
CPU time 487.29 seconds
Started May 12 04:12:20 PM PDT 24
Finished May 12 04:20:27 PM PDT 24
Peak memory 202312 kb
Host smart-bb629e42-b684-45ae-a979-22d7f96acb3e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865649110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2865649110
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2761131609
Short name T481
Test name
Test status
Simulation time 87056470939 ps
CPU time 405.88 seconds
Started May 12 04:12:22 PM PDT 24
Finished May 12 04:19:08 PM PDT 24
Peak memory 202656 kb
Host smart-0ecfa281-bdcc-4d8f-991e-2b17b95c7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761131609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2761131609
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1606751672
Short name T580
Test name
Test status
Simulation time 34371121014 ps
CPU time 83.53 seconds
Started May 12 04:12:25 PM PDT 24
Finished May 12 04:13:48 PM PDT 24
Peak memory 202088 kb
Host smart-2c0e814e-b72b-4eab-b6af-33b0d4ef3367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606751672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1606751672
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3841260957
Short name T29
Test name
Test status
Simulation time 5554469467 ps
CPU time 2.32 seconds
Started May 12 04:12:22 PM PDT 24
Finished May 12 04:12:25 PM PDT 24
Peak memory 202124 kb
Host smart-459aa559-3df6-483b-bac4-aaa0e4dba88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841260957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3841260957
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.842290674
Short name T496
Test name
Test status
Simulation time 6054654009 ps
CPU time 4.49 seconds
Started May 12 04:12:14 PM PDT 24
Finished May 12 04:12:18 PM PDT 24
Peak memory 202120 kb
Host smart-97e1244a-6ac9-463a-9162-661308e310d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842290674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.842290674
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1728425316
Short name T32
Test name
Test status
Simulation time 401044847156 ps
CPU time 260.84 seconds
Started May 12 04:12:25 PM PDT 24
Finished May 12 04:16:46 PM PDT 24
Peak memory 202280 kb
Host smart-edc53a9e-3c4e-47d3-9cb6-e426090d21cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728425316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1728425316
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2774480194
Short name T263
Test name
Test status
Simulation time 105923362474 ps
CPU time 221.04 seconds
Started May 12 04:12:23 PM PDT 24
Finished May 12 04:16:04 PM PDT 24
Peak memory 211248 kb
Host smart-9a55af80-bdb5-4fd2-b2a7-381523bdfd13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774480194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2774480194
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3151886740
Short name T596
Test name
Test status
Simulation time 373143609 ps
CPU time 1.54 seconds
Started May 12 04:12:41 PM PDT 24
Finished May 12 04:12:43 PM PDT 24
Peak memory 201996 kb
Host smart-7672a6d0-03e4-41cd-ab0b-23f0ac24528e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151886740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3151886740
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1038615669
Short name T221
Test name
Test status
Simulation time 348165673121 ps
CPU time 224.21 seconds
Started May 12 04:12:32 PM PDT 24
Finished May 12 04:16:17 PM PDT 24
Peak memory 202324 kb
Host smart-9c4b47c1-74e2-42a2-9a80-eaf8c05e6abd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038615669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1038615669
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.510524303
Short name T438
Test name
Test status
Simulation time 166836158779 ps
CPU time 192.79 seconds
Started May 12 04:12:24 PM PDT 24
Finished May 12 04:15:38 PM PDT 24
Peak memory 202416 kb
Host smart-c5f2f8fd-eabb-48ac-b204-dd2aeef59c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510524303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.510524303
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.158309959
Short name T351
Test name
Test status
Simulation time 168366136186 ps
CPU time 107.99 seconds
Started May 12 04:12:28 PM PDT 24
Finished May 12 04:14:17 PM PDT 24
Peak memory 202288 kb
Host smart-1a7b85aa-fea9-46aa-8c26-0f4cafd20ac6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=158309959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.158309959
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1452109945
Short name T442
Test name
Test status
Simulation time 331132670661 ps
CPU time 760.95 seconds
Started May 12 04:12:25 PM PDT 24
Finished May 12 04:25:06 PM PDT 24
Peak memory 202340 kb
Host smart-3a5673d1-e8a0-44ad-a305-896abc02ef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452109945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1452109945
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2421230534
Short name T398
Test name
Test status
Simulation time 327636909785 ps
CPU time 151.38 seconds
Started May 12 04:12:24 PM PDT 24
Finished May 12 04:14:56 PM PDT 24
Peak memory 202304 kb
Host smart-b4b588f5-9916-44f0-bc4e-301c68955aa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421230534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2421230534
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.397495479
Short name T112
Test name
Test status
Simulation time 469808835141 ps
CPU time 260.46 seconds
Started May 12 04:12:32 PM PDT 24
Finished May 12 04:16:53 PM PDT 24
Peak memory 202352 kb
Host smart-a640386a-d28d-475a-ab29-32b05d03cedd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397495479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.397495479
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1071983788
Short name T390
Test name
Test status
Simulation time 186340011788 ps
CPU time 139.69 seconds
Started May 12 04:12:32 PM PDT 24
Finished May 12 04:14:53 PM PDT 24
Peak memory 202336 kb
Host smart-e5e53d0e-3ea3-46e7-b3c1-8b366d0d5688
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071983788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1071983788
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3213413346
Short name T604
Test name
Test status
Simulation time 124736956855 ps
CPU time 452.16 seconds
Started May 12 04:12:36 PM PDT 24
Finished May 12 04:20:09 PM PDT 24
Peak memory 202672 kb
Host smart-50c95ac1-53f2-4ded-ae2e-9aef89840d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213413346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3213413346
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1594230165
Short name T346
Test name
Test status
Simulation time 37121936928 ps
CPU time 5.9 seconds
Started May 12 04:12:37 PM PDT 24
Finished May 12 04:12:43 PM PDT 24
Peak memory 202124 kb
Host smart-9d673c36-9898-4d7f-a963-2dc40d04581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594230165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1594230165
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2280135975
Short name T523
Test name
Test status
Simulation time 4136088891 ps
CPU time 6.07 seconds
Started May 12 04:12:36 PM PDT 24
Finished May 12 04:12:43 PM PDT 24
Peak memory 202160 kb
Host smart-e76cd2b2-9f4d-466c-810b-f765ab3eddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280135975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2280135975
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3963123687
Short name T749
Test name
Test status
Simulation time 5997375453 ps
CPU time 2.53 seconds
Started May 12 04:12:26 PM PDT 24
Finished May 12 04:12:28 PM PDT 24
Peak memory 202144 kb
Host smart-e28be431-6ba5-4662-959e-d20cae416168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963123687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3963123687
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1426313761
Short name T144
Test name
Test status
Simulation time 614574275727 ps
CPU time 707.31 seconds
Started May 12 04:12:42 PM PDT 24
Finished May 12 04:24:29 PM PDT 24
Peak memory 202692 kb
Host smart-48d4dfe1-51d2-4098-8279-57a3983e8a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426313761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1426313761
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.19018288
Short name T60
Test name
Test status
Simulation time 369054243 ps
CPU time 1.52 seconds
Started May 12 04:12:49 PM PDT 24
Finished May 12 04:12:51 PM PDT 24
Peak memory 201972 kb
Host smart-31657dde-6f8f-4ab6-8780-f0fb21b4d918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19018288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.19018288
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.429909011
Short name T176
Test name
Test status
Simulation time 162222370397 ps
CPU time 40.74 seconds
Started May 12 04:12:45 PM PDT 24
Finished May 12 04:13:26 PM PDT 24
Peak memory 202340 kb
Host smart-67e5c6e0-aede-40ea-b239-7d9e956ce4b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429909011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.429909011
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1227994562
Short name T178
Test name
Test status
Simulation time 161742293527 ps
CPU time 187 seconds
Started May 12 04:12:43 PM PDT 24
Finished May 12 04:15:50 PM PDT 24
Peak memory 202340 kb
Host smart-70832d78-0920-4973-ade6-bfff37f812a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227994562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1227994562
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2277530242
Short name T427
Test name
Test status
Simulation time 167625977471 ps
CPU time 387.83 seconds
Started May 12 04:12:39 PM PDT 24
Finished May 12 04:19:08 PM PDT 24
Peak memory 202408 kb
Host smart-062386cf-66e3-4bc8-bf8e-b06ea17743bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277530242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2277530242
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.33408829
Short name T581
Test name
Test status
Simulation time 330345213765 ps
CPU time 375.85 seconds
Started May 12 04:12:39 PM PDT 24
Finished May 12 04:18:55 PM PDT 24
Peak memory 202332 kb
Host smart-65c7151e-cff5-4e18-85d0-5c74094c7a39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=33408829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt
_fixed.33408829
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1303311461
Short name T558
Test name
Test status
Simulation time 155775639839 ps
CPU time 47.58 seconds
Started May 12 04:12:43 PM PDT 24
Finished May 12 04:13:31 PM PDT 24
Peak memory 202288 kb
Host smart-30efd0fc-61ab-4766-818a-940ff9e9c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303311461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1303311461
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1932381512
Short name T423
Test name
Test status
Simulation time 161230771895 ps
CPU time 186.77 seconds
Started May 12 04:12:43 PM PDT 24
Finished May 12 04:15:50 PM PDT 24
Peak memory 202224 kb
Host smart-733ca4e2-4ef1-4322-9122-eebadd47940c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932381512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1932381512
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3928504766
Short name T274
Test name
Test status
Simulation time 349200050527 ps
CPU time 789.79 seconds
Started May 12 04:12:42 PM PDT 24
Finished May 12 04:25:52 PM PDT 24
Peak memory 202396 kb
Host smart-794de339-9209-4760-9f21-1173d18bfb5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928504766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3928504766
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4207306775
Short name T543
Test name
Test status
Simulation time 400529069294 ps
CPU time 250.76 seconds
Started May 12 04:12:40 PM PDT 24
Finished May 12 04:16:51 PM PDT 24
Peak memory 202412 kb
Host smart-8420f3cf-1a34-49ba-8e49-8344f2e864fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207306775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4207306775
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3349216991
Short name T405
Test name
Test status
Simulation time 70978886574 ps
CPU time 342.57 seconds
Started May 12 04:12:46 PM PDT 24
Finished May 12 04:18:29 PM PDT 24
Peak memory 202848 kb
Host smart-8f83e68e-b492-4a06-928b-a4f01a64228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349216991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3349216991
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.438195885
Short name T511
Test name
Test status
Simulation time 27410910944 ps
CPU time 16.03 seconds
Started May 12 04:12:43 PM PDT 24
Finished May 12 04:13:00 PM PDT 24
Peak memory 202164 kb
Host smart-d3a56e07-516e-4596-b03f-efe1528c3fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438195885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.438195885
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2629531705
Short name T588
Test name
Test status
Simulation time 4957394357 ps
CPU time 1.95 seconds
Started May 12 04:12:43 PM PDT 24
Finished May 12 04:12:45 PM PDT 24
Peak memory 202056 kb
Host smart-8dfd8d3d-a01c-43fe-915a-da36e1646a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629531705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2629531705
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1137208798
Short name T642
Test name
Test status
Simulation time 5743309914 ps
CPU time 2.86 seconds
Started May 12 04:12:42 PM PDT 24
Finished May 12 04:12:45 PM PDT 24
Peak memory 202156 kb
Host smart-8a9fb08a-2f59-447e-8845-16c4f71d39c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137208798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1137208798
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3714111706
Short name T617
Test name
Test status
Simulation time 202731288465 ps
CPU time 725.36 seconds
Started May 12 04:12:48 PM PDT 24
Finished May 12 04:24:54 PM PDT 24
Peak memory 210952 kb
Host smart-86f66e82-5f4d-4fb9-b4e1-c817affc86f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714111706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3714111706
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1434769609
Short name T37
Test name
Test status
Simulation time 24004595717 ps
CPU time 53.08 seconds
Started May 12 04:12:47 PM PDT 24
Finished May 12 04:13:40 PM PDT 24
Peak memory 210704 kb
Host smart-51bdce26-e3f2-4e44-8d6d-5deacce7f646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434769609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1434769609
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3432697835
Short name T629
Test name
Test status
Simulation time 343101410 ps
CPU time 1.45 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:09:14 PM PDT 24
Peak memory 202020 kb
Host smart-cfd9833b-8718-4543-ae27-bc5bcf0e8ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432697835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3432697835
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1536831939
Short name T236
Test name
Test status
Simulation time 486858338689 ps
CPU time 714.17 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:21:04 PM PDT 24
Peak memory 202412 kb
Host smart-d8a33724-22db-4cf5-a4d8-89b4d4bee367
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536831939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1536831939
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2250423935
Short name T790
Test name
Test status
Simulation time 198426070380 ps
CPU time 60.07 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:10:18 PM PDT 24
Peak memory 202284 kb
Host smart-9407e3b2-3f71-41db-a91e-418e0e47d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250423935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2250423935
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2302599828
Short name T408
Test name
Test status
Simulation time 163557598199 ps
CPU time 33.87 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:09:45 PM PDT 24
Peak memory 202332 kb
Host smart-76073b98-e5d8-492d-930e-5f6b473bf114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302599828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2302599828
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1820691000
Short name T553
Test name
Test status
Simulation time 163126358603 ps
CPU time 82.82 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:10:35 PM PDT 24
Peak memory 202500 kb
Host smart-61daaea6-90a9-41ed-987e-8b5c7c8cfe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820691000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1820691000
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3337519971
Short name T795
Test name
Test status
Simulation time 487508374750 ps
CPU time 275.76 seconds
Started May 12 04:09:09 PM PDT 24
Finished May 12 04:13:46 PM PDT 24
Peak memory 202360 kb
Host smart-b6be08d5-cffd-460f-acbe-c8168845e51a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337519971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3337519971
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1911946573
Short name T293
Test name
Test status
Simulation time 369463700387 ps
CPU time 67.22 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:10:18 PM PDT 24
Peak memory 202320 kb
Host smart-dd6eb6a1-06ea-4a5d-b6d4-7240e9550971
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911946573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1911946573
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2969125304
Short name T484
Test name
Test status
Simulation time 611010594190 ps
CPU time 354.04 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:15:06 PM PDT 24
Peak memory 202280 kb
Host smart-989c1200-7029-42fd-854f-28f7a988600b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969125304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2969125304
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1634447860
Short name T491
Test name
Test status
Simulation time 128874709774 ps
CPU time 450.5 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:16:42 PM PDT 24
Peak memory 202680 kb
Host smart-1000bc7e-5ed7-40a5-b11e-dbc5d3e55f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634447860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1634447860
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2761272686
Short name T672
Test name
Test status
Simulation time 30835038965 ps
CPU time 18.7 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:31 PM PDT 24
Peak memory 202168 kb
Host smart-54047f91-2671-4817-b194-05ae7fb9a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761272686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2761272686
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1142877595
Short name T734
Test name
Test status
Simulation time 5326197883 ps
CPU time 14.2 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:26 PM PDT 24
Peak memory 202072 kb
Host smart-5955ca6b-8b50-437d-9f03-382802b84222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142877595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1142877595
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2899819588
Short name T56
Test name
Test status
Simulation time 8519024051 ps
CPU time 3.83 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:09:16 PM PDT 24
Peak memory 218872 kb
Host smart-c1baad09-ee89-4cbd-a594-9047dff5c0de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899819588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2899819588
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3514117909
Short name T9
Test name
Test status
Simulation time 5753474098 ps
CPU time 13.97 seconds
Started May 12 04:09:10 PM PDT 24
Finished May 12 04:09:26 PM PDT 24
Peak memory 202160 kb
Host smart-72074e5e-2063-4fb5-ac6d-b17f24d172f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514117909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3514117909
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.96023082
Short name T244
Test name
Test status
Simulation time 191792140955 ps
CPU time 80.24 seconds
Started May 12 04:09:11 PM PDT 24
Finished May 12 04:10:33 PM PDT 24
Peak memory 202308 kb
Host smart-24e15dc0-1478-4249-9105-debb5a5d8041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96023082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.96023082
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.993725978
Short name T687
Test name
Test status
Simulation time 319068429 ps
CPU time 0.81 seconds
Started May 12 04:12:57 PM PDT 24
Finished May 12 04:12:58 PM PDT 24
Peak memory 202020 kb
Host smart-447ecf27-e501-41dd-9aa9-a78da6582ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993725978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.993725978
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3052739246
Short name T163
Test name
Test status
Simulation time 331473258712 ps
CPU time 189.5 seconds
Started May 12 04:12:51 PM PDT 24
Finished May 12 04:16:01 PM PDT 24
Peak memory 202264 kb
Host smart-d6d64a48-158a-4e8a-ae00-4d8c4fe90747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052739246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3052739246
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2995927721
Short name T740
Test name
Test status
Simulation time 162833972459 ps
CPU time 92.42 seconds
Started May 12 04:12:50 PM PDT 24
Finished May 12 04:14:23 PM PDT 24
Peak memory 202344 kb
Host smart-4310d49a-fc30-4ae5-a760-a9d603e4a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995927721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2995927721
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3572070284
Short name T602
Test name
Test status
Simulation time 166588786320 ps
CPU time 93.84 seconds
Started May 12 04:12:52 PM PDT 24
Finished May 12 04:14:26 PM PDT 24
Peak memory 202340 kb
Host smart-ffc2b7cb-5a10-4e13-8831-23b5d0f19310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572070284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3572070284
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2558625857
Short name T233
Test name
Test status
Simulation time 488883373430 ps
CPU time 1106.48 seconds
Started May 12 04:12:50 PM PDT 24
Finished May 12 04:31:17 PM PDT 24
Peak memory 202376 kb
Host smart-7bbc44f3-a721-4698-8454-476c26f7dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558625857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2558625857
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1868432186
Short name T387
Test name
Test status
Simulation time 164962474158 ps
CPU time 96.93 seconds
Started May 12 04:12:49 PM PDT 24
Finished May 12 04:14:27 PM PDT 24
Peak memory 202352 kb
Host smart-7d87ffb3-a632-4194-9bd0-af0c83b66953
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868432186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1868432186
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1003696555
Short name T753
Test name
Test status
Simulation time 206550281655 ps
CPU time 459.32 seconds
Started May 12 04:12:54 PM PDT 24
Finished May 12 04:20:34 PM PDT 24
Peak memory 202376 kb
Host smart-f8dcbae0-c4c4-4196-8ced-4492928003f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003696555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1003696555
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2816311824
Short name T682
Test name
Test status
Simulation time 590290857059 ps
CPU time 315.9 seconds
Started May 12 04:12:54 PM PDT 24
Finished May 12 04:18:10 PM PDT 24
Peak memory 202372 kb
Host smart-fd2ffc82-24d1-460a-bfaf-2ca426723be6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816311824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2816311824
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2846171984
Short name T316
Test name
Test status
Simulation time 106222230186 ps
CPU time 565.89 seconds
Started May 12 04:12:58 PM PDT 24
Finished May 12 04:22:24 PM PDT 24
Peak memory 202240 kb
Host smart-a1b07114-0ddf-4064-b31c-ac40c6b20028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846171984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2846171984
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3492408126
Short name T695
Test name
Test status
Simulation time 44440983912 ps
CPU time 106.46 seconds
Started May 12 04:12:58 PM PDT 24
Finished May 12 04:14:45 PM PDT 24
Peak memory 201676 kb
Host smart-72c763ae-461b-44c0-9af4-51ce83e48c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492408126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3492408126
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3931382442
Short name T584
Test name
Test status
Simulation time 3647309224 ps
CPU time 3.25 seconds
Started May 12 04:12:57 PM PDT 24
Finished May 12 04:13:00 PM PDT 24
Peak memory 202152 kb
Host smart-9b44bd5f-ba23-4e5f-bc4a-3d274a900c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931382442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3931382442
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3951444286
Short name T468
Test name
Test status
Simulation time 5586993332 ps
CPU time 4.11 seconds
Started May 12 04:12:50 PM PDT 24
Finished May 12 04:12:54 PM PDT 24
Peak memory 202156 kb
Host smart-d1fed487-0021-497b-a4f6-9c536ddc52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951444286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3951444286
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2868241005
Short name T667
Test name
Test status
Simulation time 165777623965 ps
CPU time 387.13 seconds
Started May 12 04:12:56 PM PDT 24
Finished May 12 04:19:23 PM PDT 24
Peak memory 202324 kb
Host smart-777ded96-54ad-477a-95f0-27aeb11124be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868241005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2868241005
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1371781848
Short name T403
Test name
Test status
Simulation time 492203267 ps
CPU time 1.17 seconds
Started May 12 04:13:11 PM PDT 24
Finished May 12 04:13:13 PM PDT 24
Peak memory 202008 kb
Host smart-8de6b83b-3a70-4600-b7ce-2eaa600ceaee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371781848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1371781848
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.91776474
Short name T188
Test name
Test status
Simulation time 156916141724 ps
CPU time 182.49 seconds
Started May 12 04:13:07 PM PDT 24
Finished May 12 04:16:10 PM PDT 24
Peak memory 202296 kb
Host smart-0a3f933c-f0bf-4848-a208-9ef2a4dd3082
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91776474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gatin
g.91776474
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.635611924
Short name T223
Test name
Test status
Simulation time 166360186983 ps
CPU time 82.08 seconds
Started May 12 04:13:06 PM PDT 24
Finished May 12 04:14:28 PM PDT 24
Peak memory 202320 kb
Host smart-dc053fc9-89c7-4e94-a701-4712e4189170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635611924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.635611924
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3706946310
Short name T174
Test name
Test status
Simulation time 511792111246 ps
CPU time 1174.15 seconds
Started May 12 04:13:00 PM PDT 24
Finished May 12 04:32:35 PM PDT 24
Peak memory 202396 kb
Host smart-27a61db4-c488-42cd-86a1-9ceed0ac881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706946310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3706946310
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3060492293
Short name T572
Test name
Test status
Simulation time 495341768711 ps
CPU time 309.2 seconds
Started May 12 04:13:00 PM PDT 24
Finished May 12 04:18:09 PM PDT 24
Peak memory 202332 kb
Host smart-477cbe57-85c5-4423-a8ef-09f0513efe3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060492293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3060492293
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3615162234
Short name T117
Test name
Test status
Simulation time 490641429703 ps
CPU time 308.48 seconds
Started May 12 04:12:59 PM PDT 24
Finished May 12 04:18:07 PM PDT 24
Peak memory 202304 kb
Host smart-4a2688b0-1394-4492-a9b5-a82f6ee07c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615162234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3615162234
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2431150014
Short name T649
Test name
Test status
Simulation time 323364321893 ps
CPU time 205.58 seconds
Started May 12 04:12:59 PM PDT 24
Finished May 12 04:16:25 PM PDT 24
Peak memory 202268 kb
Host smart-fde88ad3-06a2-4eae-9729-3d44cec1407b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431150014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2431150014
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2302113517
Short name T355
Test name
Test status
Simulation time 598281804941 ps
CPU time 331.89 seconds
Started May 12 04:13:06 PM PDT 24
Finished May 12 04:18:38 PM PDT 24
Peak memory 202308 kb
Host smart-c527c172-3d7c-4d97-bed3-fa393f208e68
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302113517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2302113517
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.248517705
Short name T327
Test name
Test status
Simulation time 65262264345 ps
CPU time 271.79 seconds
Started May 12 04:13:08 PM PDT 24
Finished May 12 04:17:40 PM PDT 24
Peak memory 202652 kb
Host smart-48eca691-cd04-48a0-b8ab-b129d2f18586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248517705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.248517705
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3565031317
Short name T167
Test name
Test status
Simulation time 21864351496 ps
CPU time 5.34 seconds
Started May 12 04:13:09 PM PDT 24
Finished May 12 04:13:14 PM PDT 24
Peak memory 202136 kb
Host smart-78bba078-59f2-4c1d-ad9b-5400125c5bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565031317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3565031317
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.612837744
Short name T763
Test name
Test status
Simulation time 3974027204 ps
CPU time 2.93 seconds
Started May 12 04:13:08 PM PDT 24
Finished May 12 04:13:11 PM PDT 24
Peak memory 202144 kb
Host smart-278c5895-a35f-48e6-9bd6-a69c04c6b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612837744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.612837744
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2937653715
Short name T510
Test name
Test status
Simulation time 6129153602 ps
CPU time 8.68 seconds
Started May 12 04:13:01 PM PDT 24
Finished May 12 04:13:09 PM PDT 24
Peak memory 202152 kb
Host smart-a254799d-0c1c-4510-8747-e51827b8f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937653715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2937653715
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2852959479
Short name T688
Test name
Test status
Simulation time 168499976938 ps
CPU time 414.59 seconds
Started May 12 04:13:10 PM PDT 24
Finished May 12 04:20:04 PM PDT 24
Peak memory 202316 kb
Host smart-bf08b51e-8039-474b-9aa9-3530361b3078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852959479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2852959479
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2079344215
Short name T709
Test name
Test status
Simulation time 25457258292 ps
CPU time 67.52 seconds
Started May 12 04:13:09 PM PDT 24
Finished May 12 04:14:17 PM PDT 24
Peak memory 211012 kb
Host smart-ae8eeb6d-2155-451e-ba44-961e1e37a754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079344215 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2079344215
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.164378409
Short name T637
Test name
Test status
Simulation time 325533245 ps
CPU time 1.08 seconds
Started May 12 04:13:20 PM PDT 24
Finished May 12 04:13:22 PM PDT 24
Peak memory 202048 kb
Host smart-3758d65d-6a67-4d0b-93a0-3c8dc35b4fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164378409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.164378409
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3772773794
Short name T189
Test name
Test status
Simulation time 174974564624 ps
CPU time 383.62 seconds
Started May 12 04:13:17 PM PDT 24
Finished May 12 04:19:41 PM PDT 24
Peak memory 202280 kb
Host smart-f1a2bbdc-2004-4404-9b46-afabfda8487b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772773794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3772773794
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4078034598
Short name T463
Test name
Test status
Simulation time 326475535173 ps
CPU time 212.78 seconds
Started May 12 04:13:15 PM PDT 24
Finished May 12 04:16:48 PM PDT 24
Peak memory 202284 kb
Host smart-6e14e43a-e068-4d1f-b8b8-e931769867ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078034598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4078034598
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4267098952
Short name T525
Test name
Test status
Simulation time 164918463948 ps
CPU time 180.73 seconds
Started May 12 04:13:19 PM PDT 24
Finished May 12 04:16:20 PM PDT 24
Peak memory 202308 kb
Host smart-09242a3e-0ea1-4c8b-8afb-c1c3d017e2d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267098952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4267098952
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2093034967
Short name T507
Test name
Test status
Simulation time 324956953281 ps
CPU time 710.53 seconds
Started May 12 04:13:10 PM PDT 24
Finished May 12 04:25:01 PM PDT 24
Peak memory 202388 kb
Host smart-218e9e18-68f2-42f2-940a-304a2b07ee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093034967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2093034967
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3717231314
Short name T665
Test name
Test status
Simulation time 490483025163 ps
CPU time 334.35 seconds
Started May 12 04:13:10 PM PDT 24
Finished May 12 04:18:45 PM PDT 24
Peak memory 202352 kb
Host smart-a6e0230b-91c7-43fc-8993-cf22cc8bf29d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717231314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3717231314
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1858572770
Short name T299
Test name
Test status
Simulation time 185957046143 ps
CPU time 465.57 seconds
Started May 12 04:13:12 PM PDT 24
Finished May 12 04:20:58 PM PDT 24
Peak memory 202348 kb
Host smart-35e9877b-34f9-4419-a3d0-82160db29c09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858572770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1858572770
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3815604765
Short name T478
Test name
Test status
Simulation time 605327096471 ps
CPU time 373.42 seconds
Started May 12 04:13:18 PM PDT 24
Finished May 12 04:19:31 PM PDT 24
Peak memory 202352 kb
Host smart-e73814a0-ebd4-48fa-bc88-d6d0d102539c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815604765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3815604765
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1955633385
Short name T43
Test name
Test status
Simulation time 94017475180 ps
CPU time 299.36 seconds
Started May 12 04:13:20 PM PDT 24
Finished May 12 04:18:19 PM PDT 24
Peak memory 202664 kb
Host smart-cf2cf5b9-434f-4631-b487-34cbd6b21381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955633385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1955633385
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1985229874
Short name T436
Test name
Test status
Simulation time 28403992654 ps
CPU time 7.77 seconds
Started May 12 04:13:17 PM PDT 24
Finished May 12 04:13:25 PM PDT 24
Peak memory 202152 kb
Host smart-1dfc8467-ba54-45e5-a2e4-85a9fed70ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985229874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1985229874
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4101297431
Short name T724
Test name
Test status
Simulation time 2969430691 ps
CPU time 4.45 seconds
Started May 12 04:13:19 PM PDT 24
Finished May 12 04:13:24 PM PDT 24
Peak memory 202144 kb
Host smart-296b5796-4e76-410f-85f1-d24a86df4743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101297431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4101297431
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.812301841
Short name T517
Test name
Test status
Simulation time 6052073433 ps
CPU time 14.61 seconds
Started May 12 04:13:12 PM PDT 24
Finished May 12 04:13:27 PM PDT 24
Peak memory 202152 kb
Host smart-57ffa766-b4cc-4edd-987c-53219403b7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812301841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.812301841
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1324996837
Short name T498
Test name
Test status
Simulation time 153407695177 ps
CPU time 501.45 seconds
Started May 12 04:13:21 PM PDT 24
Finished May 12 04:21:43 PM PDT 24
Peak memory 202768 kb
Host smart-dcb1e26a-7d50-4f49-8839-585a1fe7c196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324996837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1324996837
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4077637033
Short name T168
Test name
Test status
Simulation time 103881383105 ps
CPU time 311.05 seconds
Started May 12 04:13:21 PM PDT 24
Finished May 12 04:18:32 PM PDT 24
Peak memory 210976 kb
Host smart-3bbf5bf4-c71a-47d9-bb01-2d88313705ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077637033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4077637033
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2938407179
Short name T566
Test name
Test status
Simulation time 480085216 ps
CPU time 1.74 seconds
Started May 12 04:13:37 PM PDT 24
Finished May 12 04:13:40 PM PDT 24
Peak memory 201960 kb
Host smart-0d8fd1ae-21b5-47c0-a052-e951e8cad6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938407179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2938407179
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4073425140
Short name T677
Test name
Test status
Simulation time 525147825114 ps
CPU time 297.78 seconds
Started May 12 04:13:31 PM PDT 24
Finished May 12 04:18:29 PM PDT 24
Peak memory 202328 kb
Host smart-05279447-166a-41d8-9951-cad55bb2588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073425140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4073425140
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3338704156
Short name T172
Test name
Test status
Simulation time 164950556366 ps
CPU time 411.53 seconds
Started May 12 04:13:23 PM PDT 24
Finished May 12 04:20:15 PM PDT 24
Peak memory 202284 kb
Host smart-d226e44e-d3a8-49a1-ab11-578277df1c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338704156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3338704156
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1151333624
Short name T73
Test name
Test status
Simulation time 328286786255 ps
CPU time 767.12 seconds
Started May 12 04:13:27 PM PDT 24
Finished May 12 04:26:15 PM PDT 24
Peak memory 202300 kb
Host smart-a7b639b0-69d2-4bba-9aac-4639516b274b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151333624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1151333624
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3148953386
Short name T783
Test name
Test status
Simulation time 162091085234 ps
CPU time 165.84 seconds
Started May 12 04:13:19 PM PDT 24
Finished May 12 04:16:05 PM PDT 24
Peak memory 202396 kb
Host smart-870dbd54-37c3-4f32-bd34-678afa7c90a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148953386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3148953386
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3306851772
Short name T697
Test name
Test status
Simulation time 163782180401 ps
CPU time 309.27 seconds
Started May 12 04:13:22 PM PDT 24
Finished May 12 04:18:31 PM PDT 24
Peak memory 202288 kb
Host smart-db1bcf45-56f6-4c1d-9346-d33ec4b44671
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306851772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3306851772
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2984255148
Short name T301
Test name
Test status
Simulation time 200010840287 ps
CPU time 505.03 seconds
Started May 12 04:13:27 PM PDT 24
Finished May 12 04:21:52 PM PDT 24
Peak memory 202396 kb
Host smart-db2221b8-6220-4b63-af14-cf3c32e45012
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984255148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2984255148
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4091022171
Short name T443
Test name
Test status
Simulation time 607498802070 ps
CPU time 1484.4 seconds
Started May 12 04:13:31 PM PDT 24
Finished May 12 04:38:16 PM PDT 24
Peak memory 202340 kb
Host smart-1b5893dd-cd7a-44a7-949d-494a36f59fe7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091022171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4091022171
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3328454743
Short name T434
Test name
Test status
Simulation time 141123306543 ps
CPU time 551.61 seconds
Started May 12 04:13:31 PM PDT 24
Finished May 12 04:22:43 PM PDT 24
Peak memory 202752 kb
Host smart-76f1c0a8-bc32-4f71-88b4-1d03626b6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328454743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3328454743
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2497778146
Short name T691
Test name
Test status
Simulation time 39877643070 ps
CPU time 68.98 seconds
Started May 12 04:13:30 PM PDT 24
Finished May 12 04:14:39 PM PDT 24
Peak memory 202112 kb
Host smart-d293071e-1e0c-4c9a-ba90-3f81164d3946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497778146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2497778146
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1190522922
Short name T362
Test name
Test status
Simulation time 3793568498 ps
CPU time 4.98 seconds
Started May 12 04:13:32 PM PDT 24
Finished May 12 04:13:37 PM PDT 24
Peak memory 202124 kb
Host smart-6bee607c-ebfb-466c-8c87-54d22551df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190522922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1190522922
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2554727826
Short name T791
Test name
Test status
Simulation time 5837819550 ps
CPU time 7.13 seconds
Started May 12 04:13:20 PM PDT 24
Finished May 12 04:13:27 PM PDT 24
Peak memory 202128 kb
Host smart-7f9a792a-5af8-4132-9cd7-24eca0f3fbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554727826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2554727826
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.165904811
Short name T175
Test name
Test status
Simulation time 361542723895 ps
CPU time 547.34 seconds
Started May 12 04:13:31 PM PDT 24
Finished May 12 04:22:39 PM PDT 24
Peak memory 202684 kb
Host smart-507dc4dc-6c0c-4f5a-a1c5-a5368044f1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165904811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
165904811
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1445128833
Short name T74
Test name
Test status
Simulation time 65353896886 ps
CPU time 143.75 seconds
Started May 12 04:13:33 PM PDT 24
Finished May 12 04:15:57 PM PDT 24
Peak memory 210620 kb
Host smart-f1dde29c-fb56-44aa-98a2-a999c332c2ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445128833 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1445128833
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.4082565388
Short name T664
Test name
Test status
Simulation time 354394567 ps
CPU time 1.37 seconds
Started May 12 04:13:43 PM PDT 24
Finished May 12 04:13:45 PM PDT 24
Peak memory 202024 kb
Host smart-0e8f77e2-3c5f-4ea3-a1e3-10dc2613596c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082565388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4082565388
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3085537130
Short name T663
Test name
Test status
Simulation time 165580261836 ps
CPU time 63.48 seconds
Started May 12 04:13:40 PM PDT 24
Finished May 12 04:14:44 PM PDT 24
Peak memory 202380 kb
Host smart-12064553-f72b-4b31-9d32-6c885367fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085537130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3085537130
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1165926353
Short name T151
Test name
Test status
Simulation time 500721304613 ps
CPU time 169.67 seconds
Started May 12 04:13:32 PM PDT 24
Finished May 12 04:16:23 PM PDT 24
Peak memory 202356 kb
Host smart-201317f5-8457-4940-a325-feb3e11feefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165926353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1165926353
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2992338717
Short name T415
Test name
Test status
Simulation time 481979316653 ps
CPU time 371.59 seconds
Started May 12 04:13:36 PM PDT 24
Finished May 12 04:19:48 PM PDT 24
Peak memory 202348 kb
Host smart-39aa606f-54bb-45c8-9bd2-97b414558c0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992338717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2992338717
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3807981233
Short name T679
Test name
Test status
Simulation time 489850130754 ps
CPU time 1015.93 seconds
Started May 12 04:13:37 PM PDT 24
Finished May 12 04:30:33 PM PDT 24
Peak memory 202224 kb
Host smart-2cd0bf61-ad69-4244-bdbc-a298c0848b97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807981233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3807981233
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1828409547
Short name T216
Test name
Test status
Simulation time 538231047053 ps
CPU time 625.04 seconds
Started May 12 04:13:35 PM PDT 24
Finished May 12 04:24:01 PM PDT 24
Peak memory 202332 kb
Host smart-7761a0aa-1a16-4a3d-9e58-78769d07a573
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828409547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1828409547
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.327316476
Short name T625
Test name
Test status
Simulation time 200980055855 ps
CPU time 81.22 seconds
Started May 12 04:13:40 PM PDT 24
Finished May 12 04:15:02 PM PDT 24
Peak memory 202288 kb
Host smart-81a82c79-5c58-4978-9ed0-676fb13c900e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327316476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.327316476
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3947515764
Short name T320
Test name
Test status
Simulation time 99543628106 ps
CPU time 385.92 seconds
Started May 12 04:13:41 PM PDT 24
Finished May 12 04:20:08 PM PDT 24
Peak memory 202632 kb
Host smart-f79dbccc-88fb-4db1-8416-437126aff266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947515764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3947515764
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2742363817
Short name T341
Test name
Test status
Simulation time 35221861980 ps
CPU time 39.78 seconds
Started May 12 04:13:39 PM PDT 24
Finished May 12 04:14:20 PM PDT 24
Peak memory 202096 kb
Host smart-83f5b703-a054-4f86-a3f4-5b5af59a2b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742363817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2742363817
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1768687992
Short name T370
Test name
Test status
Simulation time 3750530672 ps
CPU time 9.02 seconds
Started May 12 04:13:39 PM PDT 24
Finished May 12 04:13:48 PM PDT 24
Peak memory 202156 kb
Host smart-8c4c7cf0-2aed-4cc6-8db0-47327012fa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768687992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1768687992
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3697194697
Short name T774
Test name
Test status
Simulation time 5888377162 ps
CPU time 2.02 seconds
Started May 12 04:13:32 PM PDT 24
Finished May 12 04:13:34 PM PDT 24
Peak memory 202128 kb
Host smart-64686138-c9ae-4007-8ea4-13c752bbf621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697194697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3697194697
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2622179256
Short name T209
Test name
Test status
Simulation time 345841801386 ps
CPU time 416.16 seconds
Started May 12 04:13:42 PM PDT 24
Finished May 12 04:20:38 PM PDT 24
Peak memory 202316 kb
Host smart-d6fc7302-54ae-4229-8218-d78c168ba752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622179256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2622179256
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.330071293
Short name T295
Test name
Test status
Simulation time 105469392028 ps
CPU time 104.92 seconds
Started May 12 04:13:41 PM PDT 24
Finished May 12 04:15:27 PM PDT 24
Peak memory 211032 kb
Host smart-3a535edb-749b-43da-9710-3ff9a2423c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330071293 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.330071293
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3638856725
Short name T335
Test name
Test status
Simulation time 357978944 ps
CPU time 0.8 seconds
Started May 12 04:13:56 PM PDT 24
Finished May 12 04:13:57 PM PDT 24
Peak memory 201944 kb
Host smart-e3d9d326-dfb0-4947-803e-ee4790e55eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638856725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3638856725
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2186264279
Short name T226
Test name
Test status
Simulation time 356149643603 ps
CPU time 533.27 seconds
Started May 12 04:13:46 PM PDT 24
Finished May 12 04:22:40 PM PDT 24
Peak memory 202340 kb
Host smart-91a619b0-d3c2-46b1-a56d-77e5a67ed36a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186264279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2186264279
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.724576002
Short name T231
Test name
Test status
Simulation time 328631515128 ps
CPU time 201.4 seconds
Started May 12 04:13:42 PM PDT 24
Finished May 12 04:17:04 PM PDT 24
Peak memory 202332 kb
Host smart-b5ce0c10-bce7-4995-b3d5-7f492ec364a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724576002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.724576002
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3114822747
Short name T113
Test name
Test status
Simulation time 490920648292 ps
CPU time 86.02 seconds
Started May 12 04:13:44 PM PDT 24
Finished May 12 04:15:10 PM PDT 24
Peak memory 202312 kb
Host smart-29b970ef-f6d9-4a65-be28-9418e0b03c0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114822747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3114822747
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.100439376
Short name T549
Test name
Test status
Simulation time 333134216957 ps
CPU time 741.51 seconds
Started May 12 04:13:42 PM PDT 24
Finished May 12 04:26:04 PM PDT 24
Peak memory 202332 kb
Host smart-9a0b58b9-03ad-47f5-bc67-6009d7f61a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100439376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.100439376
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1860755636
Short name T524
Test name
Test status
Simulation time 164109592606 ps
CPU time 396.72 seconds
Started May 12 04:13:42 PM PDT 24
Finished May 12 04:20:19 PM PDT 24
Peak memory 202380 kb
Host smart-131655f6-2263-4152-8624-66dd6dee3f1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860755636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1860755636
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1150565053
Short name T196
Test name
Test status
Simulation time 552258032098 ps
CPU time 650.21 seconds
Started May 12 04:13:48 PM PDT 24
Finished May 12 04:24:38 PM PDT 24
Peak memory 202328 kb
Host smart-82331738-8374-4071-8805-059666e9beab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150565053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1150565053
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3101510533
Short name T417
Test name
Test status
Simulation time 596680195508 ps
CPU time 296.57 seconds
Started May 12 04:13:46 PM PDT 24
Finished May 12 04:18:43 PM PDT 24
Peak memory 202328 kb
Host smart-1aa86761-71d7-4a34-a643-4d0cff957ceb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101510533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3101510533
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3063314993
Short name T657
Test name
Test status
Simulation time 134770654417 ps
CPU time 489.13 seconds
Started May 12 04:13:49 PM PDT 24
Finished May 12 04:21:58 PM PDT 24
Peak memory 202680 kb
Host smart-f2db4b73-68d3-442e-bc5f-cca88f765e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063314993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3063314993
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3984073287
Short name T146
Test name
Test status
Simulation time 40196060088 ps
CPU time 92.34 seconds
Started May 12 04:13:48 PM PDT 24
Finished May 12 04:15:21 PM PDT 24
Peak memory 202116 kb
Host smart-194de47c-a059-42cb-844a-8bbab93e7ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984073287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3984073287
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.978573712
Short name T647
Test name
Test status
Simulation time 3035132016 ps
CPU time 2.34 seconds
Started May 12 04:13:44 PM PDT 24
Finished May 12 04:13:47 PM PDT 24
Peak memory 202140 kb
Host smart-b6686d1e-0775-4ca1-91b4-59956f6df4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978573712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.978573712
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2408717558
Short name T80
Test name
Test status
Simulation time 5647115295 ps
CPU time 12.59 seconds
Started May 12 04:13:45 PM PDT 24
Finished May 12 04:13:59 PM PDT 24
Peak memory 202152 kb
Host smart-21cebf2d-5fee-442a-8f0f-f1be35d5710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408717558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2408717558
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3021474816
Short name T755
Test name
Test status
Simulation time 151376631264 ps
CPU time 625.63 seconds
Started May 12 04:13:56 PM PDT 24
Finished May 12 04:24:22 PM PDT 24
Peak memory 219044 kb
Host smart-f6532650-d59b-478a-8924-154e75916c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021474816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3021474816
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.813251831
Short name T258
Test name
Test status
Simulation time 360898545254 ps
CPU time 246.61 seconds
Started May 12 04:13:53 PM PDT 24
Finished May 12 04:18:00 PM PDT 24
Peak memory 210880 kb
Host smart-472f856e-dedb-4ec7-b2aa-bf66369f506c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813251831 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.813251831
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4276209956
Short name T582
Test name
Test status
Simulation time 383111601 ps
CPU time 0.83 seconds
Started May 12 04:14:03 PM PDT 24
Finished May 12 04:14:04 PM PDT 24
Peak memory 201980 kb
Host smart-9ce49c99-ba96-4c01-924d-c85de903044c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276209956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4276209956
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2581991057
Short name T192
Test name
Test status
Simulation time 343973270821 ps
CPU time 199.69 seconds
Started May 12 04:13:55 PM PDT 24
Finished May 12 04:17:15 PM PDT 24
Peak memory 202368 kb
Host smart-c46e90d4-14e7-476e-b7ca-4429d9bb1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581991057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2581991057
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2731706185
Short name T458
Test name
Test status
Simulation time 495122874184 ps
CPU time 335.59 seconds
Started May 12 04:14:04 PM PDT 24
Finished May 12 04:19:40 PM PDT 24
Peak memory 202280 kb
Host smart-bb73c13a-de80-484a-b9c0-81f9aba07d04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731706185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2731706185
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.608456084
Short name T761
Test name
Test status
Simulation time 327956485333 ps
CPU time 357.86 seconds
Started May 12 04:13:53 PM PDT 24
Finished May 12 04:19:51 PM PDT 24
Peak memory 202264 kb
Host smart-7d130d3b-186b-48e8-a725-4a6cd4f5ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608456084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.608456084
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1803837357
Short name T431
Test name
Test status
Simulation time 492825705655 ps
CPU time 299.88 seconds
Started May 12 04:13:55 PM PDT 24
Finished May 12 04:18:56 PM PDT 24
Peak memory 202292 kb
Host smart-fb727eb6-88dd-465e-b37a-5b32ab9c3c5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803837357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1803837357
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3100704514
Short name T592
Test name
Test status
Simulation time 177473784818 ps
CPU time 114.2 seconds
Started May 12 04:13:56 PM PDT 24
Finished May 12 04:15:51 PM PDT 24
Peak memory 202356 kb
Host smart-69d20849-6daf-4975-965c-20b5b474c171
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100704514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3100704514
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1311342268
Short name T651
Test name
Test status
Simulation time 205104949506 ps
CPU time 72.17 seconds
Started May 12 04:14:02 PM PDT 24
Finished May 12 04:15:15 PM PDT 24
Peak memory 202308 kb
Host smart-666526be-b3d1-422d-a4e7-57a9cea896e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311342268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1311342268
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2083210669
Short name T788
Test name
Test status
Simulation time 97746359551 ps
CPU time 413.24 seconds
Started May 12 04:14:02 PM PDT 24
Finished May 12 04:20:56 PM PDT 24
Peak memory 202668 kb
Host smart-6147b918-139a-431e-a3ad-1b10cc8ce77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083210669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2083210669
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3215788218
Short name T557
Test name
Test status
Simulation time 34683851948 ps
CPU time 75.25 seconds
Started May 12 04:14:03 PM PDT 24
Finished May 12 04:15:19 PM PDT 24
Peak memory 202128 kb
Host smart-396f1466-1d81-4840-9e80-6d549ab02fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215788218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3215788218
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3633650743
Short name T719
Test name
Test status
Simulation time 4441546474 ps
CPU time 11.13 seconds
Started May 12 04:14:02 PM PDT 24
Finished May 12 04:14:14 PM PDT 24
Peak memory 202140 kb
Host smart-7ad26ed8-0947-429b-96f7-c0bf91390fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633650743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3633650743
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3332484008
Short name T70
Test name
Test status
Simulation time 6016529870 ps
CPU time 13.26 seconds
Started May 12 04:13:56 PM PDT 24
Finished May 12 04:14:10 PM PDT 24
Peak memory 202156 kb
Host smart-56eb7b0a-2a09-4605-8061-6afbfd11abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332484008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3332484008
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.151791920
Short name T539
Test name
Test status
Simulation time 690129041775 ps
CPU time 369.14 seconds
Started May 12 04:14:04 PM PDT 24
Finished May 12 04:20:14 PM PDT 24
Peak memory 202296 kb
Host smart-437c57f5-adc8-43fa-b226-2ba4bc533def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151791920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
151791920
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3047201186
Short name T704
Test name
Test status
Simulation time 139626755991 ps
CPU time 93.91 seconds
Started May 12 04:14:10 PM PDT 24
Finished May 12 04:15:44 PM PDT 24
Peak memory 210680 kb
Host smart-6d2cd48c-b5cf-4833-9b2a-274a0800599f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047201186 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3047201186
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3422006424
Short name T570
Test name
Test status
Simulation time 364933792 ps
CPU time 1.46 seconds
Started May 12 04:14:13 PM PDT 24
Finished May 12 04:14:14 PM PDT 24
Peak memory 202136 kb
Host smart-28b534b1-ce9d-4252-8175-5630b25ac0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422006424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3422006424
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2157157127
Short name T613
Test name
Test status
Simulation time 344707541917 ps
CPU time 59.88 seconds
Started May 12 04:14:12 PM PDT 24
Finished May 12 04:15:12 PM PDT 24
Peak memory 202416 kb
Host smart-e1500f7c-6dd4-4817-beef-3c9f1b940ed4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157157127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2157157127
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.594255356
Short name T245
Test name
Test status
Simulation time 165480651526 ps
CPU time 413.44 seconds
Started May 12 04:14:06 PM PDT 24
Finished May 12 04:21:00 PM PDT 24
Peak memory 202280 kb
Host smart-229aeb8c-acaa-4cd3-a1b5-db5316ae61ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594255356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.594255356
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.941278239
Short name T343
Test name
Test status
Simulation time 162568675518 ps
CPU time 46.45 seconds
Started May 12 04:14:08 PM PDT 24
Finished May 12 04:14:55 PM PDT 24
Peak memory 202284 kb
Host smart-3b2b7921-07c1-4ad8-ad42-d62e37def287
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=941278239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.941278239
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.37542267
Short name T126
Test name
Test status
Simulation time 328011842316 ps
CPU time 190.59 seconds
Started May 12 04:14:06 PM PDT 24
Finished May 12 04:17:17 PM PDT 24
Peak memory 202380 kb
Host smart-9763cb8e-ad6b-44dd-a3d8-9c74d9872e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37542267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.37542267
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.815906542
Short name T536
Test name
Test status
Simulation time 501203548815 ps
CPU time 1167.71 seconds
Started May 12 04:14:03 PM PDT 24
Finished May 12 04:33:31 PM PDT 24
Peak memory 202308 kb
Host smart-8a446910-cd4b-4e5c-acf9-00527c44951a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=815906542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.815906542
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3801032634
Short name T219
Test name
Test status
Simulation time 361836614422 ps
CPU time 495.05 seconds
Started May 12 04:14:06 PM PDT 24
Finished May 12 04:22:22 PM PDT 24
Peak memory 202408 kb
Host smart-fe894d1d-78bf-4f4b-967a-0b9c43e0daea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801032634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3801032634
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1762955028
Short name T598
Test name
Test status
Simulation time 393635501601 ps
CPU time 961.16 seconds
Started May 12 04:14:08 PM PDT 24
Finished May 12 04:30:10 PM PDT 24
Peak memory 202320 kb
Host smart-01c5f107-5141-4a09-8ae5-c87a91b7929d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762955028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1762955028
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3506397160
Short name T547
Test name
Test status
Simulation time 122225335263 ps
CPU time 441.19 seconds
Started May 12 04:14:09 PM PDT 24
Finished May 12 04:21:30 PM PDT 24
Peak memory 202744 kb
Host smart-ba09af21-4c9d-432b-9bec-23446299f910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506397160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3506397160
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1295624530
Short name T546
Test name
Test status
Simulation time 32797537450 ps
CPU time 11.33 seconds
Started May 12 04:14:10 PM PDT 24
Finished May 12 04:14:22 PM PDT 24
Peak memory 202124 kb
Host smart-b5634e6f-570c-42ec-96e3-c967a4519cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295624530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1295624530
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3635879499
Short name T703
Test name
Test status
Simulation time 5164844613 ps
CPU time 1.58 seconds
Started May 12 04:14:10 PM PDT 24
Finished May 12 04:14:12 PM PDT 24
Peak memory 202080 kb
Host smart-41d585f0-a6dc-4c8f-bb46-b2b828ecde4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635879499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3635879499
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2221281843
Short name T377
Test name
Test status
Simulation time 5945147458 ps
CPU time 2.89 seconds
Started May 12 04:14:10 PM PDT 24
Finished May 12 04:14:13 PM PDT 24
Peak memory 202136 kb
Host smart-59231ce5-4895-4ff1-9b06-ce3f6f7bc6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221281843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2221281843
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4202916094
Short name T486
Test name
Test status
Simulation time 219890313019 ps
CPU time 152.61 seconds
Started May 12 04:14:12 PM PDT 24
Finished May 12 04:16:45 PM PDT 24
Peak memory 202500 kb
Host smart-7d5bcb3f-8f13-4cb0-bcd8-c1292da908d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202916094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4202916094
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3311596366
Short name T20
Test name
Test status
Simulation time 34434358141 ps
CPU time 83.79 seconds
Started May 12 04:14:12 PM PDT 24
Finished May 12 04:15:36 PM PDT 24
Peak memory 210728 kb
Host smart-81772937-a9b1-41be-9ae0-42494a0fa9b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311596366 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3311596366
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2873463439
Short name T345
Test name
Test status
Simulation time 368914383 ps
CPU time 0.81 seconds
Started May 12 04:14:30 PM PDT 24
Finished May 12 04:14:31 PM PDT 24
Peak memory 202000 kb
Host smart-928cbce9-5906-4f9f-bb99-ba918ac4b1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873463439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2873463439
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1589182875
Short name T533
Test name
Test status
Simulation time 172196509239 ps
CPU time 394.14 seconds
Started May 12 04:14:13 PM PDT 24
Finished May 12 04:20:48 PM PDT 24
Peak memory 202416 kb
Host smart-c5a4c37e-bb50-4d59-8e6d-2571296805c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589182875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1589182875
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1149004770
Short name T756
Test name
Test status
Simulation time 160003117319 ps
CPU time 84.4 seconds
Started May 12 04:14:19 PM PDT 24
Finished May 12 04:15:43 PM PDT 24
Peak memory 202488 kb
Host smart-1c1cb0c1-7e21-4a20-8fad-2e85c29d3feb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149004770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1149004770
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2381575829
Short name T529
Test name
Test status
Simulation time 163214092344 ps
CPU time 375.62 seconds
Started May 12 04:14:14 PM PDT 24
Finished May 12 04:20:30 PM PDT 24
Peak memory 202324 kb
Host smart-eacd3e2b-68d9-4372-9d8b-00c14abb0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381575829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2381575829
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.728956817
Short name T589
Test name
Test status
Simulation time 162644654327 ps
CPU time 152.63 seconds
Started May 12 04:14:14 PM PDT 24
Finished May 12 04:16:47 PM PDT 24
Peak memory 202296 kb
Host smart-3da24ab6-ffcd-4bb9-b4a0-27f37ac0fce1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=728956817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.728956817
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2800356765
Short name T643
Test name
Test status
Simulation time 406764669433 ps
CPU time 206.91 seconds
Started May 12 04:14:18 PM PDT 24
Finished May 12 04:17:45 PM PDT 24
Peak memory 202316 kb
Host smart-8d2319d5-9201-4dfe-89ea-6d8fe84f52ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800356765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2800356765
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2930591422
Short name T739
Test name
Test status
Simulation time 82453524219 ps
CPU time 425.03 seconds
Started May 12 04:14:29 PM PDT 24
Finished May 12 04:21:35 PM PDT 24
Peak memory 202652 kb
Host smart-3c86b1eb-4e08-46ad-9faa-6e0696870b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930591422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2930591422
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2204988380
Short name T661
Test name
Test status
Simulation time 38723895181 ps
CPU time 22.42 seconds
Started May 12 04:14:24 PM PDT 24
Finished May 12 04:14:47 PM PDT 24
Peak memory 202164 kb
Host smart-1c360d97-6c3f-4970-89c9-95fc21261295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204988380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2204988380
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1921602414
Short name T767
Test name
Test status
Simulation time 3827612917 ps
CPU time 9.78 seconds
Started May 12 04:14:24 PM PDT 24
Finished May 12 04:14:34 PM PDT 24
Peak memory 202084 kb
Host smart-09337d32-0b5b-4985-ae39-97fc3508ca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921602414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1921602414
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2329246304
Short name T373
Test name
Test status
Simulation time 5764255719 ps
CPU time 10.95 seconds
Started May 12 04:14:12 PM PDT 24
Finished May 12 04:14:24 PM PDT 24
Peak memory 202144 kb
Host smart-7188637e-9e2f-4dc5-8dd3-94391f717d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329246304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2329246304
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3076704069
Short name T200
Test name
Test status
Simulation time 578699644643 ps
CPU time 1377.03 seconds
Started May 12 04:14:28 PM PDT 24
Finished May 12 04:37:25 PM PDT 24
Peak memory 213872 kb
Host smart-f78f9ad0-61cd-4d04-b6e1-840be22b04f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076704069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3076704069
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1095961722
Short name T19
Test name
Test status
Simulation time 56418563435 ps
CPU time 89.28 seconds
Started May 12 04:14:29 PM PDT 24
Finished May 12 04:15:59 PM PDT 24
Peak memory 211092 kb
Host smart-b417aa49-307d-4114-9c7d-4d686dba34fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095961722 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1095961722
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1930390530
Short name T453
Test name
Test status
Simulation time 530489010 ps
CPU time 1.74 seconds
Started May 12 04:14:37 PM PDT 24
Finished May 12 04:14:39 PM PDT 24
Peak memory 201980 kb
Host smart-d061c357-5ece-4975-9b94-f81fbf41614a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930390530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1930390530
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3699278166
Short name T732
Test name
Test status
Simulation time 508267446631 ps
CPU time 1142.91 seconds
Started May 12 04:14:35 PM PDT 24
Finished May 12 04:33:38 PM PDT 24
Peak memory 202316 kb
Host smart-b5b9b275-14e6-4c34-ab26-75347efe0c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699278166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3699278166
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3439902448
Short name T564
Test name
Test status
Simulation time 167010045519 ps
CPU time 388.77 seconds
Started May 12 04:14:34 PM PDT 24
Finished May 12 04:21:03 PM PDT 24
Peak memory 202304 kb
Host smart-9292aca7-47b0-4e06-88e0-3fe3fbd709c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439902448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3439902448
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2075147136
Short name T686
Test name
Test status
Simulation time 326034621263 ps
CPU time 802.34 seconds
Started May 12 04:14:32 PM PDT 24
Finished May 12 04:27:55 PM PDT 24
Peak memory 202312 kb
Host smart-9c118513-12bd-4510-80d9-3f529b544095
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075147136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2075147136
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3235483884
Short name T123
Test name
Test status
Simulation time 483101189663 ps
CPU time 168.77 seconds
Started May 12 04:14:29 PM PDT 24
Finished May 12 04:17:19 PM PDT 24
Peak memory 202260 kb
Host smart-0c52a03f-7f6b-4a8c-8c8c-74333f42dfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235483884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3235483884
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1402684201
Short name T518
Test name
Test status
Simulation time 503559680457 ps
CPU time 1099.88 seconds
Started May 12 04:14:30 PM PDT 24
Finished May 12 04:32:50 PM PDT 24
Peak memory 202348 kb
Host smart-d971e66b-cce4-4b4c-ae87-4841efb6c247
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402684201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1402684201
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.384677532
Short name T40
Test name
Test status
Simulation time 396185583092 ps
CPU time 112.49 seconds
Started May 12 04:14:32 PM PDT 24
Finished May 12 04:16:25 PM PDT 24
Peak memory 202352 kb
Host smart-6ad80c74-e7f3-47bc-9947-e7361a44d35d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384677532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.384677532
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2306503609
Short name T129
Test name
Test status
Simulation time 595318206511 ps
CPU time 323.54 seconds
Started May 12 04:14:35 PM PDT 24
Finished May 12 04:19:59 PM PDT 24
Peak memory 202232 kb
Host smart-5dac4f6e-a0aa-4eab-b951-433bef331aab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306503609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2306503609
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.770782957
Short name T394
Test name
Test status
Simulation time 31034672351 ps
CPU time 17.42 seconds
Started May 12 04:14:38 PM PDT 24
Finished May 12 04:14:56 PM PDT 24
Peak memory 202124 kb
Host smart-d4a4258d-56f3-40b1-9fb3-cfe645be6d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770782957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.770782957
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2142427813
Short name T367
Test name
Test status
Simulation time 3237315698 ps
CPU time 4.23 seconds
Started May 12 04:14:39 PM PDT 24
Finished May 12 04:14:44 PM PDT 24
Peak memory 202140 kb
Host smart-5232c1d0-66f6-4a82-ba6e-7a76cf337427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142427813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2142427813
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1821381579
Short name T358
Test name
Test status
Simulation time 5844062275 ps
CPU time 13.99 seconds
Started May 12 04:14:31 PM PDT 24
Finished May 12 04:14:45 PM PDT 24
Peak memory 202156 kb
Host smart-c82ee4f4-8ef6-4ff0-902d-f32c5225cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821381579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1821381579
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1513200311
Short name T487
Test name
Test status
Simulation time 75609354374 ps
CPU time 39.34 seconds
Started May 12 04:14:38 PM PDT 24
Finished May 12 04:15:18 PM PDT 24
Peak memory 210636 kb
Host smart-70b55f06-026c-4acf-909a-aa3109a2873b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513200311 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1513200311
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4034049782
Short name T707
Test name
Test status
Simulation time 333961957 ps
CPU time 1.05 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:09:17 PM PDT 24
Peak memory 202000 kb
Host smart-bf758019-9e90-4e5c-bf3b-28549aac8b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034049782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4034049782
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2564475163
Short name T660
Test name
Test status
Simulation time 365603147483 ps
CPU time 441.61 seconds
Started May 12 04:09:12 PM PDT 24
Finished May 12 04:16:35 PM PDT 24
Peak memory 202272 kb
Host smart-49dab129-932a-42e1-a9c9-df92bed9789b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564475163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2564475163
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.390174553
Short name T282
Test name
Test status
Simulation time 322631935206 ps
CPU time 387.46 seconds
Started May 12 04:09:13 PM PDT 24
Finished May 12 04:15:41 PM PDT 24
Peak memory 202324 kb
Host smart-3831f20a-26bf-4738-8efd-5f804b56458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390174553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.390174553
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3560256830
Short name T636
Test name
Test status
Simulation time 323325865679 ps
CPU time 387.87 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:15:44 PM PDT 24
Peak memory 202272 kb
Host smart-2b82fc22-4ef7-4285-8236-2a8cf876d3d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560256830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3560256830
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3884638240
Short name T240
Test name
Test status
Simulation time 321169832412 ps
CPU time 114.43 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:11:09 PM PDT 24
Peak memory 202380 kb
Host smart-99378655-b5cf-447d-9778-f18648c0c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884638240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3884638240
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1763306588
Short name T534
Test name
Test status
Simulation time 499490905626 ps
CPU time 1216.35 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:29:31 PM PDT 24
Peak memory 202288 kb
Host smart-33b55784-4625-4526-9987-aade3bb53f2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763306588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1763306588
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3194385924
Short name T261
Test name
Test status
Simulation time 538955216965 ps
CPU time 622.11 seconds
Started May 12 04:09:18 PM PDT 24
Finished May 12 04:19:41 PM PDT 24
Peak memory 202412 kb
Host smart-31e5e71e-2afb-462e-b172-34dd8839d045
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194385924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3194385924
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1418299777
Short name T516
Test name
Test status
Simulation time 198003646021 ps
CPU time 115.2 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:11:11 PM PDT 24
Peak memory 202308 kb
Host smart-71045a12-ade3-4e52-9279-9741adbfba4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418299777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1418299777
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1577247931
Short name T618
Test name
Test status
Simulation time 64547675739 ps
CPU time 295.11 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:14:11 PM PDT 24
Peak memory 202684 kb
Host smart-311876d9-d757-435f-abec-2117a31d529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577247931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1577247931
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3682302477
Short name T348
Test name
Test status
Simulation time 26491684950 ps
CPU time 66.86 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:10:23 PM PDT 24
Peak memory 202020 kb
Host smart-9e93ce37-a205-4a86-a5a5-16176d0e9069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682302477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3682302477
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.667417930
Short name T84
Test name
Test status
Simulation time 5772081866 ps
CPU time 7.55 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:09:23 PM PDT 24
Peak memory 201980 kb
Host smart-26219753-4a57-4e51-8cf0-c7e853512dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667417930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.667417930
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3358631909
Short name T379
Test name
Test status
Simulation time 5832066229 ps
CPU time 3.99 seconds
Started May 12 04:09:18 PM PDT 24
Finished May 12 04:09:23 PM PDT 24
Peak memory 202156 kb
Host smart-812939c7-bf5b-4b63-8297-1f0707ad77e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358631909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3358631909
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2475116503
Short name T407
Test name
Test status
Simulation time 172397299093 ps
CPU time 115.82 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:11:11 PM PDT 24
Peak memory 202272 kb
Host smart-774d0f89-ba46-45fa-9d66-85eed69e9bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475116503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2475116503
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2839085488
Short name T34
Test name
Test status
Simulation time 113816175963 ps
CPU time 273.26 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:13:51 PM PDT 24
Peak memory 210940 kb
Host smart-8c1f85ff-9218-4fe7-a791-5a7840720562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839085488 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2839085488
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3539736855
Short name T350
Test name
Test status
Simulation time 442516947 ps
CPU time 0.93 seconds
Started May 12 04:09:18 PM PDT 24
Finished May 12 04:09:19 PM PDT 24
Peak memory 202004 kb
Host smart-21e64bf8-19a5-40cb-96bd-a66e582805c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539736855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3539736855
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1765324520
Short name T49
Test name
Test status
Simulation time 572187799834 ps
CPU time 182.82 seconds
Started May 12 04:09:18 PM PDT 24
Finished May 12 04:12:22 PM PDT 24
Peak memory 202316 kb
Host smart-de475631-3641-4d6f-8c35-d333431a7501
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765324520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1765324520
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1490185047
Short name T143
Test name
Test status
Simulation time 518360467951 ps
CPU time 585.23 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:19:08 PM PDT 24
Peak memory 202324 kb
Host smart-2a3f4f51-8708-4669-842b-080d8d447740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490185047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1490185047
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2075551687
Short name T120
Test name
Test status
Simulation time 323478442930 ps
CPU time 183.65 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:12:22 PM PDT 24
Peak memory 202324 kb
Host smart-a13031eb-70c8-4087-9446-7c351f880e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075551687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2075551687
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1908193456
Short name T675
Test name
Test status
Simulation time 162165460437 ps
CPU time 195.45 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:12:33 PM PDT 24
Peak memory 202288 kb
Host smart-f701f9c4-69ef-4fdf-8e8e-22625b93194b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908193456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1908193456
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2571924638
Short name T159
Test name
Test status
Simulation time 331480980391 ps
CPU time 200.21 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:12:35 PM PDT 24
Peak memory 202292 kb
Host smart-3189ba79-49b0-4bee-a23b-2bc0f455c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571924638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2571924638
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3512587363
Short name T502
Test name
Test status
Simulation time 491718281460 ps
CPU time 1029.08 seconds
Started May 12 04:09:17 PM PDT 24
Finished May 12 04:26:27 PM PDT 24
Peak memory 202304 kb
Host smart-2e2a1f24-b5ce-4098-8941-c675c1b6d474
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512587363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3512587363
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.171638950
Short name T287
Test name
Test status
Simulation time 172882072088 ps
CPU time 405.5 seconds
Started May 12 04:09:16 PM PDT 24
Finished May 12 04:16:03 PM PDT 24
Peak memory 202424 kb
Host smart-2a2dc007-91cd-4df9-ba4b-fdf8bfa30c01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171638950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.171638950
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3494148537
Short name T626
Test name
Test status
Simulation time 592298905972 ps
CPU time 1337.3 seconds
Started May 12 04:09:18 PM PDT 24
Finished May 12 04:31:36 PM PDT 24
Peak memory 202404 kb
Host smart-ffbe1f63-8015-4bd5-8d7c-563ec83b47a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494148537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3494148537
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.673498810
Short name T328
Test name
Test status
Simulation time 79906825502 ps
CPU time 344 seconds
Started May 12 04:09:14 PM PDT 24
Finished May 12 04:14:59 PM PDT 24
Peak memory 202700 kb
Host smart-1d56cbdc-8dcc-495b-9aed-6ddc68e72a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673498810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.673498810
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3372313700
Short name T444
Test name
Test status
Simulation time 33502458066 ps
CPU time 17.27 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:09:47 PM PDT 24
Peak memory 202096 kb
Host smart-b7b3a3e4-abe3-465b-9468-c9809f3c508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372313700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3372313700
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1350161781
Short name T563
Test name
Test status
Simulation time 4613096281 ps
CPU time 1.42 seconds
Started May 12 04:09:16 PM PDT 24
Finished May 12 04:09:18 PM PDT 24
Peak memory 202136 kb
Host smart-e073e95c-e1f4-4a24-b7b3-be1d8322e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350161781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1350161781
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.962380338
Short name T450
Test name
Test status
Simulation time 5950034130 ps
CPU time 4.56 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:09:20 PM PDT 24
Peak memory 202152 kb
Host smart-630b5cc2-e07a-4192-8d34-6264cee23e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962380338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.962380338
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3354186517
Short name T593
Test name
Test status
Simulation time 219415479741 ps
CPU time 483.9 seconds
Started May 12 04:09:16 PM PDT 24
Finished May 12 04:17:21 PM PDT 24
Peak memory 202288 kb
Host smart-d5bb1913-a3f8-4ac6-bad6-884a6407e34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354186517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3354186517
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3973874196
Short name T36
Test name
Test status
Simulation time 102069615427 ps
CPU time 84.97 seconds
Started May 12 04:09:15 PM PDT 24
Finished May 12 04:10:41 PM PDT 24
Peak memory 210976 kb
Host smart-025b4c97-f626-407e-b6df-d611bb40760d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973874196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3973874196
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1352073730
Short name T477
Test name
Test status
Simulation time 486020166 ps
CPU time 1.71 seconds
Started May 12 04:09:19 PM PDT 24
Finished May 12 04:09:22 PM PDT 24
Peak memory 202008 kb
Host smart-7def5d61-7ad2-4091-aa60-2421bbd10270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352073730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1352073730
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.184175759
Short name T199
Test name
Test status
Simulation time 328828505137 ps
CPU time 657.24 seconds
Started May 12 04:09:19 PM PDT 24
Finished May 12 04:20:17 PM PDT 24
Peak memory 202244 kb
Host smart-76cb105b-28c6-415e-a614-572a0a11f6cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184175759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.184175759
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.535260060
Short name T308
Test name
Test status
Simulation time 513020578285 ps
CPU time 206.14 seconds
Started May 12 04:09:21 PM PDT 24
Finished May 12 04:12:48 PM PDT 24
Peak memory 202376 kb
Host smart-779039aa-99de-40f9-bcf8-6c50d50585c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535260060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.535260060
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.878065166
Short name T303
Test name
Test status
Simulation time 492775349180 ps
CPU time 564.25 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:18:46 PM PDT 24
Peak memory 202356 kb
Host smart-02aed37d-68a3-42df-8d6a-9c60b0041dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878065166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.878065166
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1063358586
Short name T515
Test name
Test status
Simulation time 164544836586 ps
CPU time 62.58 seconds
Started May 12 04:09:20 PM PDT 24
Finished May 12 04:10:23 PM PDT 24
Peak memory 202296 kb
Host smart-40e89ee0-0a46-4d9d-9e83-c4b9460ffa9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063358586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1063358586
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3812733377
Short name T685
Test name
Test status
Simulation time 494802109161 ps
CPU time 229.05 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:13:11 PM PDT 24
Peak memory 202268 kb
Host smart-102d4ff0-4d2c-4b90-b359-3b1216078e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812733377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3812733377
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1176804701
Short name T782
Test name
Test status
Simulation time 168142759938 ps
CPU time 94.22 seconds
Started May 12 04:09:28 PM PDT 24
Finished May 12 04:11:03 PM PDT 24
Peak memory 202240 kb
Host smart-d94a57fb-9764-4dcf-a8a3-964bfa0d4679
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176804701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1176804701
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1674997093
Short name T8
Test name
Test status
Simulation time 211303903195 ps
CPU time 69.23 seconds
Started May 12 04:09:29 PM PDT 24
Finished May 12 04:10:39 PM PDT 24
Peak memory 202368 kb
Host smart-e9a554a2-ed06-4f2e-a040-e02ca59eb9dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674997093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1674997093
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3962054063
Short name T433
Test name
Test status
Simulation time 388387925491 ps
CPU time 932.23 seconds
Started May 12 04:09:20 PM PDT 24
Finished May 12 04:24:53 PM PDT 24
Peak memory 202348 kb
Host smart-57a86b6f-e448-4c46-aa2a-ab1c199b57cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962054063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3962054063
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.936447008
Short name T332
Test name
Test status
Simulation time 111318676173 ps
CPU time 640.94 seconds
Started May 12 04:09:19 PM PDT 24
Finished May 12 04:20:00 PM PDT 24
Peak memory 202760 kb
Host smart-5f61d99c-525e-4bfa-a59f-46495ea082a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936447008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.936447008
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3898684346
Short name T364
Test name
Test status
Simulation time 45129841252 ps
CPU time 55.31 seconds
Started May 12 04:09:20 PM PDT 24
Finished May 12 04:10:16 PM PDT 24
Peak memory 202028 kb
Host smart-a931c9f5-74d1-4fb7-9db3-6ddbf96971ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898684346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3898684346
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2615686541
Short name T652
Test name
Test status
Simulation time 4199560277 ps
CPU time 5.38 seconds
Started May 12 04:09:29 PM PDT 24
Finished May 12 04:09:35 PM PDT 24
Peak memory 202096 kb
Host smart-f2ceb56d-7f69-4cf4-9166-74deeca54479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615686541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2615686541
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.465865335
Short name T527
Test name
Test status
Simulation time 5820999478 ps
CPU time 3.88 seconds
Started May 12 04:09:24 PM PDT 24
Finished May 12 04:09:29 PM PDT 24
Peak memory 202104 kb
Host smart-3e802d74-d652-4820-be47-674285541977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465865335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.465865335
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1055122479
Short name T253
Test name
Test status
Simulation time 222134509175 ps
CPU time 519.67 seconds
Started May 12 04:09:31 PM PDT 24
Finished May 12 04:18:11 PM PDT 24
Peak memory 202264 kb
Host smart-060e3e39-aeff-4ae2-b54e-c18950bf518f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055122479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1055122479
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2407354604
Short name T82
Test name
Test status
Simulation time 344637792 ps
CPU time 0.85 seconds
Started May 12 04:09:25 PM PDT 24
Finished May 12 04:09:26 PM PDT 24
Peak memory 202000 kb
Host smart-a1970612-9978-49d1-913b-6caba6b7c6bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407354604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2407354604
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2781970970
Short name T48
Test name
Test status
Simulation time 332258734067 ps
CPU time 121.88 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:11:39 PM PDT 24
Peak memory 202276 kb
Host smart-7387bb51-355c-45f4-b1d7-495856c21501
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781970970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2781970970
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.156276545
Short name T296
Test name
Test status
Simulation time 383613480676 ps
CPU time 481.4 seconds
Started May 12 04:09:18 PM PDT 24
Finished May 12 04:17:20 PM PDT 24
Peak memory 202300 kb
Host smart-69bbaaa4-e0ab-4881-b510-6df2c9d80948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156276545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.156276545
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2645531674
Short name T153
Test name
Test status
Simulation time 168915489628 ps
CPU time 359.46 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:15:22 PM PDT 24
Peak memory 202328 kb
Host smart-f8e17841-a839-49dd-a70f-e6c372385cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645531674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2645531674
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3989503325
Short name T474
Test name
Test status
Simulation time 484450866218 ps
CPU time 603.61 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:19:26 PM PDT 24
Peak memory 202360 kb
Host smart-f45b2070-4673-4fb0-bdf4-86cf453c0765
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989503325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3989503325
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1203147264
Short name T249
Test name
Test status
Simulation time 322357972852 ps
CPU time 705.3 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:21:09 PM PDT 24
Peak memory 202296 kb
Host smart-4a6d73d2-a9cf-4b4b-aba5-28795bf7c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203147264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1203147264
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.857016639
Short name T623
Test name
Test status
Simulation time 491672548746 ps
CPU time 279.42 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:14:16 PM PDT 24
Peak memory 202244 kb
Host smart-4f31d660-9bcc-431d-9858-db62e191ba7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=857016639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.857016639
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4089733318
Short name T471
Test name
Test status
Simulation time 393311072945 ps
CPU time 243.84 seconds
Started May 12 04:09:34 PM PDT 24
Finished May 12 04:13:39 PM PDT 24
Peak memory 202368 kb
Host smart-9ff3621b-cd7a-4500-bee8-6c1233026f94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089733318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4089733318
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3026498706
Short name T750
Test name
Test status
Simulation time 603239269307 ps
CPU time 1399.66 seconds
Started May 12 04:09:29 PM PDT 24
Finished May 12 04:32:50 PM PDT 24
Peak memory 202352 kb
Host smart-33d0a236-7518-4d68-be4d-9104b7e1a41f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026498706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3026498706
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.947188678
Short name T530
Test name
Test status
Simulation time 108387177359 ps
CPU time 589.67 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:19:12 PM PDT 24
Peak memory 202688 kb
Host smart-69ecaccf-64f8-4cc3-930d-fc4ee8ddf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947188678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.947188678
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.372359218
Short name T475
Test name
Test status
Simulation time 41072721261 ps
CPU time 18.47 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:09:42 PM PDT 24
Peak memory 202136 kb
Host smart-9507230e-3ce3-4b3a-9fd3-cfc0205bdfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372359218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.372359218
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3698484706
Short name T371
Test name
Test status
Simulation time 4826808159 ps
CPU time 3.74 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:09:28 PM PDT 24
Peak memory 202120 kb
Host smart-8f196343-1d05-4cc6-b966-f41042b3d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698484706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3698484706
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.837165734
Short name T768
Test name
Test status
Simulation time 6101942183 ps
CPU time 14.05 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:09:38 PM PDT 24
Peak memory 202132 kb
Host smart-7f0ea88b-6124-4dac-8442-b21304bc2bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837165734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.837165734
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.917394719
Short name T206
Test name
Test status
Simulation time 190663422652 ps
CPU time 120.15 seconds
Started May 12 04:09:24 PM PDT 24
Finished May 12 04:11:24 PM PDT 24
Peak memory 202324 kb
Host smart-78275cfc-78e2-4eff-b04a-2b945708baa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917394719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.917394719
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.670443310
Short name T731
Test name
Test status
Simulation time 77273163947 ps
CPU time 78.48 seconds
Started May 12 04:09:24 PM PDT 24
Finished May 12 04:10:43 PM PDT 24
Peak memory 211264 kb
Host smart-b486c55b-a0cf-4788-840b-b207d10f3331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670443310 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.670443310
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3443147965
Short name T353
Test name
Test status
Simulation time 531854440 ps
CPU time 0.82 seconds
Started May 12 04:09:26 PM PDT 24
Finished May 12 04:09:28 PM PDT 24
Peak memory 202032 kb
Host smart-8617b135-1a47-443b-8481-f89f70abce96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443147965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3443147965
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.634760759
Short name T285
Test name
Test status
Simulation time 183664417743 ps
CPU time 83.96 seconds
Started May 12 04:09:25 PM PDT 24
Finished May 12 04:10:49 PM PDT 24
Peak memory 202268 kb
Host smart-8ed52484-2518-4398-b1f7-5f0b4480a213
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634760759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.634760759
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.351037206
Short name T138
Test name
Test status
Simulation time 169888564729 ps
CPU time 211.05 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:12:55 PM PDT 24
Peak memory 202312 kb
Host smart-12a09fdc-11a4-42b2-8c0c-d3b382263117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351037206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.351037206
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2310659532
Short name T204
Test name
Test status
Simulation time 480198326390 ps
CPU time 586.43 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:19:09 PM PDT 24
Peak memory 202244 kb
Host smart-0c298c53-a60d-4668-8ba3-84bc1e90484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310659532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2310659532
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.489754972
Short name T770
Test name
Test status
Simulation time 163588784263 ps
CPU time 202.1 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:12:45 PM PDT 24
Peak memory 202328 kb
Host smart-347ccb91-75ce-42cb-bca6-bc8ae2e9ad1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=489754972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.489754972
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1159105193
Short name T116
Test name
Test status
Simulation time 334774348606 ps
CPU time 121.39 seconds
Started May 12 04:09:25 PM PDT 24
Finished May 12 04:11:27 PM PDT 24
Peak memory 202592 kb
Host smart-4a37c26d-9395-4bfb-8b21-d444520fd4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159105193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1159105193
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.713435203
Short name T705
Test name
Test status
Simulation time 497993534410 ps
CPU time 333.36 seconds
Started May 12 04:09:23 PM PDT 24
Finished May 12 04:14:57 PM PDT 24
Peak memory 202380 kb
Host smart-aca95afe-3df2-4a42-a147-e344d7c7f6b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=713435203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.713435203
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2877099545
Short name T115
Test name
Test status
Simulation time 367555238532 ps
CPU time 70.93 seconds
Started May 12 04:09:24 PM PDT 24
Finished May 12 04:10:35 PM PDT 24
Peak memory 202388 kb
Host smart-6202c2e3-0790-4240-b475-6ce98e6daf7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877099545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2877099545
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1042537558
Short name T632
Test name
Test status
Simulation time 199664442560 ps
CPU time 240.99 seconds
Started May 12 04:09:25 PM PDT 24
Finished May 12 04:13:26 PM PDT 24
Peak memory 202496 kb
Host smart-6a63d132-d397-4345-8554-4a3dd6aadf92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042537558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1042537558
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.27567499
Short name T736
Test name
Test status
Simulation time 129177918426 ps
CPU time 438.62 seconds
Started May 12 04:09:24 PM PDT 24
Finished May 12 04:16:43 PM PDT 24
Peak memory 202636 kb
Host smart-3d88e39c-d953-44e3-8a2c-e41d3424c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27567499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.27567499
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3487918341
Short name T342
Test name
Test status
Simulation time 36891060861 ps
CPU time 24.93 seconds
Started May 12 04:09:25 PM PDT 24
Finished May 12 04:09:51 PM PDT 24
Peak memory 202160 kb
Host smart-57ce3755-47b8-4c93-acb1-b06f89368571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487918341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3487918341
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.605591366
Short name T461
Test name
Test status
Simulation time 5534068745 ps
CPU time 12.86 seconds
Started May 12 04:09:22 PM PDT 24
Finished May 12 04:09:36 PM PDT 24
Peak memory 202120 kb
Host smart-904f6c2c-f1fb-4a53-88c3-0a2cd4b7f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605591366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.605591366
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.487624680
Short name T540
Test name
Test status
Simulation time 6084259222 ps
CPU time 2.45 seconds
Started May 12 04:09:35 PM PDT 24
Finished May 12 04:09:39 PM PDT 24
Peak memory 202084 kb
Host smart-58a754d6-0801-4a26-940b-97c2abb2db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487624680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.487624680
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3918775230
Short name T324
Test name
Test status
Simulation time 284565945892 ps
CPU time 706.53 seconds
Started May 12 04:09:30 PM PDT 24
Finished May 12 04:21:18 PM PDT 24
Peak memory 210912 kb
Host smart-f8804a2b-e125-41a9-b80e-bee32383b1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918775230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3918775230
Directory /workspace/9.adc_ctrl_stress_all/latest
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