Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7229	1			T3	53		T5	98		T10	32
testmodes[AdcCtrlTestmodeNormal]	5629	1			T3	37		T4	1		T5	64
testmodes[AdcCtrlTestmodeLowpower]	5675	1			T1	1		T2	20		T3	40
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3973	1			T3	35		T5	47		T10	9
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1803	1			T3	17		T5	34		T10	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1346	1			T3	1		T5	16		T10	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1764	1			T3	15		T5	24		T10	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2114	1			T3	16		T5	18		T6	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1425	1			T3	6		T5	22		T10	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1370	1			T3	3		T5	27		T10	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1375	1			T3	3		T5	11		T10	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2665	1			T2	19		T3	33		T5	15