Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23592

1

T1

16

T2

20

T3

136

auto[ADC_CTRL_FILTER_COND_OUT]

3100

1

T3

1

T4

25

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20687

1

T2

20

T3

130

T5

214

auto[1]

6005

1

T1

16

T3

7

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T218	4		-	-		-	-
values[0]	62	1			T128	3		T95	1		T219	14
values[1]	536	1			T3	1		T76	8		T41	17
values[2]	3063	1			T1	16		T8	27		T74	1
values[3]	665	1			T33	21		T130	23		T220	28
values[4]	685	1			T6	15		T221	11		T222	14
values[5]	746	1			T6	1		T11	26		T34	16
values[6]	700	1			T21	27		T131	16		T30	5
values[7]	627	1			T3	7		T9	8		T122	1
values[8]	748	1			T4	25		T7	1		T36	11
values[9]	1225	1			T5	5		T7	1		T11	25
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	823	1			T41	17		T138	8		T122	1
values[1]	2996	1			T1	16		T3	1		T8	27
values[2]	625	1			T33	21		T130	23		T220	28
values[3]	718	1			T6	16		T11	26		T221	11
values[4]	727	1			T21	27		T34	16		T41	1
values[5]	745	1			T9	8		T131	16		T28	3
values[6]	604	1			T3	7		T36	11		T122	1
values[7]	847	1			T4	25		T7	1		T32	37
values[8]	806	1			T5	5		T7	1		T11	25
values[9]	155	1			T129	9		T132	7		T223	10
minimum	17646	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	8		T138	1		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	7		T124	20		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1686	1			T1	16		T8	27		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T27	6		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	11		T139	1		T91	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T130	12		T220	16		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T222	14		T224	1		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	2		T11	14		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T21	14		T34	16		T131	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	1		T125	1		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T135	6		T91	13		T93	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	8		T131	5		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	5		T13	4		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T36	1		T122	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T32	20		T25	4		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	12		T7	1		T33	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	2		T11	12		T76	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T33	6		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T223	10		T227	1		T165	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T129	1		T132	3		T228	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17487	1			T2	20		T3	125		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	9		T138	7		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	5		T124	17		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T22	10		T203	9		T229	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T27	4		T29	5		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T33	10		T139	15		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T130	11		T220	12		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T224	8		T27	3		T230	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	14		T11	12		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T21	13		T131	9		T30	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T125	8		T28	1		T231	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T135	14		T91	15		T93	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T131	11		T28	1		T132	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	2		T13	2		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T36	10		T226	7		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	17		T25	1		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	13		T33	12		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	3		T11	13		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	6		T158	13		T233	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T227	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T129	8		T132	4		T234	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	4		T128	2		T22	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T218	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T128	1		T95	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T76	8		T41	8		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	1		T124	9		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T1	16		T8	27		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	6		T12	7		T124	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T33	11		T91	1		T172	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T130	12		T220	16		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T222	14		T224	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T221	1		T157	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T34	16		T131	8		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	1		T11	14		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T21	14		T30	2		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	5		T233	1		T235	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	5		T225	1		T135	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	8		T122	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	4		T28	1		T135	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	12		T7	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T5	2		T11	12		T32	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T7	1		T33	6		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T128	2		T219	13		T180	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T41	9		T138	7		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T160	9		T236	19		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T22	10		T203	9		T229	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	4		T12	5		T124	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T33	10		T91	1		T238	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T130	11		T220	12		T158	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T224	8		T27	1		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	14		T221	10		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T131	9		T27	2		T232	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	12		T125	8		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T21	13		T30	3		T91	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	11		T233	13		T235	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	2		T135	14		T140	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T226	7		T132	4		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	2		T135	12		T232	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	13		T36	10		T33	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	3		T11	13		T32	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T33	6		T129	8		T158	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T41	10		T138	8		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	8		T124	19		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T1	1		T8	3		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T27	8		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T33	11		T139	16		T91	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	12		T220	13		T125	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T222	1		T224	9		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	16		T11	13		T221	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T21	14		T34	1		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	1		T125	9		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T135	15		T91	16		T93	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	1		T131	12		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	6		T13	5		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	11		T122	1		T226	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T32	18		T25	4		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	14		T7	1		T33	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	5		T11	14		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T33	7		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T223	1		T227	13		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T129	9		T132	5		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17635	1			T2	20		T3	129		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	7		T222	6		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	4		T124	18		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T1	15		T8	24		T76	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T27	2		T29	3		T31	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T33	10		T14	12		T239	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T130	11		T220	15		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T222	13		T27	3		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	13		T157	10		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T21	13		T34	15		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T28	1		T234	1		T241	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T135	5		T91	12		T93	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T9	7		T131	4		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T13	1		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T232	8		T195	8		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T32	19		T25	1		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	11		T33	11		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	11		T76	6		T243	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	5		T158	15		T233	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T223	9		T165	13		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T132	2		T228	8		T234	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T245	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T128	3		T95	1		T219	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T76	1		T41	10		T138	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T124	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T1	1		T8	3		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	8		T12	8		T124	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T33	11		T91	2		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T130	12		T220	13		T158	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T222	1		T224	9		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	15		T221	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T34	1		T131	10		T27	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T11	13		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T21	14		T30	5		T91	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T131	12		T233	14		T235	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	6		T225	1		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	1		T122	1		T226	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	5		T28	1		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	14		T7	1		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T5	5		T11	14		T32	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T7	1		T33	7		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T218	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T180	11		T246	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T76	7		T41	7		T222	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T124	8		T160	11		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T1	15		T8	24		T247	37
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T27	2		T12	4		T124	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T33	10		T172	2		T239	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	11		T220	15		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T222	13		T27	1		T14	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T157	10		T240	16		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	15		T131	7		T27	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T11	13		T28	2		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	13		T91	12		T93	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T131	4		T235	21		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T135	5		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T9	7		T132	1		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	1		T135	15		T232	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	11		T33	11		T233	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	11		T32	19		T76	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T33	5		T158	15		T132	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22891

1

T1

16

T2

20

T3

137

auto[ADC_CTRL_FILTER_COND_OUT]

3801

1

T4

25

T6

1

T21

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20450

1

T2

20

T3

117

T4

25

auto[1]

6242

1

T1

16

T3

20

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	435	1			T3	13		T5	7		T10	6
values[0]	4	1			T28	4		-	-		-	-
values[1]	695	1			T11	26		T33	24		T22	11
values[2]	3144	1			T1	16		T4	25		T6	1
values[3]	683	1			T21	27		T222	14		T226	8
values[4]	810	1			T26	4		T41	1		T131	17
values[5]	590	1			T221	11		T157	11		T130	23
values[6]	766	1			T32	37		T33	12		T34	16
values[7]	727	1			T3	7		T5	1		T7	1
values[8]	715	1			T6	15		T41	17		T224	9
values[9]	925	1			T3	1		T5	4		T7	1
minimum	17198	1			T2	20		T3	116		T5	206

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T6	1		T11	26		T33	24
values[1]	2990	1			T1	16		T4	25		T8	27
values[2]	796	1			T11	25		T21	27		T131	17
values[3]	851	1			T26	4		T41	1		T122	1
values[4]	710	1			T34	16		T221	11		T129	9
values[5]	690	1			T32	37		T33	12		T76	7
values[6]	639	1			T3	7		T5	1		T6	15
values[7]	716	1			T36	11		T131	16		T224	9
values[8]	596	1			T3	1		T7	1		T9	8
values[9]	175	1			T5	4		T76	8		T122	1
minimum	17644	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	14		T22	1		T27	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T6	1		T33	12		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T1	16		T8	27		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	12		T25	4		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	12		T122	1		T222	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T21	14		T131	8		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	3		T41	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T122	1		T28	2		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T221	1		T130	12		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T34	16		T129	1		T157	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T76	7		T29	6		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T32	20		T33	6		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	5		T5	1		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T33	11		T138	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T36	1		T131	5		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T224	1		T125	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T7	1		T9	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T222	7		T27	6		T94	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T5	1		T76	8		T243	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T122	1		T145	1		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17483	1			T2	20		T3	125		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	12		T22	10		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T33	12		T129	7		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T203	9		T229	24		T27	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	13		T25	1		T226	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	13		T220	12		T13	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T21	13		T131	9		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	1		T31	3		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T28	1		T135	14		T188	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T221	10		T130	11		T91	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T129	8		T124	17		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T29	5		T238	5		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T32	17		T33	6		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	2		T6	14		T132	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	10		T138	2		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T36	10		T131	11		T139	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T224	8		T125	12		T251	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T41	9		T135	8		T252	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T27	4		T94	14		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T5	3		T132	4		T91	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T145	10		T249	9		T253	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	4		T22	2		T26	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T3	13		T5	7		T10	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T28	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	14		T22	1		T124	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	12		T129	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T1	16		T8	27		T11	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	12		T6	1		T25	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T222	14		T27	4		T13	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	14		T226	1		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	3		T41	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T131	8		T122	1		T233	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T221	1		T130	12		T136	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T157	11		T124	11		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T76	7		T29	6		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T32	20		T33	6		T34	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	5		T5	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T33	11		T138	2		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	1		T41	8		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T224	1		T254	1		T252	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T5	1		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T122	1		T222	7		T27	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17041	1			T2	20		T3	112		T5	206
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T28	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	12		T22	10		T231	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T33	12		T129	7		T125	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T11	13		T203	9		T229	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	13		T25	1		T12	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T27	2		T13	2		T255	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T21	13		T226	7		T232	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	1		T31	3		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T131	9		T233	9		T188	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T221	10		T130	11		T14	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T124	17		T28	1		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	5		T91	1		T238	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T32	17		T33	6		T128	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	2		T132	4		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T33	10		T138	9		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	14		T41	9		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T224	8		T254	11		T252	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	3		T36	10		T131	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T27	4		T94	14		T231	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3