Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23078

1

T1

16

T2

20

T3

137

auto[ADC_CTRL_FILTER_COND_OUT]

3614

1

T4

25

T5

5

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20904

1

T2

20

T3

136

T5

218

auto[1]

5788

1

T1

16

T3

1

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	29	1			T93	1		T293	28		-	-
values[0]	69	1			T122	1		T136	3		T227	12
values[1]	559	1			T25	5		T138	3		T131	16
values[2]	636	1			T6	1		T11	25		T22	11
values[3]	707	1			T7	1		T129	9		T125	13
values[4]	833	1			T41	17		T157	11		T220	28
values[5]	791	1			T3	7		T5	1		T6	15
values[6]	741	1			T9	8		T32	37		T33	21
values[7]	724	1			T5	4		T7	1		T21	27
values[8]	2987	1			T1	16		T3	1		T8	27
values[9]	985	1			T4	25		T76	8		T128	3
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	805	1			T11	25		T25	5		T22	11
values[1]	634	1			T131	17		T129	9		T132	7
values[2]	708	1			T6	1		T7	1		T157	11
values[3]	919	1			T41	17		T130	23		T220	28
values[4]	633	1			T3	7		T5	1		T6	15
values[5]	737	1			T5	4		T9	8		T32	37
values[6]	3084	1			T1	16		T7	1		T8	27
values[7]	649	1			T3	1		T34	16		T26	4
values[8]	637	1			T4	25		T76	8		T41	1
values[9]	205	1			T128	3		T221	11		T238	1
minimum	17681	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T25	4		T22	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	12		T131	5		T222	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	8		T132	3		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T129	1		T95	1		T250	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T157	11		T225	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T125	1		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T130	12		T220	16		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T41	8		T243	5		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	5		T33	6		T76	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	1		T6	1		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	8		T27	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T32	20		T33	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1644	1			T1	16		T7	1		T8	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	14		T36	1		T158	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T34	16		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T224	1		T28	1		T188	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T76	8		T122	1		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	12		T41	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T128	1		T238	1		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T221	1		T149	1		T255	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17492	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T320	15		T325	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T25	1		T22	10		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	13		T131	11		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T131	9		T132	4		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T129	8		T250	1		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T135	8		T237	1		T288	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T125	12		T132	4		T29	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T130	11		T220	12		T91	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	9		T127	13		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	2		T33	6		T124	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	14		T11	12		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	1		T232	1		T188	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	3		T32	17		T33	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T33	12		T203	9		T229	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	13		T36	10		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	1		T138	7		T135	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T224	8		T188	9		T195	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T27	2		T233	13		T31	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	13		T129	7		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T128	2		T322	7		T292	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T221	10		T255	11		T163	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	4		T22	2		T26	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T93	1		T293	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T122	1		T136	3		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T326	9		T327	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T25	4		T138	1		T12	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T131	5		T123	13		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T22	1		T131	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	12		T222	14		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	3		T30	2		T172	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	1		T129	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T157	11		T220	16		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T41	8		T243	5		T127	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	5		T33	6		T76	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T6	1		T11	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	8		T27	8		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T32	20		T33	11		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	1		T33	12		T233	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T21	14		T243	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T1	16		T3	1		T8	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	1		T28	1		T256	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T76	8		T128	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T4	12		T221	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T293	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T227	11		T328	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T326	4		T327	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T25	1		T138	2		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	11		T123	12		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T22	10		T131	9		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	13		T250	1		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T132	4		T30	3		T236	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T129	8		T125	12		T132	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T220	12		T135	8		T91	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	9		T127	13		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	2		T33	6		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	14		T11	12		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	5		T237	1		T188	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	17		T33	10		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	12		T233	9		T232	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	3		T21	13		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T26	1		T138	7		T203	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	10		T256	1		T188	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T128	2		T27	2		T233	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T4	13		T221	10		T129	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T25	4		T22	11		T138	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	14		T131	12		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T131	10		T132	5		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T129	9		T95	1		T250	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T157	1		T225	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	1		T125	13		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T130	12		T220	13		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T41	10		T243	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	6		T33	7		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T6	15		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T27	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	4		T32	18		T33	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T1	1		T7	1		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T21	14		T36	11		T158	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T34	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T224	9		T28	1		T188	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T76	1		T122	1		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	14		T41	1		T129	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T128	3		T238	1		T322	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T221	11		T149	1		T255	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17648	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T320	1		T325	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T25	1		T12	4		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	11		T131	4		T222	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	7		T132	2		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T195	7		T234	2		T279	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T157	10		T135	9		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T132	1		T29	3		T93	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T130	11		T220	15		T91	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T41	7		T243	4		T127	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T33	5		T76	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T11	13		T140	17		T290	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	7		T27	1		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T32	19		T33	10		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T1	15		T8	24		T33	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	13		T158	15		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	15		T26	1		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T188	13		T195	8		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T76	7		T27	2		T31	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	11		T139	9		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T292	11		T329	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T255	9		T166	13		T184	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T330	17		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T320	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T93	1		T293	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T122	1		T136	1		T227	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T326	5		T327	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T25	4		T138	3		T12	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T131	12		T123	13		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	1		T22	11		T131	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	14		T222	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T132	5		T30	5		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	1		T129	9		T125	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T157	1		T220	13		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T41	10		T243	1		T127	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	6		T33	7		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T6	15		T11	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T27	10		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T32	18		T33	11		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	1		T33	13		T233	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	4		T21	14		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T1	1		T3	1		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	11		T28	1		T256	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T76	1		T128	3		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T4	14		T221	11		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T293	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T136	2		T328	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T326	8		T327	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	1		T12	4		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	4		T123	12		T137	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T131	7		T277	12		T179	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	11		T222	13		T240	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T132	2		T172	2		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T132	1		T29	3		T93	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T157	10		T220	15		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T41	7		T243	4		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	1		T33	5		T76	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	13		T140	17		T331	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	7		T27	3		T256	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T32	19		T33	10		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	11		T233	15		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	13		T243	8		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T1	15		T8	24		T34	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T256	1		T188	13		T252	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T76	7		T27	2		T135	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	11		T139	9		T31	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11