Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23154

1

T1

16

T2

20

T3

137

auto[ADC_CTRL_FILTER_COND_OUT]

3538

1

T4

25

T6

15

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20443

1

T2

20

T3

137

T5

214

auto[1]

6249

1

T1

16

T4

25

T5

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T22	11		T222	7		T134	1
values[0]	26	1			T195	24		T143	1		T271	1
values[1]	569	1			T129	9		T126	1		T91	28
values[2]	822	1			T36	11		T131	16		T122	1
values[3]	702	1			T5	1		T6	1		T32	37
values[4]	537	1			T33	21		T26	4		T41	1
values[5]	3180	1			T1	16		T4	25		T8	27
values[6]	674	1			T5	4		T138	3		T27	3
values[7]	671	1			T7	1		T9	8		T11	26
values[8]	764	1			T3	8		T6	15		T122	1
values[9]	873	1			T7	1		T21	27		T76	7
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	661	1			T36	11		T129	9		T126	1
values[1]	753	1			T32	37		T131	16		T122	1
values[2]	678	1			T5	1		T6	1		T34	16
values[3]	2983	1			T1	16		T8	27		T11	25
values[4]	750	1			T4	25		T33	12		T41	17
values[5]	611	1			T5	4		T25	5		T138	3
values[6]	710	1			T7	1		T9	8		T11	26
values[7]	703	1			T3	8		T6	15		T122	1
values[8]	831	1			T7	1		T21	27		T76	7
values[9]	202	1			T22	11		T243	5		T91	20
minimum	17810	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T126	1		T248	1		T91	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T36	1		T129	1		T158	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T32	20		T30	2		T250	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	5		T122	1		T275	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	1		T6	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T34	16		T124	9		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	16		T8	27		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	12		T26	3		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	6		T41	8		T131	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T4	12		T224	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T25	4		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	7		T158	11		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	14		T33	12		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	1		T9	8		T76	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	6		T122	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T222	14		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T76	7		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T21	14		T222	7		T124	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T22	1		T91	16		T234	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T243	5		T235	22		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17505	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T140	18		T283	8		T195	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T91	15		T137	7		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	10		T129	8		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T32	17		T30	3		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T131	11		T14	16		T257	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T231	3		T189	2		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T94	14		T14	2		T273	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T33	10		T203	9		T129	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	13		T26	1		T125	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T33	6		T41	9		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	13		T224	8		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	3		T25	1		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	5		T158	9		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	12		T33	12		T27	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T128	2		T138	7		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T3	2		T123	12		T125	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	14		T130	11		T93	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T221	10		T31	3		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T21	13		T124	17		T91	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T22	10		T91	4		T87	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T235	13		T268	15		T293	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T140	14		T283	7		T195	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T22	1		T31	5		T91	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T222	7		T134	1		T91	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T195	10		T143	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T126	1		T91	13		T232	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T129	1		T93	1		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T248	1		T30	2		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T36	1		T131	5		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	1		T6	1		T32	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T34	16		T94	1		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	11		T122	1		T157	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	3		T41	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T1	16		T8	27		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	12		T11	12		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	1		T138	1		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	7		T31	9		T136	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	14		T33	12		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	1		T9	8		T76	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	6		T122	1		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	1		T222	14		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T76	7		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T21	14		T124	11		T243	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T22	10		T31	3		T91	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T91	1		T195	7		T293	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T195	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T91	15		T232	6		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T129	8		T235	9		T140	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	3		T250	13		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T36	10		T131	11		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	17		T231	3		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T94	14		T14	18		T273	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T33	10		T28	1		T236	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	1		T139	15		T274	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T33	6		T41	9		T131	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	13		T11	13		T224	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	3		T138	2		T27	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	5		T31	8		T237	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	12		T33	12		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T128	2		T138	7		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	2		T123	12		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	14		T226	7		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T221	10		T13	2		T140	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	13		T124	17		T238	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T126	1		T248	1		T91	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T36	11		T129	9		T158	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T32	18		T30	5		T250	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T131	12		T122	1		T275	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T6	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T34	1		T124	1		T94	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T1	1		T8	3		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	14		T26	3		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	7		T41	10		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	14		T224	9		T233	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	4		T25	4		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	8		T158	10		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	13		T33	13		T27	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	1		T9	1		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	7		T122	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	15		T222	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	1		T76	1		T221	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T21	14		T222	1		T124	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T22	11		T91	5		T234	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T243	1		T235	14		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17670	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T140	15		T283	8		T195	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T91	12		T137	4		T231	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T158	15		T258	10		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T32	19		T250	14		T235	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T131	4		T275	9		T14	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T14	1		T277	1		T276	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T34	15		T124	8		T172	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T1	15		T8	24		T33	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	11		T26	1		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T33	5		T41	7		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	11		T272	10		T237	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T25	1		T27	1		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	4		T158	10		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	13		T33	11		T27	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	7		T76	7		T220	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	1		T123	12		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T222	13		T130	11		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T76	6		T31	2		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	13		T222	6		T124	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T91	15		T87	13		T332	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T243	4		T235	21		T268	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T232	2		T242	11		T333	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	17		T283	7		T195	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T22	11		T31	6		T91	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T222	1		T134	1		T91	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T195	15		T143	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T126	1		T91	16		T232	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T129	9		T93	1		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T248	1		T30	5		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T36	11		T131	12		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T6	1		T32	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	1		T94	15		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	11		T122	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	3		T41	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T1	1		T8	3		T33	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	14		T11	14		T224	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	4		T138	3		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	8		T31	12		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	13		T33	13		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T9	1		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	7		T122	1		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	15		T222	1		T226	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	1		T76	1		T221	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T21	14		T124	18		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T31	2		T91	15		T319	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T222	6		T195	8		T293	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T195	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T91	12		T232	2		T231	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T258	10		T235	4		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T250	14		T137	4		T235	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T131	4		T158	15		T275	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T32	19		T14	1		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T34	15		T172	2		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T33	10		T157	10		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T26	1		T124	8		T259	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T1	15		T8	24		T33	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	11		T11	11		T278	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T27	1		T132	3		T127	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	4		T31	5		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	13		T33	11		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	7		T76	7		T220	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T123	12		T27	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T222	13		T130	11		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T76	6		T13	1		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T21	13		T124	10		T243	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11