Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23688

1

T1

16

T2

20

T3

129

auto[ADC_CTRL_FILTER_COND_OUT]

3004

1

T3

8

T5

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20628

1

T2

20

T3

130

T4

25

auto[1]

6064

1

T1

16

T3

7

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T222	7		T158	29		T225	1
values[0]	15	1			T324	10		T286	5		-	-
values[1]	662	1			T7	1		T9	8		T41	17
values[2]	648	1			T6	15		T11	26		T226	8
values[3]	782	1			T33	12		T124	9		T158	20
values[4]	3116	1			T1	16		T3	7		T7	1
values[5]	478	1			T36	11		T33	21		T41	1
values[6]	768	1			T3	1		T5	5		T6	1
values[7]	623	1			T4	25		T34	16		T122	2
values[8]	725	1			T21	27		T33	24		T76	15
values[9]	1017	1			T11	25		T32	37		T131	33
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	651	1			T9	8		T41	17		T138	8
values[1]	660	1			T6	15		T11	26		T226	8
values[2]	852	1			T3	7		T7	1		T33	12
values[3]	3080	1			T1	16		T8	27		T36	11
values[4]	524	1			T3	1		T41	1		T138	3
values[5]	751	1			T4	25		T5	4		T6	1
values[6]	633	1			T5	1		T34	16		T76	7
values[7]	751	1			T21	27		T32	37		T33	24
values[8]	968	1			T11	25		T26	4		T131	33
values[9]	75	1			T158	29		T29	11		T15	8
minimum	17747	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	8		T138	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T41	8		T126	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	1		T11	14		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T248	1		T135	6		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T33	6		T157	11		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	5		T7	1		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T1	16		T8	27		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	1		T13	5		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T129	1		T28	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T41	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T4	12		T5	1		T133	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T27	4		T243	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	16		T122	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T76	7		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T21	14		T32	20		T124	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	12		T76	8		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T11	12		T26	3		T131	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T131	8		T224	1		T12	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T15	7		T87	9		T295	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T158	16		T29	6		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17502	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T7	1		T326	9		T334	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T138	7		T129	7		T91	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	9		T94	14		T232	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	14		T11	12		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T135	14		T235	13		T257	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T33	6		T27	1		T158	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	2		T27	4		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T33	10		T25	1		T203	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	10		T13	2		T252	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T129	8		T233	9		T239	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	2		T220	12		T31	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	13		T5	3		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	2		T256	1		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T130	11		T335	11		T242	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T128	2		T14	16		T283	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	13		T32	17		T124	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	12		T221	10		T22	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	13		T26	1		T131	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T131	9		T224	8		T12	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T15	1		T87	9		T295	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T158	13		T29	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T326	4		T334	10		T184	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T222	7		T225	1		T188	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T158	16		T132	3		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T324	3		T286	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	8		T138	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	1		T41	8		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	1		T11	14		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T248	1		T135	6		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T33	6		T124	9		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T127	14		T238	14		T250	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T1	16		T8	27		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	5		T7	1		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	11		T28	1		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T36	1		T41	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T129	1		T133	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T5	1		T6	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	12		T34	16		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T122	1		T243	9		T136	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T21	14		T26	3		T124	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	12		T76	15		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T11	12		T32	20		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T131	8		T224	1		T12	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T188	9		T15	1		T87	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T158	13		T132	4		T213	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T324	7		T286	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T138	7		T129	7		T91	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T41	9		T232	9		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	14		T11	12		T226	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	14		T94	14		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	6		T158	9		T91	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T127	13		T238	8		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T25	1		T203	9		T229	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	2		T27	4		T13	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T33	10		T132	4		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T36	10		T138	2		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	3		T129	8		T91	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T27	2		T31	8		T14	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	13		T130	11		T335	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T256	1		T137	7		T283	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	13		T26	1		T124	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T33	12		T128	2		T221	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T11	13		T32	17		T131	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T131	9		T224	8		T12	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T9	1		T138	8		T129	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T41	10		T126	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	15		T11	13		T226	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T248	1		T135	15		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T33	7		T157	1		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	6		T7	1		T27	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T1	1		T8	3		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	11		T13	6		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T129	9		T28	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T41	1		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	14		T5	4		T133	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T27	4		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	1		T122	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T76	1		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T21	14		T32	18		T124	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T33	13		T76	1		T221	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T11	14		T26	3		T131	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T131	10		T224	9		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T15	3		T87	10		T295	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T158	14		T29	8		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17679	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T7	1		T326	5		T334	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	7		T243	4		T91	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T41	7		T232	8		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	13		T28	1		T135	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T135	5		T160	7		T235	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T33	5		T157	10		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	1		T27	2		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T1	15		T8	24		T33	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T252	7		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T233	15		T172	2		T239	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T222	13		T220	15		T31	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	11		T91	15		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	2		T243	8		T256	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	15		T130	11		T335	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T76	6		T136	2		T14	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T21	13		T32	19		T124	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T33	11		T76	7		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	11		T26	1		T131	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	7		T12	4		T132	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T15	5		T87	8		T295	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T158	15		T29	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T281	11		T324	2		T336	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T326	8		T184	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T222	1		T225	1		T188	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T158	14		T132	5		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T324	8		T286	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	1		T138	8		T129	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T41	10		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	15		T11	13		T226	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T248	1		T135	15		T94	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T33	7		T124	1		T158	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	14		T238	9		T250	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T1	1		T8	3		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	6		T7	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	11		T28	1		T132	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	11		T41	1		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	4		T129	9		T133	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T5	1		T6	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	14		T34	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T122	1		T243	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	14		T26	3		T124	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T33	13		T76	2		T128	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T11	14		T32	18		T131	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T131	10		T224	9		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T222	6		T188	13		T15	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T158	15		T132	2		T223	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T324	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	7		T243	4		T91	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T41	7		T232	8		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	13		T28	1		T135	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T135	5		T160	7		T235	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T33	5		T124	8		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T127	13		T238	13		T250	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	15		T8	24		T25	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T27	2		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T33	10		T132	1		T233	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T222	13		T220	15		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T91	15		T160	11		T256	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T27	2		T31	5		T14	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	11		T34	15		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T243	8		T136	2		T256	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	13		T26	1		T124	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T33	11		T76	13		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T11	11		T32	19		T131	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	7		T12	4		T29	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11