Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23280

1

T1

16

T2

20

T3

136

auto[ADC_CTRL_FILTER_COND_OUT]

3412

1

T3

1

T5

1

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20534

1

T2

20

T3

129

T5

213

auto[1]

6158

1

T1

16

T3

8

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T76	8		T126	1		T95	1
values[0]	9	1			T299	7		T300	1		T312	1
values[1]	519	1			T11	26		T41	1		T222	7
values[2]	660	1			T3	8		T36	11		T221	11
values[3]	809	1			T4	25		T7	1		T76	7
values[4]	701	1			T5	1		T6	15		T33	21
values[5]	690	1			T6	1		T11	25		T33	12
values[6]	810	1			T33	24		T122	1		T12	12
values[7]	690	1			T21	27		T138	3		T129	9
values[8]	570	1			T7	1		T32	37		T122	1
values[9]	3337	1			T1	16		T5	4		T8	27
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	411	1			T3	7		T11	26		T41	1
values[1]	804	1			T3	1		T4	25		T7	1
values[2]	717	1			T25	5		T131	16		T123	25
values[3]	796	1			T5	1		T6	15		T11	25
values[4]	622	1			T6	1		T33	36		T128	3
values[5]	803	1			T122	1		T222	14		T27	3
values[6]	2994	1			T1	16		T8	27		T21	27
values[7]	605	1			T7	1		T32	37		T122	1
values[8]	1042	1			T5	4		T9	8		T76	8
values[9]	61	1			T235	14		T297	17		T296	1
minimum	17837	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	5		T41	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	14		T138	1		T132	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	12		T36	1		T130	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T7	1		T76	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T25	4		T126	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T131	5		T123	13		T157	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T33	11		T26	3		T243	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T6	1		T11	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	1		T33	6		T131	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	12		T128	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T222	14		T27	2		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	1		T225	1		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T1	16		T8	27		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T21	14		T138	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T32	20		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T129	1		T232	9		T179	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T5	1		T9	8		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T76	8		T122	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T235	5		T297	17		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T321	1		T305	10		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17513	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T124	9		T133	1		T235	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T3	2		T298	2		T262	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	12		T138	7		T132	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	13		T36	10		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T221	10		T27	4		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T25	1		T250	1		T195	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T131	11		T123	12		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T33	10		T26	1		T93	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	14		T11	13		T41	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	6		T131	9		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T33	12		T128	2		T22	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T27	1		T14	18		T273	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	3		T156	10		T257	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T203	9		T229	24		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T21	13		T138	2		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	17		T125	8		T135	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T129	7		T232	9		T251	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T5	3		T160	12		T238	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T226	7		T125	12		T238	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T235	9		T267	1		T337	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T305	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T235	10		T273	1		T196	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T126	1		T186	10		T261	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T76	8		T95	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T299	1		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T41	1		T222	7		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	14		T124	9		T132	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	5		T36	1		T130	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	1		T221	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	12		T25	4		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T7	1		T76	7		T131	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	11		T26	3		T93	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T6	1		T34	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	1		T33	6		T131	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	12		T128	1		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T95	1		T136	3		T14	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	12		T122	1		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T222	14		T27	2		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	14		T138	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T32	20		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	1		T225	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1753	1			T1	16		T5	1		T8	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	1		T226	1		T125	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T186	8		T261	14		T199	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T140	1		T257	10		T143	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T299	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T298	2		T262	10		T283	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	12		T132	4		T91	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	2		T36	10		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T221	10		T138	7		T27	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	13		T25	1		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T131	11		T123	12		T233	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	10		T26	1		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	14		T41	9		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T33	6		T131	9		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	13		T128	2		T22	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	16		T15	1		T302	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T33	12		T12	5		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T27	1		T158	9		T31	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T21	13		T138	2		T129	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T32	17		T125	8		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T129	7		T31	8		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T5	3		T203	9		T229	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T226	7		T125	12		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T3	6		T41	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	13		T138	8		T132	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	14		T36	11		T130	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T7	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T25	4		T126	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T131	12		T123	13		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T33	11		T26	3		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T6	15		T11	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T33	7		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	13		T128	3		T22	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T222	1		T27	2		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T122	1		T225	1		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T1	1		T8	3		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T21	14		T138	3		T129	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T32	18		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T129	8		T232	10		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T5	4		T9	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T76	1		T122	1		T226	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T235	10		T297	1		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T321	1		T305	3		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17670	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T124	1		T133	1		T235	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	1		T298	10		T240	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T11	13		T132	2		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	11		T130	11		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T76	6		T27	2		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T25	1		T172	2		T195	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T131	4		T123	12		T157	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T33	10		T26	1		T243	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	11		T34	15		T41	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T33	5		T131	7		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	11		T12	4		T29	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T222	13		T27	1		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	1		T156	11		T257	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T1	15		T8	24		T247	37
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	13		T220	15		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	19		T135	11		T160	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T232	8		T179	9		T303	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	7		T243	4		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T76	7		T238	13		T256	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T235	4		T297	16		T338	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T305	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T222	6		T283	7		T259	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T124	8		T235	10		T267	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T126	1		T186	9		T261	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T76	1		T95	1		T140	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T299	7		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T41	1		T222	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	13		T124	1		T132	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	6		T36	11		T130	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T221	11		T138	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	14		T25	4		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	1		T76	1		T131	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	11		T26	3		T93	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T6	15		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T33	7		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T11	14		T128	3		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T95	1		T136	1		T14	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	13		T122	1		T12	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T222	1		T27	2		T158	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T21	14		T138	3		T129	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T32	18		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	8		T225	1		T31	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T1	1		T5	4		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T122	1		T226	8		T125	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T186	9		T261	13		T199	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T76	7		T257	15		T143	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T222	6		T298	10		T240	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	13		T124	8		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T130	11		T158	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T27	2		T255	9		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	11		T25	1		T137	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T76	6		T131	4		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T33	10		T26	1		T93	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	15		T41	7		T275	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T33	5		T131	7		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	11		T27	2		T124	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T136	2		T14	12		T277	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	11		T12	4		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T222	13		T27	1		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T21	13		T220	15		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T32	19		T135	6		T235	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T31	5		T232	8		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	15		T8	24		T9	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T238	13		T256	1		T237	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11