Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23656

1

T1

16

T2

20

T3

136

auto[ADC_CTRL_FILTER_COND_OUT]

3036

1

T3

1

T4

25

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20748

1

T2

20

T3

130

T5

214

auto[1]

5944

1

T1

16

T3

7

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T11	25		T76	7		T129	9
values[0]	49	1			T128	3		T95	1		T141	1
values[1]	632	1			T3	1		T76	8		T41	17
values[2]	2948	1			T1	16		T8	27		T74	1
values[3]	691	1			T33	21		T130	23		T220	28
values[4]	732	1			T6	15		T221	11		T222	14
values[5]	702	1			T6	1		T11	26		T34	16
values[6]	695	1			T21	27		T131	16		T30	5
values[7]	632	1			T3	7		T9	8		T36	11
values[8]	800	1			T4	25		T7	1		T33	24
values[9]	917	1			T5	5		T7	1		T32	37
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T3	1		T128	3		T41	17
values[1]	3040	1			T1	16		T8	27		T74	1
values[2]	608	1			T33	21		T130	23		T220	28
values[3]	714	1			T6	16		T11	26		T221	11
values[4]	683	1			T21	27		T34	16		T41	1
values[5]	816	1			T9	8		T131	16		T28	3
values[6]	541	1			T3	7		T36	11		T122	1
values[7]	931	1			T4	25		T7	1		T32	37
values[8]	710	1			T5	5		T7	1		T11	25
values[9]	208	1			T129	9		T158	29		T132	7
minimum	17768	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T128	1		T41	8		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	1		T124	20		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1701	1			T1	16		T8	27		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T27	6		T12	7		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	11		T139	1		T91	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T130	12		T220	16		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T222	14		T224	1		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	2		T11	14		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T21	14		T34	16		T131	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T41	1		T125	1		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T135	6		T91	13		T93	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	8		T131	5		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	5		T13	4		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T36	1		T122	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T32	20		T25	4		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	12		T7	1		T33	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	2		T11	12		T76	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	1		T33	6		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T223	10		T227	1		T165	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T129	1		T158	16		T132	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17523	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T17	1		T141	2		T339	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T128	2		T41	9		T138	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T124	17		T160	9		T236	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T22	10		T203	9		T229	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T27	4		T12	5		T29	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	10		T139	15		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T130	11		T220	12		T125	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T224	8		T27	3		T230	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	14		T11	12		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T21	13		T131	9		T30	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T125	8		T28	1		T231	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T135	14		T91	15		T93	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T131	11		T28	1		T132	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	2		T13	2		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T36	10		T226	7		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T32	17		T25	1		T129	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	13		T33	12		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	3		T11	13		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T33	6		T233	9		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T227	12		T340	4		T341	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T129	8		T158	13		T132	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T17	6		T199	5		T342	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T11	12		T76	7		T225	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T129	1		T158	16		T132	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T128	1		T95	1		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T141	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T76	8		T41	8		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T124	9		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T1	16		T8	27		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	6		T12	7		T124	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T33	11		T91	1		T172	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	12		T220	16		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T222	14		T224	1		T27	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T221	1		T157	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T34	16		T131	8		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T6	1		T11	14		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	14		T30	2		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T131	5		T233	1		T235	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	5		T225	1		T135	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	8		T36	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	4		T28	1		T135	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T4	12		T7	1		T33	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T5	2		T32	20		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	1		T33	6		T26	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T11	13		T227	21		T267	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T129	8		T158	13		T132	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T128	2		T180	11		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	9		T138	7		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T160	9		T236	19		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T22	10		T203	9		T229	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T27	4		T12	5		T124	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	10		T91	1		T238	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T130	11		T220	12		T158	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T224	8		T27	3		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	14		T221	10		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T131	9		T232	1		T235	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	12		T125	8		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T21	13		T30	3		T91	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T131	11		T233	13		T235	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	2		T135	14		T140	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T36	10		T132	4		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	2		T135	12		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	13		T33	12		T226	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	3		T32	17		T25	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T33	6		T26	1		T237	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T128	3		T41	10		T138	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	1		T124	19		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T1	1		T8	3		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	8		T12	8		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T33	11		T139	16		T91	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	12		T220	13		T125	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T222	1		T224	9		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	16		T11	13		T221	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T21	14		T34	1		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T41	1		T125	9		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T135	15		T91	16		T93	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	1		T131	12		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	6		T13	5		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	11		T122	1		T226	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T32	18		T25	4		T129	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	14		T7	1		T33	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	5		T11	14		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	1		T33	7		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T223	1		T227	13		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T129	9		T158	14		T132	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17681	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T17	7		T141	2		T339	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	7		T222	6		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	18		T139	9		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T1	15		T8	24		T76	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T27	2		T12	4		T29	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T33	10		T14	12		T239	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T130	11		T220	15		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T222	13		T27	3		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	13		T157	10		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	13		T34	15		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T28	1		T234	1		T241	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T135	5		T91	12		T93	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	7		T131	4		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T13	1		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T232	8		T195	8		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T32	19		T25	1		T91	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	11		T33	11		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	11		T76	6		T243	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	5		T233	15		T275	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T223	9		T165	13		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T158	15		T132	2		T343	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T283	7		T180	11		T244	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T339	10		T199	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	14		T76	1		T225	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T129	9		T158	14		T132	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T128	3		T95	1		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T141	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T76	1		T41	10		T138	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T124	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T1	1		T8	3		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	8		T12	8		T124	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T33	11		T91	2		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T130	12		T220	13		T158	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T222	1		T224	9		T27	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	15		T221	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T34	1		T131	10		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T11	13		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T21	14		T30	5		T91	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T131	12		T233	14		T235	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	6		T225	1		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T36	11		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	5		T28	1		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	14		T7	1		T33	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T5	5		T32	18		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T33	7		T26	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T11	11		T76	6		T341	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T158	15		T132	2		T156	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T180	11		T246	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T76	7		T41	7		T222	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T124	8		T160	11		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T1	15		T8	24		T247	37
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T27	2		T12	4		T124	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	10		T172	2		T14	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T130	11		T220	15		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T222	13		T27	3		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T157	10		T240	16		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T34	15		T131	7		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T11	13		T28	2		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	13		T91	12		T93	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T131	4		T235	21		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T135	5		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T9	7		T132	1		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T135	15		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T4	11		T33	11		T233	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T32	19		T25	1		T243	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T33	5		T26	1		T275	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11