Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21278

1

T2

20

T3

137

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

5414

1

T1

16

T5

1

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20689

1

T2

20

T3

137

T5

214

auto[1]

6003

1

T1

16

T4

25

T5

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T128	3		T27	3		T225	1
values[0]	17	1			T252	16		T312	1		-	-
values[1]	521	1			T6	1		T124	28		T28	4
values[2]	786	1			T7	1		T21	27		T76	7
values[3]	616	1			T3	8		T33	21		T13	6
values[4]	704	1			T5	4		T26	4		T129	8
values[5]	719	1			T33	12		T221	11		T122	1
values[6]	627	1			T5	1		T6	15		T9	8
values[7]	880	1			T4	25		T11	25		T32	37
values[8]	631	1			T11	26		T36	11		T34	16
values[9]	3333	1			T1	16		T7	1		T8	27
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	553	1			T7	1		T124	28		T28	4
values[1]	3157	1			T1	16		T3	7		T8	27
values[2]	660	1			T3	1		T33	21		T13	6
values[3]	664	1			T5	4		T33	12		T26	4
values[4]	732	1			T25	5		T221	11		T122	1
values[5]	630	1			T5	1		T6	15		T9	8
values[6]	883	1			T4	25		T11	25		T32	37
values[7]	694	1			T7	1		T11	26		T36	11
values[8]	835	1			T128	3		T22	11		T138	3
values[9]	99	1			T27	3		T135	11		T231	4
minimum	17785	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T240	17		T149	1		T257	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	1		T124	11		T28	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	5		T21	14		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1671	1			T1	16		T8	27		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T158	16		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	11		T13	4		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	1		T33	6		T26	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T129	1		T226	1		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T122	1		T28	2		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	4		T221	1		T91	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	8		T131	13		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T6	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T4	12		T11	12		T157	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T32	20		T33	12		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T34	16		T41	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	14		T36	1		T76	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T128	1		T125	1		T225	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	1		T138	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T281	7		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T27	2		T135	7		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17532	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T6	1		T219	1		T297	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T257	10		T273	1		T188	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T124	17		T28	1		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	2		T21	13		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1093	1			T138	7		T203	9		T229	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T158	13		T232	6		T179	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	10		T13	2		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	3		T33	6		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T129	7		T226	7		T224	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T28	1		T232	9		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T25	1		T221	10		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T131	20		T123	12		T132	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	14		T135	14		T94	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	13		T11	13		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	17		T33	12		T232	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T41	9		T125	8		T140	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	12		T36	10		T27	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T128	2		T125	12		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	10		T138	2		T129	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T281	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T27	1		T135	4		T231	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T219	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T128	1		T225	1		T188	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T27	2		T134	1		T156	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T252	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T312	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T257	16		T273	1		T188	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	1		T124	11		T28	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T21	14		T122	1		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T76	7		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	6		T28	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	11		T13	4		T139	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	1		T26	3		T158	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T129	1		T130	12		T243	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T33	6		T122	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T221	1		T226	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	8		T131	13		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	1		T6	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T4	12		T11	12		T157	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T32	20		T33	12		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	16		T222	14		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	14		T36	1		T76	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	1		T41	8		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1732	1			T1	16		T8	27		T74	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T128	2		T188	6		T189	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T27	1		T156	10		T231	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T252	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T257	10		T273	1		T188	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T124	17		T28	1		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	13		T220	12		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T138	7		T235	9		T196	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	2		T232	6		T239	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	10		T13	2		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	3		T26	1		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T129	7		T130	11		T132	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T33	6		T91	15		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T221	10		T226	7		T224	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T131	20		T123	12		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	14		T25	1		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	13		T11	13		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	17		T33	12		T94	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T125	8		T140	1		T14	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	12		T36	10		T27	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T41	9		T125	12		T91	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1132	1			T22	10		T138	2		T203	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T240	1		T149	1		T257	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	1		T124	18		T28	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	6		T21	14		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1451	1			T1	1		T8	3		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T158	14		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T33	11		T13	5		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	4		T33	7		T26	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T129	8		T226	8		T224	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T122	1		T28	2		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	4		T221	11		T91	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T131	22		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T6	15		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T4	14		T11	14		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T32	18		T33	13		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T34	1		T41	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	13		T36	11		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T128	3		T125	13		T225	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T22	11		T138	3		T129	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T281	3		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T27	2		T135	5		T231	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17717	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T6	1		T219	14		T297	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T240	16		T257	15		T188	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T124	10		T28	1		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T21	13		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1313	1			T1	15		T8	24		T76	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T158	15		T172	2		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T33	10		T13	1		T277	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	5		T26	1		T91	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T130	11		T243	8		T132	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T28	1		T232	8		T262	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T25	1		T91	15		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	7		T131	11		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T135	5		T160	11		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	11		T11	11		T157	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	19		T33	11		T237	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	15		T41	7		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	13		T76	7		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T93	8		T256	2		T137	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T124	8		T29	3		T135	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T281	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T27	1		T135	6		T319	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T276	1		T252	7		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T297	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T128	3		T225	1		T188	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T27	2		T134	1		T156	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T252	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T312	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T257	11		T273	2		T188	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	1		T124	18		T28	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T21	14		T122	1		T220	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	1		T76	1		T138	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	7		T28	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T33	11		T13	5		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	4		T26	3		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T129	8		T130	12		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T33	7		T122	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T221	11		T226	8		T224	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	1		T131	22		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T6	15		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	14		T11	14		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T32	18		T33	13		T94	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	1		T222	1		T125	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	13		T36	11		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	1		T41	10		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1505	1			T1	1		T8	3		T74	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T188	12		T319	4		T344	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T27	1		T156	11		T319	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T252	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T257	15		T188	5		T276	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T124	10		T28	1		T31	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	13		T220	15		T243	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T76	6		T222	6		T235	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T172	2		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T33	10		T13	1		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T26	1		T158	15		T140	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T130	11		T243	8		T132	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	5		T91	12		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T91	15		T258	10		T275	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	7		T131	11		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T25	1		T135	5		T160	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	11		T11	11		T157	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T32	19		T33	11		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	15		T222	13		T14	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	13		T76	7		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	7		T93	8		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1359	1			T1	15		T8	24		T27	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11