Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23179

1

T1

16

T2

20

T3

137

auto[ADC_CTRL_FILTER_COND_OUT]

3513

1

T4

25

T5

5

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20897

1

T2

20

T3

136

T5

218

auto[1]

5795

1

T1

16

T3

1

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	347	1			T4	25		T76	8		T128	3
values[0]	44	1			T122	1		T136	3		T227	12
values[1]	613	1			T25	5		T22	11		T138	3
values[2]	626	1			T11	25		T131	17		T13	1
values[3]	711	1			T6	1		T7	1		T129	9
values[4]	811	1			T41	17		T157	11		T220	28
values[5]	796	1			T3	7		T5	1		T6	15
values[6]	725	1			T9	8		T32	37		T33	21
values[7]	744	1			T5	4		T7	1		T21	27
values[8]	2968	1			T1	16		T3	1		T8	27
values[9]	676	1			T41	1		T122	1		T129	8
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	676	1			T25	5		T22	11		T138	3
values[1]	655	1			T11	25		T131	17		T129	9
values[2]	697	1			T6	1		T7	1		T157	11
values[3]	869	1			T41	17		T220	28		T126	1
values[4]	716	1			T3	7		T5	1		T6	15
values[5]	665	1			T5	4		T9	8		T33	21
values[6]	3109	1			T1	16		T7	1		T8	27
values[7]	668	1			T3	1		T34	16		T26	4
values[8]	620	1			T4	25		T41	1		T122	1
values[9]	218	1			T76	8		T128	3		T221	11
minimum	17799	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	4		T138	1		T12	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T22	1		T131	5		T222	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T131	8		T132	3		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	12		T129	1		T248	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	1		T157	11		T225	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	1		T125	1		T132	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T220	16		T126	1		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T41	8		T243	5		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	5		T33	6		T76	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T6	1		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	8		T27	8		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	1		T33	11		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T1	16		T7	1		T8	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	14		T36	1		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T34	16		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T224	1		T28	1		T256	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T122	1		T27	4		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	12		T41	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T76	8		T128	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T221	1		T149	1		T239	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17539	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T123	13		T277	2		T15	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	1		T138	2		T12	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T22	10		T131	11		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T131	9		T132	4		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	13		T129	8		T250	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T237	1		T288	12		T24	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T125	12		T132	4		T29	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T220	12		T135	8		T91	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	9		T127	13		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	2		T33	6		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	14		T11	12		T32	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	5		T232	1		T188	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	3		T33	10		T226	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T33	12		T203	9		T229	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T21	13		T36	10		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T26	1		T138	7		T135	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T224	8		T256	1		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	2		T233	13		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	13		T129	7		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T128	2		T31	8		T322	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T221	10		T239	5		T255	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T123	12		T15	1		T261	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T76	8		T128	1		T31	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	12		T221	1		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T122	1		T136	3		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T320	15		T327	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	4		T138	1		T12	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	1		T131	5		T222	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T131	8		T139	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	12		T13	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	1		T132	3		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T129	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T157	11		T220	16		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T41	8		T243	5		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	5		T33	6		T76	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T6	1		T11	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	8		T27	8		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T32	20		T33	11		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T33	12		T233	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	1		T21	14		T243	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T1	16		T3	1		T8	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	1		T224	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T122	1		T27	4		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	1		T129	1		T139	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T128	2		T31	8		T292	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	13		T221	10		T137	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T227	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T327	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T25	1		T138	2		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T22	10		T131	11		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T131	9		T139	15		T179	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	13		T250	1		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	4		T30	3		T236	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T129	8		T125	12		T132	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T220	12		T135	8		T91	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	9		T127	13		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	2		T33	6		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	14		T11	12		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	5		T237	1		T188	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T32	17		T33	10		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T33	12		T233	9		T232	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	3		T21	13		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T26	1		T138	7		T203	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T36	10		T224	8		T256	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T27	2		T233	13		T135	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T129	7		T31	3		T255	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	4		T138	3		T12	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	11		T131	12		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	10		T132	5		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	14		T129	9		T248	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T157	1		T225	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	1		T125	13		T132	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T220	13		T126	1		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T41	10		T243	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	6		T33	7		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T6	15		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T27	10		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	4		T33	11		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T1	1		T7	1		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T21	14		T36	11		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T34	1		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T224	9		T28	1		T256	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T122	1		T27	4		T233	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	14		T41	1		T129	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T76	1		T128	3		T31	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T221	11		T149	1		T239	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17676	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T123	13		T277	1		T15	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	1		T12	4		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	4		T222	13		T240	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T131	7		T132	2		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	11		T195	7		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T157	10		T172	2		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T132	1		T29	3		T93	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T220	15		T135	9		T91	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	7		T243	4		T127	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	1		T33	5		T76	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	13		T32	19		T140	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	7		T27	3		T188	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T33	10		T13	1		T298	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T1	15		T8	24		T33	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T21	13		T243	8		T158	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	15		T26	1		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T256	1		T188	13		T195	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T27	2		T235	4		T276	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T4	11		T139	9		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T76	7		T31	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T239	10		T255	9		T166	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T91	12		T136	2		T258	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T123	12		T277	1		T15	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T76	1		T128	3		T31	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	14		T221	11		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T122	1		T136	1		T227	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T320	1		T327	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	4		T138	3		T12	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	11		T131	12		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T131	10		T139	16		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	14		T13	1		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T132	5		T30	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	1		T129	9		T125	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	1		T220	13		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T41	10		T243	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	6		T33	7		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T6	15		T11	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T27	10		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	18		T33	11		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T33	13		T233	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	4		T21	14		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T1	1		T3	1		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	11		T224	9		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T122	1		T27	4		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T41	1		T129	8		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T76	7		T31	5		T292	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	11		T137	4		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T136	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T320	14		T327	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T25	1		T12	4		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	4		T222	13		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T131	7		T277	12		T179	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	11		T240	16		T345	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T132	2		T172	2		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T132	1		T29	3		T93	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T157	10		T220	15		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T41	7		T243	4		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	1		T33	5		T76	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	13		T235	10		T290	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	7		T27	3		T256	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	19		T33	10		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T33	11		T233	15		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	13		T243	8		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T1	15		T8	24		T34	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T256	1		T188	13		T252	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T27	2		T135	5		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T139	9		T31	2		T160	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11