Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	13		T22	11		T27	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T6	1		T33	13		T129	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T1	1		T8	3		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	14		T25	4		T226	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	14		T122	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T21	14		T131	10		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	3		T41	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T122	1		T28	2		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T221	11		T130	12		T91	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T34	1		T129	9		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T76	1		T29	8		T238	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T32	18		T33	7		T128	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	6		T5	1		T6	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T33	11		T138	3		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T36	11		T131	12		T139	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T224	9		T125	13		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	1		T7	1		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T222	1		T27	8		T94	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	4		T76	1		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T122	1		T145	11		T249	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17641	1			T2	20		T3	129		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	13		T27	1		T124	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T33	11		T12	4		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T1	15		T8	24		T27	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	11		T25	1		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	11		T222	13		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	13		T131	7		T233	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T26	1		T31	2		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	1		T135	5		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T130	11		T257	15		T239	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T34	15		T157	10		T124	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T76	6		T29	3		T232	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T32	19		T33	5		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	1		T132	2		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T33	10		T123	12		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T131	4		T240	16		T137	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T258	10		T259	2		T241	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T9	7		T41	7		T135	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T222	6		T27	2		T160	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T76	7		T243	4		T132	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T253	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T260	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T3	13		T5	7		T10	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T242	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T28	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	13		T22	11		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	13		T129	8		T125	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T1	1		T8	3		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T4	14		T6	1		T25	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T222	1		T27	4		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T21	14		T226	8		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T26	3		T41	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T131	10		T122	1		T233	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T221	11		T130	12		T136	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T157	1		T124	18		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T76	1		T29	8		T91	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T32	18		T33	7		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	6		T5	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T33	11		T138	11		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	15		T41	10		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T224	9		T254	12		T252	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	1		T5	4		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T122	1		T222	1		T27	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17198	1			T2	20		T3	116		T5	206
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T28	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	13		T124	8		T261	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	11		T158	15		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T1	15		T8	24		T11	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	11		T25	1		T12	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T222	13		T27	2		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	13		T232	2		T262	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	1		T31	2		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T131	7		T233	15		T188	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T130	11		T136	2		T259	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T157	10		T124	10		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T76	6		T29	3		T232	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T32	19		T33	5		T34	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T132	2		T31	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	10		T123	12		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T41	7		T127	13		T256	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T252	14		T241	2		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	7		T76	7		T131	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T222	6		T27	2		T160	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11