Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23177

1

T1

16

T2

20

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3515

1

T3

7

T4

25

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20616

1

T2

20

T3

137

T5

217

auto[1]

6076

1

T1

16

T4

25

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T264	12		-	-		-	-
values[0]	52	1			T195	24		T242	25		T143	1
values[1]	569	1			T129	9		T126	1		T91	28
values[2]	776	1			T36	11		T131	16		T122	1
values[3]	673	1			T5	1		T6	1		T32	37
values[4]	634	1			T33	21		T26	4		T41	1
values[5]	3150	1			T1	16		T4	25		T8	27
values[6]	671	1			T5	4		T138	3		T27	3
values[7]	615	1			T7	1		T9	8		T11	26
values[8]	767	1			T3	8		T6	15		T33	24
values[9]	1142	1			T7	1		T21	27		T76	7
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	806	1			T36	11		T129	9		T126	1
values[1]	799	1			T32	37		T131	16		T122	1
values[2]	640	1			T5	1		T6	1		T34	16
values[3]	3008	1			T1	16		T8	27		T11	25
values[4]	773	1			T4	25		T33	12		T41	17
values[5]	573	1			T5	4		T9	8		T25	5
values[6]	795	1			T7	1		T33	24		T76	8
values[7]	667	1			T3	8		T6	15		T11	26
values[8]	784	1			T7	1		T21	27		T76	7
values[9]	216	1			T22	11		T91	20		T235	35
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T126	1		T158	16		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T36	1		T129	1		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T32	20		T30	2		T250	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T131	5		T122	1		T235	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T5	1		T6	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T34	16		T124	9		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T1	16		T8	27		T11	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T26	3		T41	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	8		T131	8		T243	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T4	12		T33	6		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T25	4		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	8		T138	1		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T33	12		T27	4		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T76	8		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T11	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	5		T6	1		T222	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	1		T76	7		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	14		T124	11		T243	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T22	1		T91	16		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T235	22		T140	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T158	13		T91	15		T232	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T36	10		T129	8		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T32	17		T30	3		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T131	11		T235	10		T14	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T231	3		T189	2		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T94	14		T14	2		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T11	13		T33	10		T203	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T26	1		T125	12		T252	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	9		T131	9		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	13		T33	6		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	3		T25	1		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	2		T12	5		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	12		T27	2		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T128	2		T138	7		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	12		T123	12		T13	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	2		T6	14		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T221	10		T31	3		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	13		T124	17		T91	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T22	10		T91	4		T140	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T235	13		T268	15		T269	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T264	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T242	12		T270	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T195	10		T143	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T126	1		T91	13		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T129	1		T232	1		T258	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T158	16		T248	1		T250	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T36	1		T131	5		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	1		T6	1		T32	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T34	16		T94	1		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T33	11		T122	1		T157	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	3		T41	1		T124	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	16		T8	27		T11	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	12		T33	6		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T27	2		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	1		T136	3		T272	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	14		T25	4		T27	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T9	8		T76	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T33	12		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	5		T6	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T7	1		T76	7		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T21	14		T124	11		T243	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T242	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T195	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T91	15		T232	6		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T129	8		T232	1		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T158	13		T250	13		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T36	10		T131	11		T235	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T32	17		T30	3		T231	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T94	14		T14	18		T273	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T33	10		T28	1		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T26	1		T255	11		T274	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T11	13		T41	9		T131	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	13		T33	6		T224	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	3		T27	1		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	2		T239	5		T186	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	12		T25	1		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	7		T130	11		T12	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	12		T125	8		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	2		T6	14		T128	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T221	10		T22	10		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T21	13		T124	17		T91	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T126	1		T158	14		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T36	11		T129	9		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T32	18		T30	5		T250	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T131	12		T122	1		T235	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T6	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	1		T124	1		T94	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T1	1		T8	3		T11	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T26	3		T41	1		T125	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	10		T131	10		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	14		T33	7		T224	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	4		T25	4		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	1		T138	3		T12	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T33	13		T27	4		T125	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T76	1		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T11	13		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	6		T6	15		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T76	1		T221	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T21	14		T124	18		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T22	11		T91	5		T140	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T235	14		T140	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T158	15		T91	12		T232	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T258	10		T235	4		T140	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T32	19		T250	14		T275	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T131	4		T235	10		T14	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T14	1		T276	2		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T34	15		T124	8		T172	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	15		T8	24		T11	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T26	1		T259	2		T228	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T41	7		T131	7		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	11		T33	5		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	1		T27	1		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	7		T12	4		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	11		T27	2		T233	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T76	7		T27	2		T220	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	13		T123	12		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T222	13		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T76	6		T222	6		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T21	13		T124	10		T243	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T91	15		T252	4		T87	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T235	21		T268	15		T269	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T242	14		T270	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T195	15		T143	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T126	1		T91	16		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T129	9		T232	2		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	14		T248	1		T250	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T36	11		T131	12		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T6	1		T32	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	1		T94	15		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T33	11		T122	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T26	3		T41	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T1	1		T8	3		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	14		T33	7		T224	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	4		T27	2		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T138	3		T136	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	13		T25	4		T27	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T9	1		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T33	13		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	6		T6	15		T128	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T7	1		T76	1		T221	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T21	14		T124	18		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T264	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T242	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T195	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T91	12		T232	2		T231	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T258	10		T235	4		T140	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T158	15		T250	14		T137	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T131	4		T235	10		T257	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T32	19		T14	1		T277	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T34	15		T172	2		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	10		T157	10		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T26	1		T124	8		T259	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	15		T8	24		T11	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	11		T33	5		T278	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	1		T132	3		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T136	2		T272	10		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	13		T25	1		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	7		T76	7		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T33	11		T233	15		T257	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	1		T222	13		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T76	6		T222	6		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T21	13		T124	10		T243	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11