Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23702

1

T1

16

T2

20

T3

129

auto[ADC_CTRL_FILTER_COND_OUT]

2990

1

T3

8

T5

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20621

1

T2

20

T3

130

T4

25

auto[1]

6071

1

T1

16

T3

7

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T279	17		T280	5		-	-
values[0]	62	1			T243	5		T281	26		T244	13
values[1]	619	1			T7	1		T9	8		T41	17
values[2]	650	1			T6	15		T11	26		T33	12
values[3]	813	1			T27	3		T124	9		T158	20
values[4]	3028	1			T1	16		T3	7		T7	1
values[5]	532	1			T36	11		T33	21		T41	1
values[6]	768	1			T3	1		T5	5		T6	1
values[7]	577	1			T4	25		T34	16		T122	2
values[8]	784	1			T21	27		T33	24		T76	15
values[9]	1206	1			T11	25		T32	37		T131	33
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T7	1		T9	8		T41	17
values[1]	732	1			T6	15		T11	26		T226	8
values[2]	794	1			T3	7		T7	1		T33	12
values[3]	3093	1			T1	16		T8	27		T36	11
values[4]	525	1			T3	1		T138	3		T129	9
values[5]	716	1			T4	25		T5	1		T6	1
values[6]	610	1			T5	4		T34	16		T76	7
values[7]	860	1			T21	27		T32	37		T33	24
values[8]	804	1			T11	25		T131	33		T222	7
values[9]	184	1			T224	9		T12	12		T158	29
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	8		T138	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	1		T41	8		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T11	14		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T135	6		T95	1		T160	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T33	6		T157	11		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	5		T7	1		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T1	16		T8	27		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	1		T41	1		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	1		T28	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	1		T138	1		T220	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T4	12		T122	1		T133	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T6	1		T222	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T34	16		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T76	7		T122	1		T14	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T21	14		T32	20		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	12		T76	8		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T11	12		T131	5		T222	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T131	8		T132	3		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T15	7		T276	5		T282	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T224	1		T12	7		T158	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T138	7		T129	7		T91	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T41	9		T94	14		T232	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	14		T11	12		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T135	14		T235	13		T257	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	6		T27	1		T158	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	2		T27	4		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1075	1			T33	10		T25	1		T203	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	10		T13	2		T235	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	8		T233	9		T239	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	2		T220	12		T31	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	13		T91	4		T232	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T27	2		T256	1		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	3		T130	11		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	16		T283	7		T255	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	13		T32	17		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	12		T128	2		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	13		T131	11		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T131	9		T132	4		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T15	1		T276	1		T282	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T224	8		T12	5		T158	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	9		T280	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T243	5		T281	12		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T244	13		T284	9		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	8		T138	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	1		T41	8		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T11	14		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T248	1		T135	6		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T27	2		T124	9		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	1		T127	14		T238	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T1	16		T8	27		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	5		T7	1		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	11		T28	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	1		T41	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T129	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T5	1		T6	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	12		T34	16		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T122	1		T243	9		T136	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T21	14		T26	3		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	12		T76	15		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T11	12		T32	20		T131	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T131	8		T224	1		T12	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T279	8		T280	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T281	14		T286	4		T287	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	7		T129	7		T91	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T41	9		T232	9		T288	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	14		T11	12		T33	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T135	14		T94	14		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T27	1		T158	9		T135	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T127	13		T238	8		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T25	1		T203	9		T229	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	2		T27	4		T13	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T33	10		T233	9		T273	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	10		T138	2		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	3		T129	8		T91	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	2		T31	8		T14	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	13		T130	11		T124	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T256	1		T137	7		T283	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	13		T26	1		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T33	12		T128	2		T221	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T11	13		T32	17		T131	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T131	9		T224	8		T12	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T9	1		T138	8		T129	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	1		T41	10		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	15		T11	13		T226	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	15		T95	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T33	7		T157	1		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	6		T7	1		T27	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T1	1		T8	3		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T36	11		T41	1		T13	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T129	9		T28	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T138	3		T220	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	14		T122	1		T133	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T6	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	4		T34	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T76	1		T122	1		T14	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T21	14		T32	18		T26	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T33	13		T76	1		T128	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	14		T131	12		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T131	10		T132	5		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T15	3		T276	5		T282	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T224	9		T12	8		T158	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	7		T243	4		T91	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T41	7		T232	8		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	13		T28	1		T135	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	5		T160	7		T235	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T33	5		T157	10		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	1		T27	2		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	15		T8	24		T33	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T235	4		T252	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T233	15		T172	2		T239	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T220	15		T31	7		T273	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	11		T91	15		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T222	13		T27	2		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	15		T130	11		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T76	6		T14	12		T283	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T21	13		T32	19		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	11		T76	7		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	11		T131	4		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	7		T132	2		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T15	5		T276	1		T289	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T12	4		T158	15		T29	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	9		T280	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T243	1		T281	15		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T244	1		T284	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T138	8		T129	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T41	10		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	15		T11	13		T33	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T248	1		T135	15		T94	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T27	2		T124	1		T158	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T133	1		T127	14		T238	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T1	1		T8	3		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	6		T7	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	11		T28	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	11		T41	1		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	4		T129	9		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T5	1		T6	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	14		T34	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T122	1		T243	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T21	14		T26	3		T125	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T33	13		T76	2		T128	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T11	14		T32	18		T131	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T131	10		T224	9		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T279	8		T280	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T243	4		T281	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T244	12		T284	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	7		T91	12		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T41	7		T232	8		T234	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	13		T33	5		T28	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T135	5		T160	7		T235	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T27	1		T124	8		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T127	13		T238	13		T250	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	15		T8	24		T25	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T27	2		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T33	10		T233	15		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T222	13		T220	15		T290	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T91	15		T160	11		T256	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	2		T31	5		T14	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	11		T34	15		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T243	8		T136	2		T256	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	13		T26	1		T275	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T33	11		T76	13		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T11	11		T32	19		T131	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T131	7		T12	4		T158	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11