Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23271

1

T1

16

T2

20

T3

136

auto[ADC_CTRL_FILTER_COND_OUT]

3421

1

T3

1

T4

25

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20533

1

T2

20

T3

116

T5

207

auto[1]

6159

1

T1

16

T3

21

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	640	1			T3	13		T5	11		T9	8
values[1]	674	1			T11	26		T33	24		T22	11
values[2]	3104	1			T1	16		T4	25		T6	1
values[3]	708	1			T11	25		T21	27		T222	14
values[4]	916	1			T26	4		T41	1		T131	17
values[5]	511	1			T221	11		T157	11		T130	23
values[6]	796	1			T32	37		T33	12		T34	16
values[7]	714	1			T3	7		T5	1		T7	1
values[8]	684	1			T6	15		T36	11		T224	9
values[9]	747	1			T3	1		T7	1		T76	8
minimum	17198	1			T2	20		T3	116		T5	206

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T6	1		T33	24		T129	8
values[1]	3043	1			T1	16		T4	25		T8	27
values[2]	752	1			T11	25		T21	27		T131	17
values[3]	865	1			T26	4		T41	1		T122	1
values[4]	597	1			T34	16		T221	11		T129	9
values[5]	766	1			T32	37		T33	12		T76	7
values[6]	634	1			T3	7		T5	1		T6	15
values[7]	768	1			T36	11		T131	16		T224	9
values[8]	604	1			T7	1		T9	8		T76	8
values[9]	146	1			T3	1		T5	4		T122	1
minimum	17809	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	1		T27	2		T124	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	12		T129	1		T12	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T1	16		T8	27		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	12		T25	4		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	12		T122	1		T222	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T21	14		T131	8		T13	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T26	3		T31	5		T136	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T41	1		T122	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T221	1		T130	12		T124	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	16		T129	1		T157	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	1		T132	3		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T32	20		T33	6		T76	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	5		T5	1		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T7	1		T33	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T36	1		T131	5		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T224	1		T95	2		T127	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	1		T76	8		T41	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	8		T222	7		T27	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T5	1		T243	5		T132	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T3	1		T122	1		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17538	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T11	14		T28	3		T15	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T27	1		T125	8		T188	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T33	12		T129	7		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T203	9		T229	24		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	13		T25	1		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	13		T256	1		T186	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	13		T131	9		T13	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	1		T31	3		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	14		T188	6		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T221	10		T130	11		T124	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T129	8		T219	13		T14	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	7		T132	4		T238	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	17		T33	6		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	2		T233	13		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	14		T33	10		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T36	10		T131	11		T125	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T224	8		T127	13		T263	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T41	9		T135	8		T94	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T27	4		T227	9		T230	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T5	3		T132	4		T91	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T250	1		T291	11		T253	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	4		T22	12		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T11	12		T28	1		T15	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	500	1			T3	13		T5	8		T10	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T9	8		T122	1		T27	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T22	1		T124	9		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	14		T33	12		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T1	16		T6	1		T8	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	12		T25	4		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	12		T222	14		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	14		T13	4		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T26	3		T122	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T41	1		T131	8		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T221	1		T130	12		T124	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T157	11		T13	1		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T138	1		T91	1		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T32	20		T33	6		T34	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	5		T5	1		T132	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T33	11		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	1		T125	1		T240	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T224	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T76	8		T41	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	1		T222	7		T95	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17041	1			T2	20		T3	112		T5	206
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T5	3		T91	15		T94	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T27	4		T242	1		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T22	10		T125	8		T188	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	12		T33	12		T129	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T203	9		T229	24		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	13		T25	1		T12	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	13		T226	7		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	13		T13	2		T232	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T26	1		T31	3		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T131	9		T233	9		T135	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T221	10		T130	11		T124	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T255	11		T292	9		T293	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	7		T91	1		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T32	17		T33	6		T128	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	2		T132	4		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T33	10		T138	2		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	10		T125	12		T235	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	14		T224	8		T127	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	9		T131	11		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T250	1		T227	9		T291	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T27	2		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T33	13		T129	8		T12	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T1	1		T8	3		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	14		T25	4		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	14		T122	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	14		T131	10		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T26	3		T31	6		T136	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T41	1		T122	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T221	11		T130	12		T124	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	1		T129	9		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T138	8		T132	5		T238	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T32	18		T33	7		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	6		T5	1		T233	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	15		T7	1		T33	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T36	11		T131	12		T125	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T224	9		T95	2		T127	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T76	1		T41	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	1		T222	1		T27	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T5	4		T243	1		T132	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T3	1		T122	1		T250	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17693	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T11	13		T28	3		T15	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T27	1		T124	8		T188	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T33	11		T12	4		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T1	15		T8	24		T27	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	11		T25	1		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	11		T222	13		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	13		T131	7		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	1		T31	2		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	5		T14	1		T188	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	11		T124	10		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T34	15		T157	10		T14	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T132	2		T232	8		T257	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T32	19		T33	5		T76	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	1		T31	5		T140	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T33	10		T123	12		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T131	4		T240	16		T137	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T127	13		T258	10		T259	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T76	7		T41	7		T135	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	7		T222	6		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T243	4		T132	1		T91	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T291	12		T253	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T244	12		T245	11		T294	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T11	13		T28	1		T15	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	532	1			T3	13		T5	11		T10	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T9	1		T122	1		T27	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T22	11		T124	1		T125	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	13		T33	13		T129	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T1	1		T6	1		T8	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	14		T25	4		T12	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	14		T222	1		T226	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	14		T13	5		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T26	3		T122	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T41	1		T131	10		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T221	11		T130	12		T124	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T157	1		T13	1		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T138	8		T91	2		T160	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T32	18		T33	7		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	6		T5	1		T132	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T7	1		T33	11		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T36	11		T125	13		T240	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	15		T224	9		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	1		T76	1		T41	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T222	1		T95	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17198	1			T2	20		T3	116		T5	206
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T243	4		T91	12		T295	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T9	7		T27	2		T280	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T124	8		T188	13		T261	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	13		T33	11		T28	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T1	15		T8	24		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	11		T25	1		T12	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	11		T222	13		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T21	13		T13	1		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	1		T31	2		T256	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T131	7		T233	15		T135	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	11		T124	10		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T157	10		T14	1		T255	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T160	11		T232	8		T257	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T32	19		T33	5		T34	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	1		T132	2		T31	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T33	10		T123	12		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T240	16		T137	8		T235	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T127	13		T256	1		T252	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T76	7		T41	7		T131	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T222	6		T160	7		T172	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11