Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21258

1

T2

20

T3

137

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

5434

1

T1

16

T5

1

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20690

1

T2

20

T3

137

T5

214

auto[1]

6002

1

T1

16

T4

25

T5

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T306	2		-	-		-	-
values[0]	37	1			T6	1		T188	10		T307	1
values[1]	528	1			T124	28		T243	5		T31	17
values[2]	760	1			T7	1		T21	27		T138	8
values[3]	613	1			T3	8		T33	21		T76	7
values[4]	713	1			T5	4		T26	4		T129	8
values[5]	713	1			T33	12		T221	11		T122	2
values[6]	662	1			T5	1		T6	15		T9	8
values[7]	823	1			T4	25		T11	25		T32	37
values[8]	649	1			T7	1		T11	26		T36	11
values[9]	3561	1			T1	16		T8	27		T74	1
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	690	1			T6	1		T7	1		T124	28
values[1]	3196	1			T1	16		T3	7		T8	27
values[2]	600	1			T3	1		T33	21		T13	6
values[3]	743	1			T5	4		T33	12		T26	4
values[4]	685	1			T221	11		T122	1		T129	8
values[5]	670	1			T5	1		T6	15		T9	8
values[6]	834	1			T4	25		T11	25		T32	37
values[7]	678	1			T7	1		T11	26		T36	11
values[8]	794	1			T128	3		T22	11		T138	3
values[9]	169	1			T129	9		T27	3		T135	11
minimum	17633	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T240	17		T149	1		T257	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	1		T7	1		T124	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	5		T21	14		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1676	1			T1	16		T8	27		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T158	16		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	11		T13	4		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T5	1		T33	6		T26	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T226	1		T224	1		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T122	1		T126	1		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T221	1		T129	1		T91	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	8		T131	13		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	1		T6	1		T25	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T4	12		T11	12		T157	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T32	20		T33	12		T27	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	1		T34	16		T222	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	14		T36	1		T76	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T128	1		T125	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T22	1		T138	1		T124	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T281	7		T308	6		T284	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T129	1		T27	2		T135	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T309	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T257	10		T273	1		T188	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T124	17		T28	1		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	2		T21	13		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1094	1			T138	7		T203	9		T229	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T158	13		T179	6		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	10		T13	2		T250	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	3		T33	6		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T226	7		T224	8		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	1		T232	9		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T221	10		T129	7		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T131	20		T123	12		T132	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	14		T25	1		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	13		T11	13		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T32	17		T33	12		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T125	8		T140	1		T14	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	12		T36	10		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T128	2		T125	12		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	10		T138	2		T29	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T281	2		T308	5		T310	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T129	8		T27	1		T135	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T309	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T188	6		T18	5		T311	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T6	1		T307	1		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T243	5		T257	16		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T124	11		T31	9		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T21	14		T122	1		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T138	1		T222	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	6		T28	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	11		T76	7		T13	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	1		T26	3		T158	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T129	1		T130	12		T243	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	6		T122	2		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T221	1		T226	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	8		T131	13		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	1		T6	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	12		T11	12		T157	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T32	20		T33	12		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	1		T34	16		T222	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	14		T36	1		T76	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T128	1		T125	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1805	1			T1	16		T8	27		T74	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T188	4		T18	2		T311	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T257	10		T273	1		T276	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T124	17		T31	8		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	13		T220	12		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	7		T28	1		T235	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	2		T232	6		T239	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	10		T13	2		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	3		T26	1		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T129	7		T130	11		T257	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T33	6		T91	15		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T221	10		T226	7		T224	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T131	20		T123	12		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	14		T25	1		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	13		T11	13		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	17		T33	12		T94	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T125	8		T158	9		T14	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	12		T36	10		T27	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T128	2		T125	12		T91	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1187	1			T22	10		T41	9		T138	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T240	1		T149	1		T257	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T7	1		T124	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	6		T21	14		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1452	1			T1	1		T8	3		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T158	14		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	11		T13	5		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	4		T33	7		T26	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T226	8		T224	9		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T122	1		T126	1		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T221	11		T129	8		T91	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T131	22		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T6	15		T25	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T4	14		T11	14		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	18		T33	13		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T34	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	13		T36	11		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T128	3		T125	13		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	11		T138	3		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T281	3		T308	6		T284	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T129	9		T27	2		T135	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T309	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T240	16		T257	15		T188	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T124	10		T28	1		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T21	13		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1318	1			T1	15		T8	24		T76	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T158	15		T172	2		T179	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	10		T13	1		T277	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T33	5		T26	1		T91	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T130	11		T243	8		T132	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T28	1		T232	8		T262	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T91	15		T160	11		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	7		T131	11		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T25	1		T135	5		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	11		T11	11		T157	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	19		T33	11		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T34	15		T222	13		T195	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	13		T76	7		T41	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T93	8		T256	2		T137	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T124	8		T29	3		T135	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T281	6		T308	5		T284	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T27	1		T135	6		T156	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T306	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T188	5		T18	6		T311	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T6	1		T307	1		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T243	1		T257	11		T273	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T124	18		T31	12		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T21	14		T122	1		T220	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	1		T138	8		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	7		T28	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T33	11		T76	1		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	4		T26	3		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T129	8		T130	12		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T33	7		T122	2		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T221	11		T226	8		T224	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	1		T131	22		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	1		T6	15		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	14		T11	14		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T32	18		T33	13		T94	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T34	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	13		T36	11		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T128	3		T125	13		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1571	1			T1	1		T8	3		T74	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T188	5		T18	1		T311	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T243	4		T257	15		T276	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T124	10		T31	5		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	13		T220	15		T240	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T222	6		T28	1		T235	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T172	2		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	10		T76	6		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	1		T158	15		T140	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T130	11		T243	8		T257	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T33	5		T91	12		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	1		T91	15		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	7		T131	11		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T25	1		T135	5		T160	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	11		T11	11		T157	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T32	19		T33	11		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	15		T222	13		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	13		T76	7		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T93	8		T256	2		T137	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1421	1			T1	15		T8	24		T41	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11