Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23341

1

T1

16

T2

20

T3

137

auto[ADC_CTRL_FILTER_COND_OUT]

3351

1

T5

5

T6

16

T11

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20578

1

T2

20

T3

130

T4

25

auto[1]

6114

1

T1

16

T3

7

T5

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T224	9		-	-		-	-
values[0]	14	1			T232	2		T227	10		T313	1
values[1]	738	1			T7	1		T11	26		T33	12
values[2]	687	1			T122	1		T226	8		T124	37
values[3]	673	1			T6	15		T11	25		T36	11
values[4]	428	1			T3	1		T129	8		T28	4
values[5]	2955	1			T1	16		T6	1		T8	27
values[6]	675	1			T5	4		T33	24		T128	3
values[7]	641	1			T4	25		T5	1		T33	21
values[8]	740	1			T3	7		T7	1		T32	37
values[9]	1501	1			T9	8		T21	27		T34	16
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	869	1			T7	1		T33	12		T122	1
values[1]	634	1			T11	51		T36	11		T26	4
values[2]	716	1			T6	15		T122	2		T129	8
values[3]	2855	1			T1	16		T3	1		T8	27
values[4]	553	1			T76	7		T131	17		T123	25
values[5]	684	1			T4	25		T6	1		T33	24
values[6]	552	1			T5	5		T33	21		T76	8
values[7]	936	1			T3	7		T7	1		T32	37
values[8]	1033	1			T21	27		T41	17		T224	9
values[9]	193	1			T9	8		T27	6		T126	1
minimum	17667	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	1		T122	1		T27	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T33	6		T124	9		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	14		T36	1		T26	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	12		T162	1		T255	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T122	1		T129	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T122	1		T157	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T1	16		T3	1		T8	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T225	1		T172	3		T314	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T131	8		T123	13		T243	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T76	7		T28	3		T139	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	12		T33	12		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T138	2		T222	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T22	1		T41	1		T222	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	2		T33	11		T76	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	5		T7	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T32	20		T34	16		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T224	1		T13	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T21	14		T41	8		T158	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T9	8		T27	4		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T126	1		T240	17		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T315	1		T316	1		T287	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	4		T232	1		T14	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T33	6		T125	12		T219	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	12		T36	10		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	13		T255	11		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T129	7		T125	8		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	14		T27	1		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T203	9		T229	24		T317	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T314	1		T180	11		T199	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T131	9		T123	12		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	1		T91	1		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	13		T33	12		T128	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	9		T12	5		T94	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T22	10		T28	1		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	3		T33	10		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	2		T25	1		T135	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T32	17		T130	11		T238	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T224	8		T30	3		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T21	13		T41	9		T158	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T27	2		T31	8		T160	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T318	11		T200	8		T146	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T315	12		T316	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T224	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T232	1		T205	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T227	1		T313	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T11	14		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	6		T265	1		T275	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T122	1		T226	1		T124	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T124	9		T125	1		T140	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T36	1		T26	3		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T11	12		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	1		T129	1		T127	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T28	3		T225	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T1	16		T8	27		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	1		T76	7		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T33	12		T128	1		T131	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T138	2		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	12		T220	16		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T33	11		T76	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	5		T7	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T32	20		T221	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	406	1			T9	8		T27	4		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T21	14		T34	16		T41	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T224	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T232	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T227	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	12		T27	4		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T33	6		T219	13		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T226	7		T124	17		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T125	12		T140	14		T288	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T36	10		T26	1		T125	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	14		T11	13		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	7		T127	13		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T28	1		T314	1		T242	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T131	11		T203	9		T229	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T256	1		T16	5		T199	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T33	12		T128	2		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	3		T138	9		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	13		T220	12		T13	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	10		T94	14		T239	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T25	1		T22	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	17		T221	10		T129	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T27	2		T30	3		T233	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T21	13		T41	9		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T122	1		T27	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T33	7		T124	1		T125	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	13		T36	11		T26	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	14		T162	1		T255	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T122	1		T129	8		T125	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	15		T122	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T1	1		T3	1		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T225	1		T172	1		T314	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	10		T123	13		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T76	1		T28	3		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	14		T33	13		T128	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T138	11		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T22	11		T41	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	5		T33	11		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	6		T7	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T32	18		T34	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T224	9		T13	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T21	14		T41	10		T158	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T9	1		T27	4		T31	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T126	1		T240	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T315	13		T316	12		T287	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T27	2		T237	1		T319	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T33	5		T124	8		T275	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	13		T26	1		T124	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	11		T255	9		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T238	13		T262	5		T278	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T157	10		T27	1		T250	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	15		T8	24		T247	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T172	2		T268	11		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T131	7		T123	12		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T76	6		T28	1		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	11		T33	11		T131	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T222	13		T12	4		T237	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T222	6		T28	1		T14	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	10		T76	7		T29	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T25	1		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T32	19		T34	15		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T233	15		T91	15		T93	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T21	13		T41	7		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T9	7		T27	2		T31	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T240	16		T320	14		T200	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T287	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T224	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T232	2		T205	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	10		T313	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T11	13		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T33	7		T265	1		T275	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T122	1		T226	8		T124	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	1		T125	13		T140	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	11		T26	3		T125	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	15		T11	14		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T129	8		T127	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T28	3		T225	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T1	1		T8	3		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T76	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	13		T128	3		T131	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	4		T138	11		T12	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	14		T220	13		T13	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T33	11		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	6		T7	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T32	18		T221	11		T129	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T9	1		T27	4		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T21	14		T34	1		T41	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	13		T27	2		T237	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T33	5		T275	9		T235	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T124	10		T136	2		T137	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T124	8		T140	17		T255	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T26	1		T238	13		T237	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	11		T157	10		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T127	13		T262	5		T188	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T28	1		T172	2		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T1	15		T8	24		T131	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T76	6		T256	1		T272	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T33	11		T131	7		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	4		T139	9		T135	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	11		T220	15		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T33	10		T76	7		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T25	1		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	19		T243	4		T29	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T9	7		T27	2		T233	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T21	13		T34	15		T41	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11