Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26692

1

T1

16

T2

20

T3

137

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23378

1

T1

16

T2

20

T3

137

auto[ADC_CTRL_FILTER_COND_OUT]

3314

1

T5

5

T6

16

T11

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20578

1

T2

20

T3

130

T4

25

auto[1]

6114

1

T1

16

T3

7

T5

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22587

1

T1

16

T2

20

T3

131

auto[1]

4105

1

T3

6

T4

13

T5

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	366	1			T9	8		T21	27		T224	9
values[0]	10	1			T227	10		-	-		-	-
values[1]	747	1			T7	1		T33	12		T122	1
values[2]	699	1			T11	26		T36	11		T226	8
values[3]	619	1			T6	15		T11	25		T26	4
values[4]	476	1			T3	1		T129	8		T28	4
values[5]	2954	1			T1	16		T6	1		T8	27
values[6]	660	1			T5	4		T33	24		T128	3
values[7]	607	1			T4	25		T5	1		T33	21
values[8]	808	1			T3	7		T7	1		T34	16
values[9]	1115	1			T32	37		T41	17		T130	23
minimum	17631	1			T2	20		T3	129		T5	213

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	720	1			T33	12		T122	1		T27	10
values[1]	625	1			T11	51		T36	11		T26	4
values[2]	659	1			T6	15		T122	1		T129	8
values[3]	2884	1			T1	16		T3	1		T8	27
values[4]	597	1			T6	1		T76	7		T131	33
values[5]	602	1			T5	4		T33	24		T128	3
values[6]	633	1			T4	25		T5	1		T33	21
values[7]	851	1			T3	7		T7	1		T32	37
values[8]	1084	1			T9	8		T21	27		T41	17
values[9]	203	1			T27	6		T31	17		T93	19
minimum	17834	1			T2	20		T3	129		T5	213

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

4054

1

T1

15

T3

1

T4

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T122	1		T27	6		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T33	6		T124	9		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	14		T36	1		T26	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	12		T122	1		T237	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T122	1		T129	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T157	11		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T1	16		T3	1		T8	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T225	1		T172	3		T272	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	13		T123	13		T243	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	1		T76	7		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	12		T128	1		T220	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T138	2		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	12		T22	1		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T33	11		T76	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	5		T7	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T32	20		T34	16		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T9	8		T224	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T21	14		T41	8		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T27	4		T31	9		T93	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T240	17		T318	1		T321	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17504	1			T2	20		T3	125		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T219	1		T227	1		T322	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T27	4		T232	1		T17	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T33	6		T125	12		T235	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	12		T36	10		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	13		T237	1		T255	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	7		T127	13		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	14		T27	1		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T203	9		T229	24		T125	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T314	1		T242	13		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	20		T123	12		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	1		T91	1		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T33	12		T128	2		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	3		T138	9		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	13		T22	10		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	10		T221	10		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	2		T25	1		T135	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	17		T130	11		T238	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T224	8		T30	3		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T21	13		T41	9		T158	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T27	2		T31	8		T93	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T318	11		T321	12		T200	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	4		T22	2		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T219	13		T227	9		T322	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T9	8		T224	1		T27	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T21	14		T126	1		T235	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T227	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T122	1		T27	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T33	6		T265	1		T275	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	14		T36	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T124	9		T125	1		T140	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	3		T122	1		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T11	12		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T129	1		T127	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T28	3		T225	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T1	16		T8	27		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	1		T76	7		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T33	12		T128	1		T131	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T138	2		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	12		T220	16		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T33	11		T76	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	5		T7	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T34	16		T221	1		T243	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T13	1		T133	1		T30	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T32	20		T41	8		T130	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T3	125		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T224	8		T27	2		T233	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T21	13		T235	10		T323	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T227	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	4		T232	1		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T33	6		T219	13		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	12		T36	10		T226	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T125	12		T140	14		T288	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	1		T125	8		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	14		T11	13		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	7		T127	13		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T28	1		T314	1		T242	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T131	11		T203	9		T229	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T256	1		T16	5		T199	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T33	12		T128	2		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	3		T138	9		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	13		T220	12		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	10		T129	8		T94	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	2		T25	1		T22	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T221	10		T29	5		T238	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T30	3		T135	4		T31	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T32	17		T41	9		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T22	2		T26	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T122	1		T27	8		T232	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T33	7		T124	1		T125	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	13		T36	11		T26	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	14		T122	1		T237	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T122	1		T129	8		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	15		T157	1		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T1	1		T3	1		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T225	1		T172	1		T272	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T131	22		T123	13		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T76	1		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	13		T128	3		T220	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	4		T138	11		T12	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	14		T22	11		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T33	11		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	6		T7	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T32	18		T34	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T9	1		T224	9		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T21	14		T41	10		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T27	4		T31	12		T93	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T240	1		T318	12		T321	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17683	1			T2	20		T3	129		T5	213
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T219	14		T227	10		T322	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T27	2		T319	9		T293	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T33	5		T124	8		T275	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	13		T26	1		T124	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	11		T237	1		T255	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T127	13		T238	13		T262	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T157	10		T27	1		T250	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T1	15		T8	24		T247	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T172	2		T272	10		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T131	11		T123	12		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T76	6		T28	1		T256	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T33	11		T220	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	4		T139	9		T237	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	11		T222	6		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T33	10		T76	7		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T25	1		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T32	19		T34	15		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	7		T233	15		T91	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T21	13		T41	7		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T27	2		T31	5		T93	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T240	16		T321	10		T320	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T237	1		T213	15		T324	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T241	8		T279	7		T289	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T9	1		T224	9		T27	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	14		T126	1		T235	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T227	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	1		T122	1		T27	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T33	7		T265	1		T275	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	13		T36	11		T226	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T124	1		T125	13		T140	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	3		T122	1		T125	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	15		T11	14		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T129	8		T127	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T28	3		T225	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T1	1		T8	3		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	1		T76	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	13		T128	3		T131	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	4		T138	11		T12	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	14		T220	13		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	1		T33	11		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	6		T7	1		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	1		T221	11		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T13	1		T133	1		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T32	18		T41	10		T130	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17631	1			T2	20		T3	129		T5	213
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T9	7		T27	2		T233	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T21	13		T235	10		T259	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T27	2		T237	1		T293	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	5		T275	9		T235	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	13		T124	10		T136	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T124	8		T140	17		T255	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	1		T238	13		T278	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	11		T157	10		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	13		T262	5		T188	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T28	1		T172	2		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	15		T8	24		T131	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T76	6		T256	1		T272	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T33	11		T131	7		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	4		T139	9		T135	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	11		T220	15		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	10		T76	7		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T25	1		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T34	15		T243	4		T29	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T135	6		T31	5		T91	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T32	19		T41	7		T130	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22638

1

T1

1

T2

20

T3

136

auto[1]

auto[0]

4054

1

T1

15

T3

1

T4

11