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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 99.07 96.67 100.00 100.00 98.83 98.33 90.37


Total test records in report: 918
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T799 /workspace/coverage/default/10.adc_ctrl_smoke.2877697904 May 14 03:00:39 PM PDT 24 May 14 03:00:45 PM PDT 24 6004134802 ps
T800 /workspace/coverage/default/25.adc_ctrl_poweron_counter.1084802082 May 14 03:04:18 PM PDT 24 May 14 03:04:25 PM PDT 24 3198490143 ps
T311 /workspace/coverage/default/23.adc_ctrl_filters_both.3503377379 May 14 03:03:45 PM PDT 24 May 14 03:04:33 PM PDT 24 178534256050 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1689413410 May 14 01:21:29 PM PDT 24 May 14 01:21:31 PM PDT 24 465318861 ps
T38 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3757378017 May 14 01:21:40 PM PDT 24 May 14 01:22:28 PM PDT 24 27106445534 ps
T39 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3269352248 May 14 01:22:13 PM PDT 24 May 14 01:22:21 PM PDT 24 4513844637 ps
T46 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3708243002 May 14 01:22:15 PM PDT 24 May 14 01:22:19 PM PDT 24 606281935 ps
T47 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.686320268 May 14 01:22:17 PM PDT 24 May 14 01:22:20 PM PDT 24 404831186 ps
T801 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.310048408 May 14 01:22:34 PM PDT 24 May 14 01:22:37 PM PDT 24 461183214 ps
T40 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1271432438 May 14 01:21:57 PM PDT 24 May 14 01:22:15 PM PDT 24 4937050201 ps
T802 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.639101012 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 339403076 ps
T803 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2293945563 May 14 01:22:33 PM PDT 24 May 14 01:22:37 PM PDT 24 446614917 ps
T804 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3443708218 May 14 01:22:16 PM PDT 24 May 14 01:22:19 PM PDT 24 483733728 ps
T805 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1714403582 May 14 01:22:16 PM PDT 24 May 14 01:22:20 PM PDT 24 295587447 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3410447614 May 14 01:21:25 PM PDT 24 May 14 01:21:36 PM PDT 24 4478666030 ps
T806 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1276144175 May 14 01:22:32 PM PDT 24 May 14 01:22:34 PM PDT 24 508954513 ps
T100 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.213383553 May 14 01:21:29 PM PDT 24 May 14 01:21:33 PM PDT 24 1199091618 ps
T42 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3257319335 May 14 01:22:14 PM PDT 24 May 14 01:22:28 PM PDT 24 4198031308 ps
T807 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2321635938 May 14 01:21:57 PM PDT 24 May 14 01:22:00 PM PDT 24 417975799 ps
T101 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1222653805 May 14 01:21:31 PM PDT 24 May 14 01:21:35 PM PDT 24 509902904 ps
T43 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2403225189 May 14 01:22:15 PM PDT 24 May 14 01:22:24 PM PDT 24 4485677134 ps
T52 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1875041318 May 14 01:22:13 PM PDT 24 May 14 01:22:16 PM PDT 24 546183832 ps
T808 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4173069319 May 14 01:22:16 PM PDT 24 May 14 01:22:20 PM PDT 24 480287542 ps
T809 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3344749024 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 285989039 ps
T63 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4074126683 May 14 01:21:29 PM PDT 24 May 14 01:21:32 PM PDT 24 429849471 ps
T62 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1308506800 May 14 01:21:58 PM PDT 24 May 14 01:22:00 PM PDT 24 419219088 ps
T102 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3921897860 May 14 01:21:41 PM PDT 24 May 14 01:21:44 PM PDT 24 447136701 ps
T116 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3899652784 May 14 01:22:16 PM PDT 24 May 14 01:22:31 PM PDT 24 4518200560 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.266969345 May 14 01:21:31 PM PDT 24 May 14 01:21:33 PM PDT 24 537995236 ps
T65 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1206427860 May 14 01:21:41 PM PDT 24 May 14 01:21:43 PM PDT 24 613688924 ps
T60 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1413266180 May 14 01:22:13 PM PDT 24 May 14 01:22:15 PM PDT 24 547243869 ps
T53 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.361979659 May 14 01:22:19 PM PDT 24 May 14 01:22:22 PM PDT 24 818879011 ps
T810 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3298577345 May 14 01:22:33 PM PDT 24 May 14 01:22:35 PM PDT 24 328644524 ps
T44 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3041304453 May 14 01:21:22 PM PDT 24 May 14 01:21:27 PM PDT 24 4697534798 ps
T811 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.409772114 May 14 01:22:17 PM PDT 24 May 14 01:22:21 PM PDT 24 502610177 ps
T64 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2835039659 May 14 01:21:34 PM PDT 24 May 14 01:21:36 PM PDT 24 598620456 ps
T812 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3150792274 May 14 01:22:33 PM PDT 24 May 14 01:22:37 PM PDT 24 531837294 ps
T813 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3930955864 May 14 01:22:18 PM PDT 24 May 14 01:22:22 PM PDT 24 497663047 ps
T103 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2899642611 May 14 01:21:55 PM PDT 24 May 14 01:21:57 PM PDT 24 365432273 ps
T814 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3451703806 May 14 01:22:33 PM PDT 24 May 14 01:22:37 PM PDT 24 441313597 ps
T815 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2798106300 May 14 01:22:35 PM PDT 24 May 14 01:22:40 PM PDT 24 443023152 ps
T104 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2720222808 May 14 01:21:29 PM PDT 24 May 14 01:21:33 PM PDT 24 1034794372 ps
T816 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2725318504 May 14 01:21:59 PM PDT 24 May 14 01:22:02 PM PDT 24 678959181 ps
T105 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3614182919 May 14 01:22:13 PM PDT 24 May 14 01:22:15 PM PDT 24 399205510 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3902277307 May 14 01:21:23 PM PDT 24 May 14 01:21:26 PM PDT 24 448367852 ps
T817 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3650463122 May 14 01:21:23 PM PDT 24 May 14 01:21:25 PM PDT 24 342776589 ps
T118 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2653020400 May 14 01:21:57 PM PDT 24 May 14 01:21:59 PM PDT 24 596559320 ps
T68 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2035614049 May 14 01:21:58 PM PDT 24 May 14 01:22:01 PM PDT 24 509453659 ps
T119 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.384019591 May 14 01:22:13 PM PDT 24 May 14 01:22:14 PM PDT 24 372209409 ps
T818 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1308732963 May 14 01:22:13 PM PDT 24 May 14 01:22:16 PM PDT 24 484067867 ps
T819 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1833836707 May 14 01:22:34 PM PDT 24 May 14 01:22:37 PM PDT 24 350464296 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2899919653 May 14 01:21:24 PM PDT 24 May 14 01:21:28 PM PDT 24 725120371 ps
T820 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1321059802 May 14 01:22:33 PM PDT 24 May 14 01:22:35 PM PDT 24 471939557 ps
T55 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2019244148 May 14 01:21:59 PM PDT 24 May 14 01:22:03 PM PDT 24 555648494 ps
T821 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2751644315 May 14 01:22:16 PM PDT 24 May 14 01:22:36 PM PDT 24 4336416881 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4040520922 May 14 01:21:34 PM PDT 24 May 14 01:21:37 PM PDT 24 519094306 ps
T107 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2917985123 May 14 01:21:59 PM PDT 24 May 14 01:22:00 PM PDT 24 729768108 ps
T823 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1616618133 May 14 01:21:57 PM PDT 24 May 14 01:21:59 PM PDT 24 477942709 ps
T108 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3617063014 May 14 01:21:33 PM PDT 24 May 14 01:22:13 PM PDT 24 50987887546 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1967483702 May 14 01:21:58 PM PDT 24 May 14 01:22:00 PM PDT 24 472298332 ps
T48 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.954649827 May 14 01:21:59 PM PDT 24 May 14 01:22:06 PM PDT 24 4027269066 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3343752242 May 14 01:22:15 PM PDT 24 May 14 01:22:19 PM PDT 24 414677660 ps
T826 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.163966119 May 14 01:21:41 PM PDT 24 May 14 01:21:45 PM PDT 24 493152798 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.787542702 May 14 01:21:57 PM PDT 24 May 14 01:21:59 PM PDT 24 305048809 ps
T828 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1561010805 May 14 01:22:23 PM PDT 24 May 14 01:22:25 PM PDT 24 481770825 ps
T829 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2950065555 May 14 01:22:35 PM PDT 24 May 14 01:22:39 PM PDT 24 556138663 ps
T54 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2476656873 May 14 01:21:23 PM PDT 24 May 14 01:21:27 PM PDT 24 564332399 ps
T69 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.189856029 May 14 01:22:17 PM PDT 24 May 14 01:22:23 PM PDT 24 4418839285 ps
T109 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4145670203 May 14 01:21:30 PM PDT 24 May 14 01:21:36 PM PDT 24 1167379556 ps
T830 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1954189177 May 14 01:22:34 PM PDT 24 May 14 01:22:38 PM PDT 24 500624601 ps
T831 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4256320546 May 14 01:21:42 PM PDT 24 May 14 01:21:49 PM PDT 24 3853881552 ps
T832 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3615263373 May 14 01:21:34 PM PDT 24 May 14 01:21:37 PM PDT 24 421187435 ps
T61 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2987020028 May 14 01:22:16 PM PDT 24 May 14 01:22:26 PM PDT 24 9450746719 ps
T59 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1443652357 May 14 01:21:56 PM PDT 24 May 14 01:22:03 PM PDT 24 8887769992 ps
T833 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1157780961 May 14 01:21:41 PM PDT 24 May 14 01:21:55 PM PDT 24 4325758485 ps
T834 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1771346946 May 14 01:22:15 PM PDT 24 May 14 01:22:23 PM PDT 24 8594462082 ps
T835 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1601483742 May 14 01:22:33 PM PDT 24 May 14 01:22:37 PM PDT 24 292025886 ps
T836 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.556231990 May 14 01:22:32 PM PDT 24 May 14 01:22:35 PM PDT 24 333865700 ps
T837 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2754202919 May 14 01:22:18 PM PDT 24 May 14 01:22:20 PM PDT 24 468236653 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1209394401 May 14 01:22:14 PM PDT 24 May 14 01:22:17 PM PDT 24 376049672 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3102633311 May 14 01:21:40 PM PDT 24 May 14 01:21:43 PM PDT 24 591818726 ps
T840 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4162836840 May 14 01:21:57 PM PDT 24 May 14 01:22:00 PM PDT 24 526690059 ps
T110 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3498535827 May 14 01:21:56 PM PDT 24 May 14 01:21:57 PM PDT 24 542682115 ps
T841 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1148619630 May 14 01:21:30 PM PDT 24 May 14 01:21:38 PM PDT 24 4414872783 ps
T842 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4177861221 May 14 01:21:42 PM PDT 24 May 14 01:21:45 PM PDT 24 467865877 ps
T843 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3876419017 May 14 01:22:15 PM PDT 24 May 14 01:22:20 PM PDT 24 2439146600 ps
T66 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2096316372 May 14 01:21:25 PM PDT 24 May 14 01:21:29 PM PDT 24 541446199 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3835518616 May 14 01:21:24 PM PDT 24 May 14 01:21:28 PM PDT 24 765182731 ps
T67 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.121096817 May 14 01:21:56 PM PDT 24 May 14 01:22:03 PM PDT 24 4222422213 ps
T844 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.111223049 May 14 01:21:34 PM PDT 24 May 14 01:21:37 PM PDT 24 787282580 ps
T845 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.567116807 May 14 01:22:14 PM PDT 24 May 14 01:22:18 PM PDT 24 390376915 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3618889241 May 14 01:21:23 PM PDT 24 May 14 01:21:31 PM PDT 24 4733608881 ps
T847 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3030912893 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 464326550 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3879415690 May 14 01:21:31 PM PDT 24 May 14 01:22:45 PM PDT 24 17121439041 ps
T848 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3258367052 May 14 01:21:57 PM PDT 24 May 14 01:22:09 PM PDT 24 4690919441 ps
T849 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1814220019 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 574962747 ps
T850 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2658266192 May 14 01:21:34 PM PDT 24 May 14 01:21:39 PM PDT 24 4730038484 ps
T851 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2275405370 May 14 01:22:14 PM PDT 24 May 14 01:22:20 PM PDT 24 1928959268 ps
T852 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3176178125 May 14 01:21:31 PM PDT 24 May 14 01:21:41 PM PDT 24 3923986677 ps
T853 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1134049755 May 14 01:22:14 PM PDT 24 May 14 01:22:21 PM PDT 24 2446400513 ps
T854 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2201446262 May 14 01:22:16 PM PDT 24 May 14 01:22:19 PM PDT 24 465850344 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1874430627 May 14 01:21:26 PM PDT 24 May 14 01:21:28 PM PDT 24 503251710 ps
T856 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1747770558 May 14 01:22:14 PM PDT 24 May 14 01:22:17 PM PDT 24 414149347 ps
T857 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.114087085 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 505814174 ps
T113 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1011986068 May 14 01:22:16 PM PDT 24 May 14 01:22:20 PM PDT 24 527202582 ps
T858 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4259954252 May 14 01:22:19 PM PDT 24 May 14 01:22:22 PM PDT 24 400014174 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2216309186 May 14 01:22:15 PM PDT 24 May 14 01:22:21 PM PDT 24 3037442494 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.862190019 May 14 01:21:33 PM PDT 24 May 14 01:21:45 PM PDT 24 4214435692 ps
T70 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2901696855 May 14 01:21:33 PM PDT 24 May 14 01:21:42 PM PDT 24 8354590897 ps
T861 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1412818733 May 14 01:22:16 PM PDT 24 May 14 01:22:19 PM PDT 24 309651553 ps
T71 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.321390995 May 14 01:22:15 PM PDT 24 May 14 01:22:26 PM PDT 24 8575020686 ps
T862 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3960762420 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 451512054 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3605010030 May 14 01:22:13 PM PDT 24 May 14 01:22:16 PM PDT 24 448662995 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1201558434 May 14 01:21:33 PM PDT 24 May 14 01:21:35 PM PDT 24 405751792 ps
T865 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2562137175 May 14 01:22:14 PM PDT 24 May 14 01:22:29 PM PDT 24 4985372669 ps
T866 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1114150823 May 14 01:22:16 PM PDT 24 May 14 01:22:19 PM PDT 24 453279603 ps
T867 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2295227760 May 14 01:21:30 PM PDT 24 May 14 01:21:35 PM PDT 24 1095112143 ps
T868 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1536494484 May 14 01:22:16 PM PDT 24 May 14 01:22:20 PM PDT 24 585952152 ps
T869 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2129670400 May 14 01:21:58 PM PDT 24 May 14 01:22:01 PM PDT 24 390294783 ps
T870 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3643593544 May 14 01:22:33 PM PDT 24 May 14 01:22:36 PM PDT 24 492033355 ps
T871 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3868731194 May 14 01:21:57 PM PDT 24 May 14 01:22:14 PM PDT 24 4610933307 ps
T872 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1629991590 May 14 01:22:15 PM PDT 24 May 14 01:22:18 PM PDT 24 538486208 ps
T873 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3074007150 May 14 01:21:41 PM PDT 24 May 14 01:21:44 PM PDT 24 728404845 ps
T874 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.84400699 May 14 01:21:57 PM PDT 24 May 14 01:21:59 PM PDT 24 520256669 ps
T875 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3284536440 May 14 01:22:35 PM PDT 24 May 14 01:22:40 PM PDT 24 451832757 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2314613806 May 14 01:21:40 PM PDT 24 May 14 01:21:42 PM PDT 24 662099019 ps
T877 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3436516948 May 14 01:21:33 PM PDT 24 May 14 01:21:36 PM PDT 24 396802264 ps
T878 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2909010747 May 14 01:21:40 PM PDT 24 May 14 01:21:42 PM PDT 24 355992919 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3858046542 May 14 01:21:30 PM PDT 24 May 14 01:21:36 PM PDT 24 867976239 ps
T880 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1375462986 May 14 01:22:15 PM PDT 24 May 14 01:22:28 PM PDT 24 4610070418 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2353566816 May 14 01:21:29 PM PDT 24 May 14 01:21:38 PM PDT 24 2277814661 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1903171154 May 14 01:21:28 PM PDT 24 May 14 01:21:30 PM PDT 24 409116573 ps
T883 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.873798511 May 14 01:22:15 PM PDT 24 May 14 01:22:20 PM PDT 24 560535227 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1624726465 May 14 01:22:14 PM PDT 24 May 14 01:22:20 PM PDT 24 4151136556 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1059150646 May 14 01:21:30 PM PDT 24 May 14 01:21:48 PM PDT 24 27219927471 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2447849005 May 14 01:21:41 PM PDT 24 May 14 01:22:01 PM PDT 24 8132332949 ps
T887 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3641746817 May 14 01:22:16 PM PDT 24 May 14 01:22:19 PM PDT 24 304405454 ps
T888 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1222060885 May 14 01:22:16 PM PDT 24 May 14 01:22:19 PM PDT 24 454242655 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.697193412 May 14 01:21:30 PM PDT 24 May 14 01:21:33 PM PDT 24 542312910 ps
T890 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3605653424 May 14 01:21:42 PM PDT 24 May 14 01:22:00 PM PDT 24 3776625451 ps
T891 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2864487960 May 14 01:22:14 PM PDT 24 May 14 01:22:18 PM PDT 24 574877053 ps
T892 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4081912815 May 14 01:22:12 PM PDT 24 May 14 01:22:14 PM PDT 24 479894082 ps
T893 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2078133327 May 14 01:21:25 PM PDT 24 May 14 01:21:28 PM PDT 24 876589658 ps
T894 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1757631089 May 14 01:22:14 PM PDT 24 May 14 01:22:18 PM PDT 24 556473325 ps
T895 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3630237567 May 14 01:21:40 PM PDT 24 May 14 01:21:48 PM PDT 24 8807651459 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.691673726 May 14 01:21:31 PM PDT 24 May 14 01:21:35 PM PDT 24 547301706 ps
T897 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3060343084 May 14 01:22:15 PM PDT 24 May 14 01:22:18 PM PDT 24 609706609 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3395499964 May 14 01:21:58 PM PDT 24 May 14 01:22:22 PM PDT 24 8233466051 ps
T899 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.839180734 May 14 01:21:41 PM PDT 24 May 14 01:21:44 PM PDT 24 547893981 ps
T900 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4011795088 May 14 01:22:13 PM PDT 24 May 14 01:22:17 PM PDT 24 495578067 ps
T901 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.836965560 May 14 01:21:42 PM PDT 24 May 14 01:21:46 PM PDT 24 2506634453 ps
T902 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.155082388 May 14 01:21:57 PM PDT 24 May 14 01:21:59 PM PDT 24 711339778 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2455413128 May 14 01:21:58 PM PDT 24 May 14 01:22:02 PM PDT 24 480279653 ps
T904 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2486949454 May 14 01:22:15 PM PDT 24 May 14 01:22:19 PM PDT 24 682029883 ps
T905 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.589910928 May 14 01:22:32 PM PDT 24 May 14 01:22:34 PM PDT 24 552992606 ps
T906 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.636661493 May 14 01:22:18 PM PDT 24 May 14 01:22:21 PM PDT 24 312680787 ps
T907 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.805210630 May 14 01:21:31 PM PDT 24 May 14 01:21:35 PM PDT 24 945517963 ps
T908 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.540370742 May 14 01:21:41 PM PDT 24 May 14 01:21:44 PM PDT 24 576551651 ps
T909 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1422745822 May 14 01:22:33 PM PDT 24 May 14 01:22:37 PM PDT 24 291722533 ps
T910 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2706659301 May 14 01:21:57 PM PDT 24 May 14 01:22:01 PM PDT 24 574523110 ps
T911 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1081367471 May 14 01:21:56 PM PDT 24 May 14 01:21:59 PM PDT 24 2612612659 ps
T912 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.767107800 May 14 01:22:34 PM PDT 24 May 14 01:22:38 PM PDT 24 510690587 ps
T913 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3461554766 May 14 01:22:14 PM PDT 24 May 14 01:22:16 PM PDT 24 442131436 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2943935877 May 14 01:21:24 PM PDT 24 May 14 01:22:00 PM PDT 24 27416033705 ps
T915 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2473225311 May 14 01:21:57 PM PDT 24 May 14 01:22:00 PM PDT 24 2208392085 ps
T916 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3204684910 May 14 01:21:40 PM PDT 24 May 14 01:21:43 PM PDT 24 681781846 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2977700222 May 14 01:21:42 PM PDT 24 May 14 01:21:46 PM PDT 24 524139754 ps
T918 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4145825929 May 14 01:22:15 PM PDT 24 May 14 01:22:19 PM PDT 24 423737649 ps

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2530561665
Short name T3
Test name
Test status
Simulation time 197099297659 ps
CPU time 175.84 seconds
Started May 14 03:01:56 PM PDT 24
Finished May 14 03:04:52 PM PDT 24
Peak memory 210600 kb
Host smart-7c0c0d1e-d2bd-44d3-a682-124a2fce714e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530561665 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2530561665
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3815432254
Short name T36
Test name
Test status
Simulation time 533665950697 ps
CPU time 2579.83 seconds
Started May 14 03:05:50 PM PDT 24
Finished May 14 03:48:51 PM PDT 24
Peak memory 210400 kb
Host smart-290d35a7-7311-4f27-9e69-63264b74b4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815432254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3815432254
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3382224881
Short name T33
Test name
Test status
Simulation time 502626420085 ps
CPU time 1039.2 seconds
Started May 14 03:06:37 PM PDT 24
Finished May 14 03:23:59 PM PDT 24
Peak memory 201808 kb
Host smart-8db5aea1-e833-404e-87ea-1e660269fa9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382224881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3382224881
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3072729379
Short name T11
Test name
Test status
Simulation time 360086005398 ps
CPU time 785.03 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:13:59 PM PDT 24
Peak memory 201724 kb
Host smart-5c49ee9f-8771-4c79-b6bc-e8bc24ab885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072729379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3072729379
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.957980663
Short name T91
Test name
Test status
Simulation time 521103309643 ps
CPU time 393.11 seconds
Started May 14 03:08:28 PM PDT 24
Finished May 14 03:15:02 PM PDT 24
Peak memory 201808 kb
Host smart-1b125176-ebeb-44cb-ae5f-b7d1d7ff415b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957980663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.957980663
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2854513270
Short name T27
Test name
Test status
Simulation time 197162950432 ps
CPU time 226.36 seconds
Started May 14 03:03:54 PM PDT 24
Finished May 14 03:07:41 PM PDT 24
Peak memory 210404 kb
Host smart-f4a94cd2-e6d5-4a82-8344-f8fe51d53b4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854513270 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2854513270
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4004102309
Short name T235
Test name
Test status
Simulation time 557492926672 ps
CPU time 268.13 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:11:46 PM PDT 24
Peak memory 201800 kb
Host smart-82482ab3-1bef-4209-91c2-db8798a2b898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004102309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4004102309
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.750957456
Short name T31
Test name
Test status
Simulation time 208023359680 ps
CPU time 131.13 seconds
Started May 14 03:01:46 PM PDT 24
Finished May 14 03:03:58 PM PDT 24
Peak memory 217760 kb
Host smart-1f12cd38-e96f-47e6-bf00-d849435901a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750957456 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.750957456
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.984423657
Short name T131
Test name
Test status
Simulation time 328173308012 ps
CPU time 215.22 seconds
Started May 14 03:01:56 PM PDT 24
Finished May 14 03:05:32 PM PDT 24
Peak memory 201916 kb
Host smart-2bdd2108-5eba-48bb-8a92-48ca8fc9871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984423657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.984423657
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1272806514
Short name T28
Test name
Test status
Simulation time 147683825296 ps
CPU time 228.44 seconds
Started May 14 02:56:58 PM PDT 24
Finished May 14 03:00:47 PM PDT 24
Peak memory 218672 kb
Host smart-82f924bb-e897-4fa0-8d4a-be89beef5cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272806514 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1272806514
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2805991294
Short name T195
Test name
Test status
Simulation time 524482620321 ps
CPU time 1276.77 seconds
Started May 14 03:09:21 PM PDT 24
Finished May 14 03:30:39 PM PDT 24
Peak memory 201788 kb
Host smart-637a1ed3-ceb7-43ad-a46b-d083a4582020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805991294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2805991294
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3116131303
Short name T49
Test name
Test status
Simulation time 8186386240 ps
CPU time 5.4 seconds
Started May 14 02:56:56 PM PDT 24
Finished May 14 02:57:03 PM PDT 24
Peak memory 218416 kb
Host smart-3f1de8ef-dcd9-4e93-9e4e-8ff5cafdf2e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116131303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3116131303
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1875041318
Short name T52
Test name
Test status
Simulation time 546183832 ps
CPU time 2.08 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:16 PM PDT 24
Peak memory 210184 kb
Host smart-1734345c-472a-46f5-a9a0-51ed6072ea0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875041318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1875041318
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2226013144
Short name T238
Test name
Test status
Simulation time 499445520807 ps
CPU time 626.75 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 03:08:01 PM PDT 24
Peak memory 201900 kb
Host smart-20a93b4b-dc9d-43bd-a432-6dd9c535c260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226013144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2226013144
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2028191720
Short name T252
Test name
Test status
Simulation time 510388408191 ps
CPU time 1159.55 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 03:16:54 PM PDT 24
Peak memory 201848 kb
Host smart-280c7020-8d88-4909-a586-c10d8d1ca21b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028191720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2028191720
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3282366179
Short name T223
Test name
Test status
Simulation time 350763353143 ps
CPU time 738 seconds
Started May 14 02:57:25 PM PDT 24
Finished May 14 03:09:44 PM PDT 24
Peak memory 201928 kb
Host smart-7cf3d523-b801-4f9d-8a15-e009dbc330e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282366179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3282366179
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3617063014
Short name T108
Test name
Test status
Simulation time 50987887546 ps
CPU time 38.47 seconds
Started May 14 01:21:33 PM PDT 24
Finished May 14 01:22:13 PM PDT 24
Peak memory 201904 kb
Host smart-a3a648f2-7a62-495e-bacb-2675aabceea5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617063014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3617063014
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.4165953537
Short name T34
Test name
Test status
Simulation time 170833613288 ps
CPU time 100.4 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:10:24 PM PDT 24
Peak memory 201840 kb
Host smart-20d8e1b1-78cf-44f4-9827-4fa006273d4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165953537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.4165953537
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1898885717
Short name T232
Test name
Test status
Simulation time 541263357387 ps
CPU time 248.42 seconds
Started May 14 02:57:44 PM PDT 24
Finished May 14 03:01:54 PM PDT 24
Peak memory 201808 kb
Host smart-fa3876fd-79be-4705-8540-f237dfa2ed6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898885717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1898885717
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2775228233
Short name T199
Test name
Test status
Simulation time 551168017629 ps
CPU time 716.93 seconds
Started May 14 03:09:05 PM PDT 24
Finished May 14 03:21:03 PM PDT 24
Peak memory 201736 kb
Host smart-d5b96a91-424f-47d9-a615-037c3359c304
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775228233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2775228233
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.854345763
Short name T140
Test name
Test status
Simulation time 522597219137 ps
CPU time 198.24 seconds
Started May 14 03:07:22 PM PDT 24
Finished May 14 03:10:41 PM PDT 24
Peak memory 201836 kb
Host smart-e26b5734-d934-416b-bae7-fde5bc0f7324
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854345763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.854345763
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1372674141
Short name T8
Test name
Test status
Simulation time 600349512820 ps
CPU time 843.36 seconds
Started May 14 03:06:39 PM PDT 24
Finished May 14 03:20:44 PM PDT 24
Peak memory 201732 kb
Host smart-ca3c5521-08f9-4961-bc6a-2dba060390eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372674141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1372674141
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2865938992
Short name T255
Test name
Test status
Simulation time 353856172968 ps
CPU time 769.03 seconds
Started May 14 03:04:00 PM PDT 24
Finished May 14 03:16:51 PM PDT 24
Peak memory 201804 kb
Host smart-cfa7ae62-1cc3-468d-bef6-826c01e9fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865938992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2865938992
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2745223096
Short name T160
Test name
Test status
Simulation time 550306128268 ps
CPU time 153 seconds
Started May 14 03:08:49 PM PDT 24
Finished May 14 03:11:22 PM PDT 24
Peak memory 201836 kb
Host smart-8edf5b57-00ff-4cc9-bcee-b05581223d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745223096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2745223096
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.939730409
Short name T188
Test name
Test status
Simulation time 615749086261 ps
CPU time 1316.82 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:24:32 PM PDT 24
Peak memory 201852 kb
Host smart-532af7a0-e872-447b-a266-5bff65b87fb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939730409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.939730409
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1371428146
Short name T227
Test name
Test status
Simulation time 493345178322 ps
CPU time 614.53 seconds
Started May 14 02:57:45 PM PDT 24
Finished May 14 03:08:00 PM PDT 24
Peak memory 201904 kb
Host smart-0e90a8da-0a7a-41a4-b0a9-c0e1d2017f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371428146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1371428146
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.508419135
Short name T158
Test name
Test status
Simulation time 344390312192 ps
CPU time 390.07 seconds
Started May 14 03:05:45 PM PDT 24
Finished May 14 03:12:17 PM PDT 24
Peak memory 201924 kb
Host smart-3fc6c128-5392-4157-89b2-2f235a0a8ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508419135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.508419135
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2037453354
Short name T180
Test name
Test status
Simulation time 334607870581 ps
CPU time 203.43 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:04:17 PM PDT 24
Peak memory 201740 kb
Host smart-387a17f8-dc0a-449f-bc68-7ccdfff34d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037453354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2037453354
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3393076766
Short name T97
Test name
Test status
Simulation time 328352506 ps
CPU time 0.84 seconds
Started May 14 03:01:25 PM PDT 24
Finished May 14 03:01:26 PM PDT 24
Peak memory 201492 kb
Host smart-4969e9bf-2352-4b6e-a63e-3a6c5c6a3ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393076766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3393076766
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1443652357
Short name T59
Test name
Test status
Simulation time 8887769992 ps
CPU time 5.43 seconds
Started May 14 01:21:56 PM PDT 24
Finished May 14 01:22:03 PM PDT 24
Peak memory 201996 kb
Host smart-d1b44399-0889-43ed-b5f6-f0e6029dafe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443652357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1443652357
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1318521547
Short name T276
Test name
Test status
Simulation time 132888417543 ps
CPU time 110.22 seconds
Started May 14 02:59:33 PM PDT 24
Finished May 14 03:01:24 PM PDT 24
Peak memory 210516 kb
Host smart-895a71d3-2851-47b9-b237-44aca5bd5b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318521547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1318521547
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.482305911
Short name T281
Test name
Test status
Simulation time 329329118226 ps
CPU time 220.51 seconds
Started May 14 02:58:50 PM PDT 24
Finished May 14 03:02:31 PM PDT 24
Peak memory 201820 kb
Host smart-8e5047b2-280b-4130-a5cd-38704a7b3d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482305911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.482305911
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4003069807
Short name T293
Test name
Test status
Simulation time 549044764607 ps
CPU time 727.64 seconds
Started May 14 03:06:03 PM PDT 24
Finished May 14 03:18:13 PM PDT 24
Peak memory 201836 kb
Host smart-7b6e5111-24e4-490f-a0b6-5f9daed76185
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003069807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4003069807
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3410447614
Short name T115
Test name
Test status
Simulation time 4478666030 ps
CPU time 10.3 seconds
Started May 14 01:21:25 PM PDT 24
Finished May 14 01:21:36 PM PDT 24
Peak memory 201920 kb
Host smart-943909b1-0474-43c1-bcc8-d1d3dedf0af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410447614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3410447614
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2920511372
Short name T240
Test name
Test status
Simulation time 172885786356 ps
CPU time 380.03 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:13:38 PM PDT 24
Peak memory 201888 kb
Host smart-ca502106-6f86-43e4-be30-b33e09dc846d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920511372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2920511372
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4086412320
Short name T241
Test name
Test status
Simulation time 341198840310 ps
CPU time 195.59 seconds
Started May 14 03:00:38 PM PDT 24
Finished May 14 03:03:55 PM PDT 24
Peak memory 201880 kb
Host smart-77815111-a0f1-4cf8-96cb-422ea9b06910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086412320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4086412320
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1199596183
Short name T327
Test name
Test status
Simulation time 524855020394 ps
CPU time 599.81 seconds
Started May 14 03:07:04 PM PDT 24
Finished May 14 03:17:06 PM PDT 24
Peak memory 201788 kb
Host smart-0e0e13a3-1125-49e1-9e94-a4af11b20486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199596183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1199596183
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2978371497
Short name T124
Test name
Test status
Simulation time 335707634245 ps
CPU time 412.87 seconds
Started May 14 02:57:45 PM PDT 24
Finished May 14 03:04:39 PM PDT 24
Peak memory 201776 kb
Host smart-3d5eb287-b848-4ed7-b6f5-d71ab78873b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978371497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2978371497
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4098546017
Short name T242
Test name
Test status
Simulation time 329917473526 ps
CPU time 96.1 seconds
Started May 14 03:06:19 PM PDT 24
Finished May 14 03:07:58 PM PDT 24
Peak memory 201928 kb
Host smart-4a7fce83-2435-4582-b64e-afb62b88f139
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098546017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4098546017
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2096316372
Short name T66
Test name
Test status
Simulation time 541446199 ps
CPU time 2.73 seconds
Started May 14 01:21:25 PM PDT 24
Finished May 14 01:21:29 PM PDT 24
Peak memory 210192 kb
Host smart-33d631aa-b27b-46a0-82d0-bd22a07c8d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096316372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2096316372
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3816673569
Short name T6
Test name
Test status
Simulation time 327578007300 ps
CPU time 208.46 seconds
Started May 14 02:58:13 PM PDT 24
Finished May 14 03:01:42 PM PDT 24
Peak memory 201800 kb
Host smart-01f9fc2c-8b2a-4298-8ffe-0f880ed25de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816673569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3816673569
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3485609606
Short name T253
Test name
Test status
Simulation time 339601224560 ps
CPU time 414.53 seconds
Started May 14 03:03:11 PM PDT 24
Finished May 14 03:10:07 PM PDT 24
Peak memory 201792 kb
Host smart-d649ec09-2b90-41dd-867e-edb1e666b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485609606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3485609606
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2730153952
Short name T299
Test name
Test status
Simulation time 487367092768 ps
CPU time 265.71 seconds
Started May 14 03:03:30 PM PDT 24
Finished May 14 03:07:57 PM PDT 24
Peak memory 201728 kb
Host smart-d260b09b-2fca-47bc-a04a-b441446b9497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730153952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2730153952
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.691154650
Short name T334
Test name
Test status
Simulation time 337083916148 ps
CPU time 401.41 seconds
Started May 14 03:01:00 PM PDT 24
Finished May 14 03:07:45 PM PDT 24
Peak memory 201772 kb
Host smart-f860ac06-31b8-41f9-b296-271cc496ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691154650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.691154650
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1896097800
Short name T324
Test name
Test status
Simulation time 493697092256 ps
CPU time 320.6 seconds
Started May 14 03:05:09 PM PDT 24
Finished May 14 03:10:31 PM PDT 24
Peak memory 201888 kb
Host smart-05b677ce-5e08-4e71-838d-446643235ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896097800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1896097800
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3839290054
Short name T257
Test name
Test status
Simulation time 348290125730 ps
CPU time 196.48 seconds
Started May 14 03:03:11 PM PDT 24
Finished May 14 03:06:29 PM PDT 24
Peak memory 201804 kb
Host smart-a2d8e537-19f4-4984-9340-34793f192c08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839290054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3839290054
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4191037658
Short name T280
Test name
Test status
Simulation time 338765614639 ps
CPU time 604.85 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:17:23 PM PDT 24
Peak memory 201844 kb
Host smart-4bf11637-df0a-43fc-9ee3-8df65bde9150
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191037658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4191037658
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3081311106
Short name T372
Test name
Test status
Simulation time 330607140716 ps
CPU time 832.11 seconds
Started May 14 03:00:48 PM PDT 24
Finished May 14 03:14:42 PM PDT 24
Peak memory 201836 kb
Host smart-f4462ed9-97e2-4962-9df9-597fa5f4294e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081311106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3081311106
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.758765779
Short name T305
Test name
Test status
Simulation time 164871331394 ps
CPU time 118.32 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:02:53 PM PDT 24
Peak memory 201916 kb
Host smart-ec5320f8-8d48-4fcd-81eb-5adc17b26ded
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758765779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.758765779
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3886771917
Short name T312
Test name
Test status
Simulation time 484656306199 ps
CPU time 266.69 seconds
Started May 14 03:01:25 PM PDT 24
Finished May 14 03:05:52 PM PDT 24
Peak memory 202132 kb
Host smart-5c15362b-61ce-491d-b0e2-993d24a08996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886771917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3886771917
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1161229235
Short name T244
Test name
Test status
Simulation time 579812699600 ps
CPU time 1473.47 seconds
Started May 14 03:03:02 PM PDT 24
Finished May 14 03:27:36 PM PDT 24
Peak memory 201820 kb
Host smart-37ce7305-aeca-49e2-bfc8-5ca78915cba5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161229235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1161229235
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1200858855
Short name T15
Test name
Test status
Simulation time 343596092381 ps
CPU time 251.63 seconds
Started May 14 03:04:52 PM PDT 24
Finished May 14 03:09:05 PM PDT 24
Peak memory 216328 kb
Host smart-609b7c33-43ca-4240-bdbe-5e6675a67573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200858855 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1200858855
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2302912168
Short name T287
Test name
Test status
Simulation time 507954052960 ps
CPU time 771.95 seconds
Started May 14 03:05:18 PM PDT 24
Finished May 14 03:18:11 PM PDT 24
Peak memory 201848 kb
Host smart-f72257fb-f6cd-427b-8214-9659add02282
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302912168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2302912168
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3024585457
Short name T264
Test name
Test status
Simulation time 179434636387 ps
CPU time 351.59 seconds
Started May 14 03:05:51 PM PDT 24
Finished May 14 03:11:44 PM PDT 24
Peak memory 201844 kb
Host smart-d43d87d9-a266-4169-80a1-50eac1c8e013
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024585457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3024585457
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3761640738
Short name T347
Test name
Test status
Simulation time 184650480278 ps
CPU time 735.52 seconds
Started May 14 03:06:11 PM PDT 24
Finished May 14 03:18:27 PM PDT 24
Peak memory 202192 kb
Host smart-0f5e678f-37fc-4dae-a07b-8d2786d86f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761640738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3761640738
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3861569796
Short name T306
Test name
Test status
Simulation time 529364744408 ps
CPU time 227.89 seconds
Started May 14 02:58:02 PM PDT 24
Finished May 14 03:01:51 PM PDT 24
Peak memory 201860 kb
Host smart-895a349e-94da-40be-afff-93206191ce5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861569796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3861569796
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2598049223
Short name T224
Test name
Test status
Simulation time 186143798096 ps
CPU time 389.98 seconds
Started May 14 03:07:25 PM PDT 24
Finished May 14 03:13:56 PM PDT 24
Peak memory 201824 kb
Host smart-10d0a0d7-1854-4701-a594-d38d55c05459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598049223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2598049223
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2240511456
Short name T218
Test name
Test status
Simulation time 360126141638 ps
CPU time 420.69 seconds
Started May 14 02:58:38 PM PDT 24
Finished May 14 03:05:41 PM PDT 24
Peak memory 201908 kb
Host smart-8ea92896-f902-4355-8e38-c9069019a158
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240511456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2240511456
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.520047464
Short name T320
Test name
Test status
Simulation time 171549561939 ps
CPU time 372.43 seconds
Started May 14 03:03:18 PM PDT 24
Finished May 14 03:09:32 PM PDT 24
Peak memory 201880 kb
Host smart-ed3fb433-5455-47b3-976b-6ca514e2a995
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520047464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.520047464
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2221704909
Short name T350
Test name
Test status
Simulation time 144563151276 ps
CPU time 508.69 seconds
Started May 14 03:06:40 PM PDT 24
Finished May 14 03:15:10 PM PDT 24
Peak memory 202052 kb
Host smart-912ded3c-9f25-458b-83dc-6224eeaacc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221704909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2221704909
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.145543341
Short name T309
Test name
Test status
Simulation time 162354615096 ps
CPU time 196.71 seconds
Started May 14 03:06:46 PM PDT 24
Finished May 14 03:10:04 PM PDT 24
Peak memory 201940 kb
Host smart-86215d93-e8d7-4822-8ee9-139f26b380bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145543341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.145543341
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2232192949
Short name T296
Test name
Test status
Simulation time 158030420350 ps
CPU time 383.72 seconds
Started May 14 02:58:21 PM PDT 24
Finished May 14 03:04:45 PM PDT 24
Peak memory 201748 kb
Host smart-30b5eb32-25b0-4ce6-899f-aa4890b2e4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232192949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2232192949
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3850176602
Short name T318
Test name
Test status
Simulation time 488625582308 ps
CPU time 338.41 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:06:20 PM PDT 24
Peak memory 201872 kb
Host smart-7814629e-59bc-4f0a-900a-c429393352b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850176602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3850176602
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.321789503
Short name T301
Test name
Test status
Simulation time 173066392542 ps
CPU time 69.13 seconds
Started May 14 03:00:58 PM PDT 24
Finished May 14 03:02:11 PM PDT 24
Peak memory 201844 kb
Host smart-14380aaf-a8a2-4c73-b1dd-52db6f3a9b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321789503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
321789503
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2745222967
Short name T348
Test name
Test status
Simulation time 118219292535 ps
CPU time 413.92 seconds
Started May 14 03:04:53 PM PDT 24
Finished May 14 03:11:48 PM PDT 24
Peak memory 202080 kb
Host smart-7642d9d5-5e7d-4865-b0bd-e99024f7a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745222967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2745222967
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.4158422151
Short name T222
Test name
Test status
Simulation time 459511291326 ps
CPU time 250.58 seconds
Started May 14 03:07:40 PM PDT 24
Finished May 14 03:11:52 PM PDT 24
Peak memory 202124 kb
Host smart-2c782965-a775-4a5c-8206-6aa78bc65f7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158422151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.4158422151
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.220663885
Short name T136
Test name
Test status
Simulation time 339585579479 ps
CPU time 658.92 seconds
Started May 14 03:08:56 PM PDT 24
Finished May 14 03:19:56 PM PDT 24
Peak memory 201904 kb
Host smart-c5f9c737-e9e0-4075-887e-b7ad3382099d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220663885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
220663885
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2643709111
Short name T141
Test name
Test status
Simulation time 491653122708 ps
CPU time 982.49 seconds
Started May 14 02:59:19 PM PDT 24
Finished May 14 03:15:43 PM PDT 24
Peak memory 201860 kb
Host smart-a6b82f85-c8ee-42ef-a9d7-c28253563145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643709111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2643709111
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2476656873
Short name T54
Test name
Test status
Simulation time 564332399 ps
CPU time 2.55 seconds
Started May 14 01:21:23 PM PDT 24
Finished May 14 01:21:27 PM PDT 24
Peak memory 201904 kb
Host smart-d2b00cfe-b988-4c1e-bfc4-e73d843811ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476656873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2476656873
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.321390995
Short name T71
Test name
Test status
Simulation time 8575020686 ps
CPU time 9.44 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:26 PM PDT 24
Peak memory 201944 kb
Host smart-0a80c9df-7446-419f-8db6-fb4fd921824d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321390995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.321390995
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.465650039
Short name T245
Test name
Test status
Simulation time 400491211635 ps
CPU time 952.89 seconds
Started May 14 03:01:07 PM PDT 24
Finished May 14 03:17:01 PM PDT 24
Peak memory 201904 kb
Host smart-c9065371-0406-449c-b113-9d684139d5a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465650039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.465650039
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.421734703
Short name T769
Test name
Test status
Simulation time 520427573167 ps
CPU time 1207.32 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:21:42 PM PDT 24
Peak memory 201884 kb
Host smart-235698e1-ec1b-4720-a52b-b379077b51b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421734703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.421734703
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.695183944
Short name T211
Test name
Test status
Simulation time 120514162276 ps
CPU time 664.52 seconds
Started May 14 03:01:43 PM PDT 24
Finished May 14 03:12:49 PM PDT 24
Peak memory 202152 kb
Host smart-9bc8b945-ac2c-42d4-920a-33c8fdcc0c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695183944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.695183944
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.34540873
Short name T292
Test name
Test status
Simulation time 200636375791 ps
CPU time 477.58 seconds
Started May 14 03:02:52 PM PDT 24
Finished May 14 03:10:51 PM PDT 24
Peak memory 201800 kb
Host smart-d81b38d1-aed7-495f-953a-760657c2b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34540873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.34540873
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1470789018
Short name T10
Test name
Test status
Simulation time 63689905421 ps
CPU time 375.61 seconds
Started May 14 02:57:34 PM PDT 24
Finished May 14 03:03:51 PM PDT 24
Peak memory 202140 kb
Host smart-c599d3b4-ea90-4bf4-bf0a-0c14865c8a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470789018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1470789018
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.696530717
Short name T219
Test name
Test status
Simulation time 165030180674 ps
CPU time 372.01 seconds
Started May 14 03:03:00 PM PDT 24
Finished May 14 03:09:12 PM PDT 24
Peak memory 201812 kb
Host smart-c32795e1-9cf2-4d93-a219-9cfb7996d793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696530717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.696530717
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2363243820
Short name T316
Test name
Test status
Simulation time 207474921712 ps
CPU time 472.75 seconds
Started May 14 03:03:55 PM PDT 24
Finished May 14 03:11:49 PM PDT 24
Peak memory 201868 kb
Host smart-7c6665a3-af5c-4a15-87e5-409662b5ecdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363243820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2363243820
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4060883941
Short name T297
Test name
Test status
Simulation time 174874689750 ps
CPU time 35.18 seconds
Started May 14 03:04:01 PM PDT 24
Finished May 14 03:04:38 PM PDT 24
Peak memory 201736 kb
Host smart-3853c4af-e438-4119-aba3-dd5ea943cea3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060883941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4060883941
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.78875332
Short name T217
Test name
Test status
Simulation time 119332705169 ps
CPU time 637.12 seconds
Started May 14 03:04:20 PM PDT 24
Finished May 14 03:14:59 PM PDT 24
Peak memory 202136 kb
Host smart-7f683451-2d73-43a3-a6a2-acfcfacc3d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78875332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.78875332
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.250264701
Short name T330
Test name
Test status
Simulation time 528202657575 ps
CPU time 944.65 seconds
Started May 14 03:04:59 PM PDT 24
Finished May 14 03:20:45 PM PDT 24
Peak memory 201748 kb
Host smart-1f302593-0203-4e69-b755-670868c3bff8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250264701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.250264701
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3736525126
Short name T326
Test name
Test status
Simulation time 362275909398 ps
CPU time 436.28 seconds
Started May 14 03:05:51 PM PDT 24
Finished May 14 03:13:09 PM PDT 24
Peak memory 201868 kb
Host smart-16d1f8c8-ba32-43a0-b908-397a8ec6a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736525126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3736525126
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2834029083
Short name T346
Test name
Test status
Simulation time 95099727514 ps
CPU time 326.78 seconds
Started May 14 02:58:15 PM PDT 24
Finished May 14 03:03:42 PM PDT 24
Peak memory 202036 kb
Host smart-6d7e5f0c-1fe6-4df0-a5ea-a34072864f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834029083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2834029083
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.389989196
Short name T260
Test name
Test status
Simulation time 146726416538 ps
CPU time 99.69 seconds
Started May 14 03:08:12 PM PDT 24
Finished May 14 03:09:53 PM PDT 24
Peak memory 218000 kb
Host smart-0d9c16a8-9e1f-46a7-abef-e6b502bea99a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389989196 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.389989196
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2078133327
Short name T893
Test name
Test status
Simulation time 876589658 ps
CPU time 1.95 seconds
Started May 14 01:21:25 PM PDT 24
Finished May 14 01:21:28 PM PDT 24
Peak memory 201900 kb
Host smart-0cd664e0-ae82-4797-afb6-1c1a35c046fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078133327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2078133327
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2943935877
Short name T914
Test name
Test status
Simulation time 27416033705 ps
CPU time 33.8 seconds
Started May 14 01:21:24 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201932 kb
Host smart-b4f855a0-1a70-4b88-8daa-2677c713eca3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943935877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2943935877
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3835518616
Short name T111
Test name
Test status
Simulation time 765182731 ps
CPU time 2.39 seconds
Started May 14 01:21:24 PM PDT 24
Finished May 14 01:21:28 PM PDT 24
Peak memory 201640 kb
Host smart-180e4347-ec15-485c-a736-995a42275760
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835518616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3835518616
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3436516948
Short name T877
Test name
Test status
Simulation time 396802264 ps
CPU time 1.8 seconds
Started May 14 01:21:33 PM PDT 24
Finished May 14 01:21:36 PM PDT 24
Peak memory 201580 kb
Host smart-fb3f7f65-afcb-4d67-a4f2-0ac873f09384
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436516948 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3436516948
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3902277307
Short name T117
Test name
Test status
Simulation time 448367852 ps
CPU time 0.85 seconds
Started May 14 01:21:23 PM PDT 24
Finished May 14 01:21:26 PM PDT 24
Peak memory 201612 kb
Host smart-38cd82cd-9231-4a05-8aac-c4f5aea552f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902277307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3902277307
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1903171154
Short name T882
Test name
Test status
Simulation time 409116573 ps
CPU time 1.59 seconds
Started May 14 01:21:28 PM PDT 24
Finished May 14 01:21:30 PM PDT 24
Peak memory 201676 kb
Host smart-d836fea2-b26d-485c-939d-1d2d001f1c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903171154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1903171154
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3618889241
Short name T846
Test name
Test status
Simulation time 4733608881 ps
CPU time 7.23 seconds
Started May 14 01:21:23 PM PDT 24
Finished May 14 01:21:31 PM PDT 24
Peak memory 201876 kb
Host smart-b9f080f5-b723-4d81-b112-8603cc2bb362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618889241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3618889241
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1222653805
Short name T101
Test name
Test status
Simulation time 509902904 ps
CPU time 3 seconds
Started May 14 01:21:31 PM PDT 24
Finished May 14 01:21:35 PM PDT 24
Peak memory 201836 kb
Host smart-1b18b548-1f1f-4df2-afd3-813f7d48b85f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222653805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1222653805
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2899919653
Short name T106
Test name
Test status
Simulation time 725120371 ps
CPU time 2.31 seconds
Started May 14 01:21:24 PM PDT 24
Finished May 14 01:21:28 PM PDT 24
Peak memory 201688 kb
Host smart-cb138df4-57a0-4f43-8096-dd06ad0fa50a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899919653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2899919653
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4074126683
Short name T63
Test name
Test status
Simulation time 429849471 ps
CPU time 1.99 seconds
Started May 14 01:21:29 PM PDT 24
Finished May 14 01:21:32 PM PDT 24
Peak memory 201808 kb
Host smart-cc4ffd16-70f5-43d6-9876-40ad754b53c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074126683 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4074126683
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1874430627
Short name T855
Test name
Test status
Simulation time 503251710 ps
CPU time 1.53 seconds
Started May 14 01:21:26 PM PDT 24
Finished May 14 01:21:28 PM PDT 24
Peak memory 201704 kb
Host smart-49925df3-23b0-4be8-9ef0-fea454083ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874430627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1874430627
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3650463122
Short name T817
Test name
Test status
Simulation time 342776589 ps
CPU time 1.02 seconds
Started May 14 01:21:23 PM PDT 24
Finished May 14 01:21:25 PM PDT 24
Peak memory 201672 kb
Host smart-afc2da19-abfe-480d-a08c-e5e387a46e39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650463122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3650463122
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3176178125
Short name T852
Test name
Test status
Simulation time 3923986677 ps
CPU time 8.74 seconds
Started May 14 01:21:31 PM PDT 24
Finished May 14 01:21:41 PM PDT 24
Peak memory 201988 kb
Host smart-ae2b7271-cd0f-4293-ae43-782247b511af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176178125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3176178125
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3041304453
Short name T44
Test name
Test status
Simulation time 4697534798 ps
CPU time 3.23 seconds
Started May 14 01:21:22 PM PDT 24
Finished May 14 01:21:27 PM PDT 24
Peak memory 201948 kb
Host smart-8ee432f0-3be0-40e9-88bc-60fe46224646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041304453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3041304453
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2725318504
Short name T816
Test name
Test status
Simulation time 678959181 ps
CPU time 1.35 seconds
Started May 14 01:21:59 PM PDT 24
Finished May 14 01:22:02 PM PDT 24
Peak memory 201704 kb
Host smart-716479b6-3083-4821-96cf-6b19118c5774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725318504 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2725318504
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2899642611
Short name T103
Test name
Test status
Simulation time 365432273 ps
CPU time 1.16 seconds
Started May 14 01:21:55 PM PDT 24
Finished May 14 01:21:57 PM PDT 24
Peak memory 201716 kb
Host smart-78b24b29-827b-424b-af2b-fedf37f64e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899642611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2899642611
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1616618133
Short name T823
Test name
Test status
Simulation time 477942709 ps
CPU time 0.81 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:21:59 PM PDT 24
Peak memory 201688 kb
Host smart-54c1e8ae-b790-44ec-8777-95e1e663f16b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616618133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1616618133
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1271432438
Short name T40
Test name
Test status
Simulation time 4937050201 ps
CPU time 16.83 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:15 PM PDT 24
Peak memory 201916 kb
Host smart-d3aecadd-1a28-4ec3-8b10-7098ac5a20d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271432438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1271432438
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2706659301
Short name T910
Test name
Test status
Simulation time 574523110 ps
CPU time 2.27 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:01 PM PDT 24
Peak memory 201992 kb
Host smart-3364527e-fc82-4f84-aeba-51df8853e82f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706659301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2706659301
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.954649827
Short name T48
Test name
Test status
Simulation time 4027269066 ps
CPU time 6.66 seconds
Started May 14 01:21:59 PM PDT 24
Finished May 14 01:22:06 PM PDT 24
Peak memory 201920 kb
Host smart-7fcadcd6-736a-44b8-9f39-1512067fa588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954649827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.954649827
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1413266180
Short name T60
Test name
Test status
Simulation time 547243869 ps
CPU time 1.48 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:15 PM PDT 24
Peak memory 201720 kb
Host smart-677a7f69-d8f6-4df4-878b-f4e2541ebd8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413266180 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1413266180
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2917985123
Short name T107
Test name
Test status
Simulation time 729768108 ps
CPU time 0.95 seconds
Started May 14 01:21:59 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201608 kb
Host smart-64823d4b-2982-4990-842d-4a85a8819955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917985123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2917985123
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2321635938
Short name T807
Test name
Test status
Simulation time 417975799 ps
CPU time 1.63 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201672 kb
Host smart-f103701f-5ab6-45d4-b960-d4ce6e0db48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321635938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2321635938
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1081367471
Short name T911
Test name
Test status
Simulation time 2612612659 ps
CPU time 2.58 seconds
Started May 14 01:21:56 PM PDT 24
Finished May 14 01:21:59 PM PDT 24
Peak memory 201732 kb
Host smart-76847e60-8789-488b-9248-1a8ce8d187f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081367471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1081367471
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2019244148
Short name T55
Test name
Test status
Simulation time 555648494 ps
CPU time 2.79 seconds
Started May 14 01:21:59 PM PDT 24
Finished May 14 01:22:03 PM PDT 24
Peak memory 218020 kb
Host smart-a46bbfab-96bf-4d87-ab49-38793888af22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019244148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2019244148
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.121096817
Short name T67
Test name
Test status
Simulation time 4222422213 ps
CPU time 6.06 seconds
Started May 14 01:21:56 PM PDT 24
Finished May 14 01:22:03 PM PDT 24
Peak memory 201984 kb
Host smart-bf899a83-d452-42fc-a5c1-896454741a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121096817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.121096817
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3930955864
Short name T813
Test name
Test status
Simulation time 497663047 ps
CPU time 2 seconds
Started May 14 01:22:18 PM PDT 24
Finished May 14 01:22:22 PM PDT 24
Peak memory 201708 kb
Host smart-3d3827ec-587f-40bf-9de6-ac9be6c5367b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930955864 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3930955864
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1629991590
Short name T872
Test name
Test status
Simulation time 538486208 ps
CPU time 1.36 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:18 PM PDT 24
Peak memory 201700 kb
Host smart-5767c032-378e-46c1-8e40-e93817c2dc7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629991590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1629991590
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4173069319
Short name T808
Test name
Test status
Simulation time 480287542 ps
CPU time 1.69 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201676 kb
Host smart-fbf50db8-11e8-48be-b4a9-c7e635b1f36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173069319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.4173069319
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2216309186
Short name T859
Test name
Test status
Simulation time 3037442494 ps
CPU time 3.51 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:21 PM PDT 24
Peak memory 201944 kb
Host smart-06505850-04eb-4be2-9502-7e21903b082c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216309186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2216309186
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1624726465
Short name T884
Test name
Test status
Simulation time 4151136556 ps
CPU time 4.12 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 202040 kb
Host smart-a2f67041-a1a2-4f1d-85a7-3c90e2439eab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624726465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1624726465
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.686320268
Short name T47
Test name
Test status
Simulation time 404831186 ps
CPU time 1.32 seconds
Started May 14 01:22:17 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201092 kb
Host smart-2ebc7d13-9d1f-4214-bdfc-6b3a712075bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686320268 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.686320268
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1222060885
Short name T888
Test name
Test status
Simulation time 454242655 ps
CPU time 0.96 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201628 kb
Host smart-c955588a-0e4a-4021-8c4e-73a3dc36dabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222060885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1222060885
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4259954252
Short name T858
Test name
Test status
Simulation time 400014174 ps
CPU time 1.58 seconds
Started May 14 01:22:19 PM PDT 24
Finished May 14 01:22:22 PM PDT 24
Peak memory 201560 kb
Host smart-e584b2f8-5a80-4175-9bf1-f82c5592ed1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259954252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4259954252
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3269352248
Short name T39
Test name
Test status
Simulation time 4513844637 ps
CPU time 6.77 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:21 PM PDT 24
Peak memory 201968 kb
Host smart-f6d36141-2d40-4ef6-a17c-238242fd5769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269352248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3269352248
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.873798511
Short name T883
Test name
Test status
Simulation time 560535227 ps
CPU time 3.15 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 211168 kb
Host smart-080be5f9-64ae-4ebe-b81d-c24c1c492ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873798511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.873798511
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1771346946
Short name T834
Test name
Test status
Simulation time 8594462082 ps
CPU time 6.02 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:23 PM PDT 24
Peak memory 201932 kb
Host smart-bc9d7090-e2b2-47aa-9e17-8fc6b678858f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771346946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1771346946
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3708243002
Short name T46
Test name
Test status
Simulation time 606281935 ps
CPU time 2.27 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201712 kb
Host smart-4a4a7e82-c555-4d20-ac53-31941ee8e350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708243002 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3708243002
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1011986068
Short name T113
Test name
Test status
Simulation time 527202582 ps
CPU time 2.04 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201672 kb
Host smart-d2a65e38-89de-49ee-a32a-88c965628e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011986068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1011986068
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1412818733
Short name T861
Test name
Test status
Simulation time 309651553 ps
CPU time 1.38 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201676 kb
Host smart-b09079cd-1644-4afa-8f97-34f22277aba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412818733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1412818733
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3876419017
Short name T843
Test name
Test status
Simulation time 2439146600 ps
CPU time 2.32 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201728 kb
Host smart-8d8488e4-e4c7-4fc2-906d-12f9daeb056e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876419017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3876419017
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4011795088
Short name T900
Test name
Test status
Simulation time 495578067 ps
CPU time 2.83 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:17 PM PDT 24
Peak memory 201924 kb
Host smart-54783859-9e55-4f26-b359-acbc8ddd2f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011795088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4011795088
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2403225189
Short name T43
Test name
Test status
Simulation time 4485677134 ps
CPU time 6.75 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:24 PM PDT 24
Peak memory 201924 kb
Host smart-eee3d301-29ec-4b32-826e-310fc30ca6e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403225189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2403225189
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3060343084
Short name T897
Test name
Test status
Simulation time 609706609 ps
CPU time 1.38 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:18 PM PDT 24
Peak memory 201696 kb
Host smart-788acdb4-5336-4491-b25b-89381db1ce7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060343084 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3060343084
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1308732963
Short name T818
Test name
Test status
Simulation time 484067867 ps
CPU time 1.42 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:16 PM PDT 24
Peak memory 201704 kb
Host smart-f83a2679-106c-4681-8eb3-f8e0f1f87a99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308732963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1308732963
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3443708218
Short name T804
Test name
Test status
Simulation time 483733728 ps
CPU time 0.86 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201676 kb
Host smart-8ae11d49-531c-413b-b0cd-0ef665dd7928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443708218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3443708218
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3899652784
Short name T116
Test name
Test status
Simulation time 4518200560 ps
CPU time 12.63 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:31 PM PDT 24
Peak memory 201964 kb
Host smart-3ad9a003-d251-450a-9f89-1e8db4f9c671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899652784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3899652784
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2486949454
Short name T904
Test name
Test status
Simulation time 682029883 ps
CPU time 2.68 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201972 kb
Host smart-32a7d5a7-67d6-4583-b401-7c5c6d72385c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486949454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2486949454
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.189856029
Short name T69
Test name
Test status
Simulation time 4418839285 ps
CPU time 4.81 seconds
Started May 14 01:22:17 PM PDT 24
Finished May 14 01:22:23 PM PDT 24
Peak memory 201292 kb
Host smart-c4856802-5159-40d8-8949-fe7569e99a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189856029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.189856029
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3343752242
Short name T825
Test name
Test status
Simulation time 414677660 ps
CPU time 1.86 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201724 kb
Host smart-42de3cb6-27b6-4e98-9049-41ba2952a5fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343752242 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3343752242
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3641746817
Short name T887
Test name
Test status
Simulation time 304405454 ps
CPU time 1.17 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201672 kb
Host smart-ff11cc1e-8ffc-4619-b149-a1d6a3840317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641746817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3641746817
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1747770558
Short name T856
Test name
Test status
Simulation time 414149347 ps
CPU time 0.76 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:17 PM PDT 24
Peak memory 201680 kb
Host smart-727044a8-0f3e-4490-9136-917668921e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747770558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1747770558
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1375462986
Short name T880
Test name
Test status
Simulation time 4610070418 ps
CPU time 10.71 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:28 PM PDT 24
Peak memory 201868 kb
Host smart-7889b87d-f48b-483f-953a-665bb4093a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375462986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1375462986
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.361979659
Short name T53
Test name
Test status
Simulation time 818879011 ps
CPU time 2.23 seconds
Started May 14 01:22:19 PM PDT 24
Finished May 14 01:22:22 PM PDT 24
Peak memory 201868 kb
Host smart-965b5a61-ebb6-4248-9555-c8223754f3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361979659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.361979659
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1757631089
Short name T894
Test name
Test status
Simulation time 556473325 ps
CPU time 2.07 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:18 PM PDT 24
Peak memory 201708 kb
Host smart-043fff17-81dc-4dcd-89a0-0913ea109dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757631089 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1757631089
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.384019591
Short name T119
Test name
Test status
Simulation time 372209409 ps
CPU time 0.92 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:14 PM PDT 24
Peak memory 201708 kb
Host smart-9d5389c5-8b2e-4596-9b0c-1864988c5256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384019591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.384019591
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3461554766
Short name T913
Test name
Test status
Simulation time 442131436 ps
CPU time 0.91 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:16 PM PDT 24
Peak memory 201584 kb
Host smart-8fd4bdb6-8e4d-48b8-9680-a4cf3ff7b2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461554766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3461554766
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2751644315
Short name T821
Test name
Test status
Simulation time 4336416881 ps
CPU time 17.57 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201940 kb
Host smart-acb070c9-9782-4eb2-abfb-a1bb0e202007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751644315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2751644315
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2864487960
Short name T891
Test name
Test status
Simulation time 574877053 ps
CPU time 2.08 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:18 PM PDT 24
Peak memory 201948 kb
Host smart-9ca81562-aa97-443c-bd18-49d385ac531e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864487960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2864487960
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3257319335
Short name T42
Test name
Test status
Simulation time 4198031308 ps
CPU time 12.31 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:28 PM PDT 24
Peak memory 201952 kb
Host smart-c5bf3cf4-0619-4f8a-a936-c9829923c796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257319335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3257319335
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.409772114
Short name T811
Test name
Test status
Simulation time 502610177 ps
CPU time 2.15 seconds
Started May 14 01:22:17 PM PDT 24
Finished May 14 01:22:21 PM PDT 24
Peak memory 201732 kb
Host smart-3bf432cf-6e87-4d76-9cc8-894314e118bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409772114 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.409772114
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3614182919
Short name T105
Test name
Test status
Simulation time 399205510 ps
CPU time 0.95 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:15 PM PDT 24
Peak memory 201720 kb
Host smart-a78e5e37-6a33-4fba-8c3e-4da7e6e2a540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614182919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3614182919
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3605010030
Short name T863
Test name
Test status
Simulation time 448662995 ps
CPU time 1.49 seconds
Started May 14 01:22:13 PM PDT 24
Finished May 14 01:22:16 PM PDT 24
Peak memory 201692 kb
Host smart-87aa2421-3d9d-40dd-be0f-0298edccc7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605010030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3605010030
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2275405370
Short name T851
Test name
Test status
Simulation time 1928959268 ps
CPU time 4.63 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201652 kb
Host smart-b3b2ab4c-19d0-4882-a554-498d412c5a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275405370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2275405370
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1536494484
Short name T868
Test name
Test status
Simulation time 585952152 ps
CPU time 2.53 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 218248 kb
Host smart-29b03eef-32f4-4b9e-a3b7-dabeb4476cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536494484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1536494484
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2987020028
Short name T61
Test name
Test status
Simulation time 9450746719 ps
CPU time 7.78 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:26 PM PDT 24
Peak memory 201956 kb
Host smart-570d3291-152d-4dc9-9c9e-add7321bf329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987020028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2987020028
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1209394401
Short name T838
Test name
Test status
Simulation time 376049672 ps
CPU time 1.25 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:17 PM PDT 24
Peak memory 201744 kb
Host smart-39587134-31e5-4dd9-897f-df09b57c65d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209394401 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1209394401
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2201446262
Short name T854
Test name
Test status
Simulation time 465850344 ps
CPU time 1.01 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201692 kb
Host smart-8705104e-6afe-4a2a-96de-df25be53518f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201446262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2201446262
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2754202919
Short name T837
Test name
Test status
Simulation time 468236653 ps
CPU time 0.71 seconds
Started May 14 01:22:18 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201656 kb
Host smart-92286946-4f16-4356-be07-88537bcab57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754202919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2754202919
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1134049755
Short name T853
Test name
Test status
Simulation time 2446400513 ps
CPU time 5.22 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:21 PM PDT 24
Peak memory 201740 kb
Host smart-c0b45362-bd74-44f5-852d-d0bb6c82dce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134049755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1134049755
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.567116807
Short name T845
Test name
Test status
Simulation time 390376915 ps
CPU time 2.67 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:18 PM PDT 24
Peak memory 201988 kb
Host smart-c7450800-81b3-4c5b-be3c-ebc887a16068
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567116807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.567116807
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2562137175
Short name T865
Test name
Test status
Simulation time 4985372669 ps
CPU time 12.67 seconds
Started May 14 01:22:14 PM PDT 24
Finished May 14 01:22:29 PM PDT 24
Peak memory 201868 kb
Host smart-cb1be4ac-ebac-40ed-8a47-2263f2652984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562137175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2562137175
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3858046542
Short name T879
Test name
Test status
Simulation time 867976239 ps
CPU time 4.11 seconds
Started May 14 01:21:30 PM PDT 24
Finished May 14 01:21:36 PM PDT 24
Peak memory 201864 kb
Host smart-b5f55f7c-06b6-444a-8cb7-da2d90c26f6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858046542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3858046542
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1059150646
Short name T885
Test name
Test status
Simulation time 27219927471 ps
CPU time 16.48 seconds
Started May 14 01:21:30 PM PDT 24
Finished May 14 01:21:48 PM PDT 24
Peak memory 201896 kb
Host smart-2ab42da8-24d2-4a64-ba18-d5f61bf77edb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059150646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1059150646
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2720222808
Short name T104
Test name
Test status
Simulation time 1034794372 ps
CPU time 2.32 seconds
Started May 14 01:21:29 PM PDT 24
Finished May 14 01:21:33 PM PDT 24
Peak memory 201700 kb
Host smart-7beec47a-fa99-49bf-ad9a-ad4e6f2281ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720222808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2720222808
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2835039659
Short name T64
Test name
Test status
Simulation time 598620456 ps
CPU time 1.3 seconds
Started May 14 01:21:34 PM PDT 24
Finished May 14 01:21:36 PM PDT 24
Peak memory 201736 kb
Host smart-477ca34a-defe-451e-bd9d-7a7ea00e0de7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835039659 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2835039659
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1689413410
Short name T114
Test name
Test status
Simulation time 465318861 ps
CPU time 1.07 seconds
Started May 14 01:21:29 PM PDT 24
Finished May 14 01:21:31 PM PDT 24
Peak memory 201736 kb
Host smart-8e448940-de8d-4303-b656-5815db02f404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689413410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1689413410
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1201558434
Short name T864
Test name
Test status
Simulation time 405751792 ps
CPU time 1.6 seconds
Started May 14 01:21:33 PM PDT 24
Finished May 14 01:21:35 PM PDT 24
Peak memory 201704 kb
Host smart-78007c43-fab0-4e5d-a240-689db299a8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201558434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1201558434
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1148619630
Short name T841
Test name
Test status
Simulation time 4414872783 ps
CPU time 5.82 seconds
Started May 14 01:21:30 PM PDT 24
Finished May 14 01:21:38 PM PDT 24
Peak memory 202020 kb
Host smart-289ec3d1-39b6-49c6-b7a6-ed936f64f9d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148619630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1148619630
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.805210630
Short name T907
Test name
Test status
Simulation time 945517963 ps
CPU time 2.45 seconds
Started May 14 01:21:31 PM PDT 24
Finished May 14 01:21:35 PM PDT 24
Peak memory 211136 kb
Host smart-03ecaa32-ed68-476d-a273-1981156985df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805210630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.805210630
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.862190019
Short name T860
Test name
Test status
Simulation time 4214435692 ps
CPU time 11.54 seconds
Started May 14 01:21:33 PM PDT 24
Finished May 14 01:21:45 PM PDT 24
Peak memory 201964 kb
Host smart-6f7d3352-d2a2-4e02-98b6-908c9da19ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862190019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.862190019
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1714403582
Short name T805
Test name
Test status
Simulation time 295587447 ps
CPU time 1.33 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:20 PM PDT 24
Peak memory 201676 kb
Host smart-cd55677f-be9a-4b8c-b319-e07e6bfad7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714403582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1714403582
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4081912815
Short name T892
Test name
Test status
Simulation time 479894082 ps
CPU time 1.8 seconds
Started May 14 01:22:12 PM PDT 24
Finished May 14 01:22:14 PM PDT 24
Peak memory 201616 kb
Host smart-1fd17b97-0e96-4a49-bc09-bdff1400ea27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081912815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4081912815
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1114150823
Short name T866
Test name
Test status
Simulation time 453279603 ps
CPU time 1.44 seconds
Started May 14 01:22:16 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201640 kb
Host smart-c3a22a4e-4257-4901-a31b-67ee0841511e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114150823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1114150823
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4145825929
Short name T918
Test name
Test status
Simulation time 423737649 ps
CPU time 1.61 seconds
Started May 14 01:22:15 PM PDT 24
Finished May 14 01:22:19 PM PDT 24
Peak memory 201620 kb
Host smart-7fad273f-70e0-4175-8226-5acb0561218a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145825929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4145825929
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.636661493
Short name T906
Test name
Test status
Simulation time 312680787 ps
CPU time 1.39 seconds
Started May 14 01:22:18 PM PDT 24
Finished May 14 01:22:21 PM PDT 24
Peak memory 201672 kb
Host smart-3b538996-a56a-4873-aec2-44496e497887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636661493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.636661493
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1561010805
Short name T828
Test name
Test status
Simulation time 481770825 ps
CPU time 0.98 seconds
Started May 14 01:22:23 PM PDT 24
Finished May 14 01:22:25 PM PDT 24
Peak memory 201692 kb
Host smart-48749cd8-c656-4a84-a861-7aa08832e3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561010805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1561010805
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2293945563
Short name T803
Test name
Test status
Simulation time 446614917 ps
CPU time 1.53 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201684 kb
Host smart-e1724efe-a958-4213-b12c-5af662e35dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293945563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2293945563
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3344749024
Short name T809
Test name
Test status
Simulation time 285989039 ps
CPU time 1.33 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201624 kb
Host smart-f9ee9c6c-65cf-420a-847d-41ca6ea81486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344749024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3344749024
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.556231990
Short name T836
Test name
Test status
Simulation time 333865700 ps
CPU time 1.36 seconds
Started May 14 01:22:32 PM PDT 24
Finished May 14 01:22:35 PM PDT 24
Peak memory 201672 kb
Host smart-b4411258-f881-464b-9fee-4492ad4b46aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556231990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.556231990
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3150792274
Short name T812
Test name
Test status
Simulation time 531837294 ps
CPU time 1.85 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201904 kb
Host smart-c89ed0a5-bd6a-4045-a7c7-b2c092c0e072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150792274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3150792274
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4145670203
Short name T109
Test name
Test status
Simulation time 1167379556 ps
CPU time 5.02 seconds
Started May 14 01:21:30 PM PDT 24
Finished May 14 01:21:36 PM PDT 24
Peak memory 201944 kb
Host smart-046ec0e6-326f-4f1c-80d7-92a769c88db0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145670203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4145670203
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3879415690
Short name T112
Test name
Test status
Simulation time 17121439041 ps
CPU time 72.66 seconds
Started May 14 01:21:31 PM PDT 24
Finished May 14 01:22:45 PM PDT 24
Peak memory 201968 kb
Host smart-d3834e8e-6fb5-43f6-bf92-eb6b0d24ab3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879415690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3879415690
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.213383553
Short name T100
Test name
Test status
Simulation time 1199091618 ps
CPU time 2.8 seconds
Started May 14 01:21:29 PM PDT 24
Finished May 14 01:21:33 PM PDT 24
Peak memory 201684 kb
Host smart-f2f8d93e-ad62-40fc-b96c-7c833642db31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213383553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.213383553
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.697193412
Short name T889
Test name
Test status
Simulation time 542312910 ps
CPU time 1.39 seconds
Started May 14 01:21:30 PM PDT 24
Finished May 14 01:21:33 PM PDT 24
Peak memory 201956 kb
Host smart-1daa0caf-c1e4-4098-8e32-4c7f3f0fc10e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697193412 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.697193412
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.266969345
Short name T120
Test name
Test status
Simulation time 537995236 ps
CPU time 0.97 seconds
Started May 14 01:21:31 PM PDT 24
Finished May 14 01:21:33 PM PDT 24
Peak memory 201712 kb
Host smart-37d76e61-a2a2-427f-9c14-acc63b33051a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266969345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.266969345
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4040520922
Short name T822
Test name
Test status
Simulation time 519094306 ps
CPU time 1.26 seconds
Started May 14 01:21:34 PM PDT 24
Finished May 14 01:21:37 PM PDT 24
Peak memory 201540 kb
Host smart-3484506f-f61a-42c5-a541-2a784e936c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040520922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4040520922
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2353566816
Short name T881
Test name
Test status
Simulation time 2277814661 ps
CPU time 8.14 seconds
Started May 14 01:21:29 PM PDT 24
Finished May 14 01:21:38 PM PDT 24
Peak memory 201732 kb
Host smart-c1317309-a787-43f2-a46e-1d82295ab023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353566816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2353566816
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2295227760
Short name T867
Test name
Test status
Simulation time 1095112143 ps
CPU time 2.53 seconds
Started May 14 01:21:30 PM PDT 24
Finished May 14 01:21:35 PM PDT 24
Peak memory 218000 kb
Host smart-55f0af71-4534-4108-bf4b-cddbc36f6371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295227760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2295227760
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2658266192
Short name T850
Test name
Test status
Simulation time 4730038484 ps
CPU time 4.19 seconds
Started May 14 01:21:34 PM PDT 24
Finished May 14 01:21:39 PM PDT 24
Peak memory 201968 kb
Host smart-889535ac-780c-4bc0-a3e9-69ddc27b37ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658266192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2658266192
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1276144175
Short name T806
Test name
Test status
Simulation time 508954513 ps
CPU time 1.17 seconds
Started May 14 01:22:32 PM PDT 24
Finished May 14 01:22:34 PM PDT 24
Peak memory 201616 kb
Host smart-890c9df3-1592-4857-a9d4-c07c648a8d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276144175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1276144175
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3451703806
Short name T814
Test name
Test status
Simulation time 441313597 ps
CPU time 0.93 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201628 kb
Host smart-721fbc91-44da-4bb3-8f0b-f1c395c5943e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451703806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3451703806
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3030912893
Short name T847
Test name
Test status
Simulation time 464326550 ps
CPU time 1.74 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201648 kb
Host smart-cf6a09ff-f2ac-4e3c-be99-fb81cb1fd522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030912893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3030912893
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1814220019
Short name T849
Test name
Test status
Simulation time 574962747 ps
CPU time 0.8 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201660 kb
Host smart-b215e9f5-046a-4c4f-a98f-0021f1df56f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814220019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1814220019
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1954189177
Short name T830
Test name
Test status
Simulation time 500624601 ps
CPU time 0.97 seconds
Started May 14 01:22:34 PM PDT 24
Finished May 14 01:22:38 PM PDT 24
Peak memory 201668 kb
Host smart-2bba4e85-ba5e-4ee8-808f-8cae73ae18a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954189177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1954189177
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1601483742
Short name T835
Test name
Test status
Simulation time 292025886 ps
CPU time 1.31 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201652 kb
Host smart-ce5f0c47-bbd0-4cbf-80c3-56752906a598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601483742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1601483742
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3960762420
Short name T862
Test name
Test status
Simulation time 451512054 ps
CPU time 1.6 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201676 kb
Host smart-b44a5b66-d796-47fc-8eec-f5f31da8d5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960762420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3960762420
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2798106300
Short name T815
Test name
Test status
Simulation time 443023152 ps
CPU time 1.73 seconds
Started May 14 01:22:35 PM PDT 24
Finished May 14 01:22:40 PM PDT 24
Peak memory 201680 kb
Host smart-ca90c1d6-05ad-41fa-ac0a-442739f52319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798106300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2798106300
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1321059802
Short name T820
Test name
Test status
Simulation time 471939557 ps
CPU time 0.88 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:35 PM PDT 24
Peak memory 201620 kb
Host smart-d3d10b94-64d0-4d1c-9fe1-c8cf666bb307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321059802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1321059802
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1422745822
Short name T909
Test name
Test status
Simulation time 291722533 ps
CPU time 1.38 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201640 kb
Host smart-0318fdf2-2444-4b94-a6b6-40d207935f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422745822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1422745822
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3204684910
Short name T916
Test name
Test status
Simulation time 681781846 ps
CPU time 3.02 seconds
Started May 14 01:21:40 PM PDT 24
Finished May 14 01:21:43 PM PDT 24
Peak memory 201840 kb
Host smart-583bc64b-2362-43b9-8825-17d7c6648383
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204684910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3204684910
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3757378017
Short name T38
Test name
Test status
Simulation time 27106445534 ps
CPU time 46.15 seconds
Started May 14 01:21:40 PM PDT 24
Finished May 14 01:22:28 PM PDT 24
Peak memory 201928 kb
Host smart-09e883e3-fcf3-4e13-8e3c-5da4bc318adb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757378017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3757378017
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.111223049
Short name T844
Test name
Test status
Simulation time 787282580 ps
CPU time 2.41 seconds
Started May 14 01:21:34 PM PDT 24
Finished May 14 01:21:37 PM PDT 24
Peak memory 201548 kb
Host smart-555a8105-94b6-429e-8c20-f6a7af76a15f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111223049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.111223049
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3102633311
Short name T839
Test name
Test status
Simulation time 591818726 ps
CPU time 1.2 seconds
Started May 14 01:21:40 PM PDT 24
Finished May 14 01:21:43 PM PDT 24
Peak memory 201756 kb
Host smart-c7ea1fd7-a8b8-4597-89dc-181b988fe97a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102633311 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3102633311
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2977700222
Short name T917
Test name
Test status
Simulation time 524139754 ps
CPU time 1.43 seconds
Started May 14 01:21:42 PM PDT 24
Finished May 14 01:21:46 PM PDT 24
Peak memory 201704 kb
Host smart-da3876a6-88d5-4a95-9f9b-40e64f10786a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977700222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2977700222
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3615263373
Short name T832
Test name
Test status
Simulation time 421187435 ps
CPU time 1.56 seconds
Started May 14 01:21:34 PM PDT 24
Finished May 14 01:21:37 PM PDT 24
Peak memory 201536 kb
Host smart-9c81312a-7b0c-4d21-9b3c-8078715c34ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615263373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3615263373
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4256320546
Short name T831
Test name
Test status
Simulation time 3853881552 ps
CPU time 4.49 seconds
Started May 14 01:21:42 PM PDT 24
Finished May 14 01:21:49 PM PDT 24
Peak memory 201960 kb
Host smart-968886dd-ca6a-4acb-82ea-76e14fe05ee1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256320546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4256320546
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.691673726
Short name T896
Test name
Test status
Simulation time 547301706 ps
CPU time 2.25 seconds
Started May 14 01:21:31 PM PDT 24
Finished May 14 01:21:35 PM PDT 24
Peak memory 201876 kb
Host smart-6d065a5a-86e0-4080-bad0-1de6d7c27eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691673726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.691673726
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2901696855
Short name T70
Test name
Test status
Simulation time 8354590897 ps
CPU time 8.03 seconds
Started May 14 01:21:33 PM PDT 24
Finished May 14 01:21:42 PM PDT 24
Peak memory 201900 kb
Host smart-dafa69dd-26ba-4e34-a181-e41451222264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901696855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2901696855
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.589910928
Short name T905
Test name
Test status
Simulation time 552992606 ps
CPU time 1.04 seconds
Started May 14 01:22:32 PM PDT 24
Finished May 14 01:22:34 PM PDT 24
Peak memory 201692 kb
Host smart-b90a6f03-092a-437a-818e-a0f9d533c0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589910928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.589910928
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.310048408
Short name T801
Test name
Test status
Simulation time 461183214 ps
CPU time 0.92 seconds
Started May 14 01:22:34 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201700 kb
Host smart-eec40781-1d08-4cc7-b603-605e0f7b8a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310048408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.310048408
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.767107800
Short name T912
Test name
Test status
Simulation time 510690587 ps
CPU time 1.81 seconds
Started May 14 01:22:34 PM PDT 24
Finished May 14 01:22:38 PM PDT 24
Peak memory 201648 kb
Host smart-1674628a-e65a-44a7-95e8-1a60a2d5d5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767107800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.767107800
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3284536440
Short name T875
Test name
Test status
Simulation time 451832757 ps
CPU time 1.82 seconds
Started May 14 01:22:35 PM PDT 24
Finished May 14 01:22:40 PM PDT 24
Peak memory 201640 kb
Host smart-fa221c98-152e-4b3b-b360-41a9a5d8ffc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284536440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3284536440
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3643593544
Short name T870
Test name
Test status
Simulation time 492033355 ps
CPU time 0.71 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201680 kb
Host smart-4f443f7e-016d-4d88-a698-d907a889b537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643593544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3643593544
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1833836707
Short name T819
Test name
Test status
Simulation time 350464296 ps
CPU time 0.74 seconds
Started May 14 01:22:34 PM PDT 24
Finished May 14 01:22:37 PM PDT 24
Peak memory 201668 kb
Host smart-bcd70064-fce8-4444-8446-4c71bfb33de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833836707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1833836707
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.639101012
Short name T802
Test name
Test status
Simulation time 339403076 ps
CPU time 1.5 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201680 kb
Host smart-21ba3092-5090-4363-9866-719b28071ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639101012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.639101012
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.114087085
Short name T857
Test name
Test status
Simulation time 505814174 ps
CPU time 0.97 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:36 PM PDT 24
Peak memory 201672 kb
Host smart-4526d246-1df8-4eee-9f88-35c9de9a56f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114087085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.114087085
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3298577345
Short name T810
Test name
Test status
Simulation time 328644524 ps
CPU time 1.01 seconds
Started May 14 01:22:33 PM PDT 24
Finished May 14 01:22:35 PM PDT 24
Peak memory 201692 kb
Host smart-09e1c80f-84d2-4dfd-8e6d-934b0aaad4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298577345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3298577345
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2950065555
Short name T829
Test name
Test status
Simulation time 556138663 ps
CPU time 0.74 seconds
Started May 14 01:22:35 PM PDT 24
Finished May 14 01:22:39 PM PDT 24
Peak memory 201660 kb
Host smart-6524fefb-1fdf-48a6-8ebc-e407df283f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950065555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2950065555
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2314613806
Short name T876
Test name
Test status
Simulation time 662099019 ps
CPU time 1.13 seconds
Started May 14 01:21:40 PM PDT 24
Finished May 14 01:21:42 PM PDT 24
Peak memory 201736 kb
Host smart-c9eac8c0-e87c-4eed-a984-f0233420cab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314613806 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2314613806
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3921897860
Short name T102
Test name
Test status
Simulation time 447136701 ps
CPU time 1.77 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:44 PM PDT 24
Peak memory 201668 kb
Host smart-908ffda9-c4bb-4b62-b358-b66f1d9cb39e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921897860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3921897860
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.163966119
Short name T826
Test name
Test status
Simulation time 493152798 ps
CPU time 1.71 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:45 PM PDT 24
Peak memory 201576 kb
Host smart-ce942501-0f72-4f69-83b9-9144cc8f1ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163966119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.163966119
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3605653424
Short name T890
Test name
Test status
Simulation time 3776625451 ps
CPU time 15.34 seconds
Started May 14 01:21:42 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201924 kb
Host smart-a38fa673-9493-4823-af92-bd447a8399c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605653424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3605653424
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.540370742
Short name T908
Test name
Test status
Simulation time 576551651 ps
CPU time 2.45 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:44 PM PDT 24
Peak memory 218268 kb
Host smart-535de972-db0a-4ee5-b25e-b1c9bbf8cde7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540370742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.540370742
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2447849005
Short name T886
Test name
Test status
Simulation time 8132332949 ps
CPU time 18.32 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:22:01 PM PDT 24
Peak memory 201868 kb
Host smart-ae38dcc6-e514-43b0-bc69-f494d65436f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447849005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2447849005
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1206427860
Short name T65
Test name
Test status
Simulation time 613688924 ps
CPU time 0.88 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:43 PM PDT 24
Peak memory 201664 kb
Host smart-e944daab-5ca9-4917-8268-990942d6bcf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206427860 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1206427860
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2909010747
Short name T878
Test name
Test status
Simulation time 355992919 ps
CPU time 1.59 seconds
Started May 14 01:21:40 PM PDT 24
Finished May 14 01:21:42 PM PDT 24
Peak memory 201636 kb
Host smart-56f93f2d-a5b7-4f34-8b33-1af6b4f305fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909010747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2909010747
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4177861221
Short name T842
Test name
Test status
Simulation time 467865877 ps
CPU time 1.19 seconds
Started May 14 01:21:42 PM PDT 24
Finished May 14 01:21:45 PM PDT 24
Peak memory 201688 kb
Host smart-91ee7cd9-369e-4def-89ff-278e520184e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177861221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4177861221
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.836965560
Short name T901
Test name
Test status
Simulation time 2506634453 ps
CPU time 2.19 seconds
Started May 14 01:21:42 PM PDT 24
Finished May 14 01:21:46 PM PDT 24
Peak memory 201764 kb
Host smart-05d855b8-8cb7-44d7-a719-b1d583f4ab35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836965560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.836965560
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3074007150
Short name T873
Test name
Test status
Simulation time 728404845 ps
CPU time 2.19 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:44 PM PDT 24
Peak memory 201912 kb
Host smart-1b53234a-e4b7-4e58-b01e-f7c5b5a9207e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074007150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3074007150
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1157780961
Short name T833
Test name
Test status
Simulation time 4325758485 ps
CPU time 11.84 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:55 PM PDT 24
Peak memory 201960 kb
Host smart-4570ab94-6185-4ceb-95f2-505bcc8520fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157780961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1157780961
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1308506800
Short name T62
Test name
Test status
Simulation time 419219088 ps
CPU time 1.37 seconds
Started May 14 01:21:58 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201748 kb
Host smart-13be696e-4c31-46ad-830e-4765b1357bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308506800 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1308506800
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3498535827
Short name T110
Test name
Test status
Simulation time 542682115 ps
CPU time 1.4 seconds
Started May 14 01:21:56 PM PDT 24
Finished May 14 01:21:57 PM PDT 24
Peak memory 201676 kb
Host smart-7db75b0f-9aee-4274-b09e-3856809308c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498535827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3498535827
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.787542702
Short name T827
Test name
Test status
Simulation time 305048809 ps
CPU time 0.78 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:21:59 PM PDT 24
Peak memory 201680 kb
Host smart-a5a216d2-c359-42c9-a004-cf39cab05428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787542702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.787542702
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3258367052
Short name T848
Test name
Test status
Simulation time 4690919441 ps
CPU time 10.76 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:09 PM PDT 24
Peak memory 201928 kb
Host smart-4c826260-7c60-489e-b68e-c0ba8ee43267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258367052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3258367052
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.839180734
Short name T899
Test name
Test status
Simulation time 547893981 ps
CPU time 1.73 seconds
Started May 14 01:21:41 PM PDT 24
Finished May 14 01:21:44 PM PDT 24
Peak memory 201932 kb
Host smart-3a796eb0-30e3-426b-887c-8345510136f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839180734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.839180734
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3630237567
Short name T895
Test name
Test status
Simulation time 8807651459 ps
CPU time 7.13 seconds
Started May 14 01:21:40 PM PDT 24
Finished May 14 01:21:48 PM PDT 24
Peak memory 201908 kb
Host smart-a3e0f8a5-c543-4cdf-b019-148d813158ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630237567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3630237567
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4162836840
Short name T840
Test name
Test status
Simulation time 526690059 ps
CPU time 1.99 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201716 kb
Host smart-e94a2bd7-beeb-465d-b9eb-f4b9e387c128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162836840 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4162836840
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2653020400
Short name T118
Test name
Test status
Simulation time 596559320 ps
CPU time 0.77 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:21:59 PM PDT 24
Peak memory 201672 kb
Host smart-b158a2e8-fb00-4b49-9f11-e64fc3c7c5e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653020400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2653020400
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1967483702
Short name T824
Test name
Test status
Simulation time 472298332 ps
CPU time 0.81 seconds
Started May 14 01:21:58 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201700 kb
Host smart-cba6bb41-b6fd-4804-8ee4-9270ad07d063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967483702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1967483702
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3868731194
Short name T871
Test name
Test status
Simulation time 4610933307 ps
CPU time 16.08 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:14 PM PDT 24
Peak memory 201980 kb
Host smart-cfc7f22c-cf48-42a7-bf60-eadc76f1bfdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868731194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3868731194
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2455413128
Short name T903
Test name
Test status
Simulation time 480279653 ps
CPU time 3.32 seconds
Started May 14 01:21:58 PM PDT 24
Finished May 14 01:22:02 PM PDT 24
Peak memory 217824 kb
Host smart-089fa317-436f-42f5-93e0-80389915ce4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455413128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2455413128
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2035614049
Short name T68
Test name
Test status
Simulation time 509453659 ps
CPU time 1.25 seconds
Started May 14 01:21:58 PM PDT 24
Finished May 14 01:22:01 PM PDT 24
Peak memory 201736 kb
Host smart-84c7c700-c32c-427c-ba96-5df1b7777cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035614049 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2035614049
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.155082388
Short name T902
Test name
Test status
Simulation time 711339778 ps
CPU time 0.93 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:21:59 PM PDT 24
Peak memory 201596 kb
Host smart-49c84337-43a9-4168-b65a-7b892330e541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155082388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.155082388
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.84400699
Short name T874
Test name
Test status
Simulation time 520256669 ps
CPU time 0.84 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:21:59 PM PDT 24
Peak memory 201656 kb
Host smart-5dbd51aa-000e-4b59-b63d-1c03ae76f046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84400699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.84400699
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2473225311
Short name T915
Test name
Test status
Simulation time 2208392085 ps
CPU time 2.19 seconds
Started May 14 01:21:57 PM PDT 24
Finished May 14 01:22:00 PM PDT 24
Peak memory 201668 kb
Host smart-e13f29d1-0ccf-4738-ba1f-8afbd2dfac0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473225311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2473225311
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2129670400
Short name T869
Test name
Test status
Simulation time 390294783 ps
CPU time 2.89 seconds
Started May 14 01:21:58 PM PDT 24
Finished May 14 01:22:01 PM PDT 24
Peak memory 202204 kb
Host smart-ec184f7e-65a9-4931-8ca5-53b7f5353155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129670400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2129670400
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3395499964
Short name T898
Test name
Test status
Simulation time 8233466051 ps
CPU time 22.59 seconds
Started May 14 01:21:58 PM PDT 24
Finished May 14 01:22:22 PM PDT 24
Peak memory 201964 kb
Host smart-2c09a715-1721-4dc0-9a8b-2979e7c75944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395499964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3395499964
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.955575234
Short name T582
Test name
Test status
Simulation time 510730431 ps
CPU time 0.81 seconds
Started May 14 02:56:56 PM PDT 24
Finished May 14 02:56:58 PM PDT 24
Peak memory 201576 kb
Host smart-31f1a425-55b2-42a4-b88c-3b5796d3952d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955575234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.955575234
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1584314044
Short name T323
Test name
Test status
Simulation time 502805762253 ps
CPU time 415.58 seconds
Started May 14 02:56:50 PM PDT 24
Finished May 14 03:03:46 PM PDT 24
Peak memory 201792 kb
Host smart-e2701734-1ce3-499a-bf34-81fb1a41173d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584314044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1584314044
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3451732464
Short name T621
Test name
Test status
Simulation time 350589180552 ps
CPU time 430.68 seconds
Started May 14 02:56:47 PM PDT 24
Finished May 14 03:03:59 PM PDT 24
Peak memory 201808 kb
Host smart-94b14809-1481-4893-90d7-3ccff4f614f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451732464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3451732464
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2938518846
Short name T221
Test name
Test status
Simulation time 166725989646 ps
CPU time 153.76 seconds
Started May 14 02:56:46 PM PDT 24
Finished May 14 02:59:21 PM PDT 24
Peak memory 201872 kb
Host smart-435071a2-4e07-4ad2-a08c-356f04eaee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938518846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2938518846
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2176319272
Short name T712
Test name
Test status
Simulation time 161450078355 ps
CPU time 199.14 seconds
Started May 14 02:56:48 PM PDT 24
Finished May 14 03:00:09 PM PDT 24
Peak memory 201848 kb
Host smart-1cbdd5ee-6b50-4039-b87f-3e826a5a262c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176319272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2176319272
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2359114883
Short name T659
Test name
Test status
Simulation time 169975563286 ps
CPU time 28.36 seconds
Started May 14 02:56:47 PM PDT 24
Finished May 14 02:57:17 PM PDT 24
Peak memory 201880 kb
Host smart-d7eccbc3-28a9-482a-b3d6-d8d3e3155c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359114883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2359114883
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1933401700
Short name T479
Test name
Test status
Simulation time 333338120207 ps
CPU time 737.06 seconds
Started May 14 02:56:48 PM PDT 24
Finished May 14 03:09:06 PM PDT 24
Peak memory 201788 kb
Host smart-91faf6ef-629d-44fa-a5f7-69252b0ca4ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933401700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1933401700
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.166066012
Short name T142
Test name
Test status
Simulation time 197938503067 ps
CPU time 423.27 seconds
Started May 14 02:56:47 PM PDT 24
Finished May 14 03:03:52 PM PDT 24
Peak memory 201804 kb
Host smart-741c3b8e-3ade-4230-adbd-a45a285c18fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166066012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.166066012
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1658958720
Short name T159
Test name
Test status
Simulation time 604215828988 ps
CPU time 96.99 seconds
Started May 14 02:56:47 PM PDT 24
Finished May 14 02:58:25 PM PDT 24
Peak memory 201832 kb
Host smart-9c22a288-eb2a-43a0-ae70-6ae786a85f50
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658958720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1658958720
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2512635398
Short name T519
Test name
Test status
Simulation time 112562051884 ps
CPU time 360.54 seconds
Started May 14 02:56:58 PM PDT 24
Finished May 14 03:02:59 PM PDT 24
Peak memory 202036 kb
Host smart-cbb5aaaf-c994-4838-8a0e-e422b2853f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512635398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2512635398
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2449016131
Short name T537
Test name
Test status
Simulation time 41100929197 ps
CPU time 46.32 seconds
Started May 14 02:56:55 PM PDT 24
Finished May 14 02:57:42 PM PDT 24
Peak memory 201576 kb
Host smart-443882c6-07b8-426a-b053-118dbe5366e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449016131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2449016131
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3306750036
Short name T658
Test name
Test status
Simulation time 4219607710 ps
CPU time 2.95 seconds
Started May 14 02:56:48 PM PDT 24
Finished May 14 02:56:53 PM PDT 24
Peak memory 201556 kb
Host smart-ec97757b-0b12-404c-aff6-71f387ee4bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306750036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3306750036
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.144909543
Short name T790
Test name
Test status
Simulation time 5697024355 ps
CPU time 4.43 seconds
Started May 14 02:56:50 PM PDT 24
Finished May 14 02:56:55 PM PDT 24
Peak memory 201616 kb
Host smart-0c7970b4-044f-4d65-a593-eff5a0712030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144909543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.144909543
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.607597813
Short name T436
Test name
Test status
Simulation time 98913612863 ps
CPU time 282.19 seconds
Started May 14 02:56:56 PM PDT 24
Finished May 14 03:01:39 PM PDT 24
Peak memory 202112 kb
Host smart-81a19918-52e9-4b97-abdf-969e2915113c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607597813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.607597813
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2957857689
Short name T668
Test name
Test status
Simulation time 538665152 ps
CPU time 0.96 seconds
Started May 14 02:57:16 PM PDT 24
Finished May 14 02:57:18 PM PDT 24
Peak memory 201444 kb
Host smart-a7cbb4bd-2b6b-427d-a3a9-b0bf8a46e79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957857689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2957857689
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2820370616
Short name T32
Test name
Test status
Simulation time 196700830354 ps
CPU time 335.02 seconds
Started May 14 02:57:06 PM PDT 24
Finished May 14 03:02:42 PM PDT 24
Peak memory 201852 kb
Host smart-5686feb6-76e3-45d4-a8bc-c7dc59d0ce4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820370616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2820370616
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1091783318
Short name T739
Test name
Test status
Simulation time 347745326204 ps
CPU time 217.28 seconds
Started May 14 02:57:05 PM PDT 24
Finished May 14 03:00:43 PM PDT 24
Peak memory 201728 kb
Host smart-c241b2ba-e097-4a14-b68d-e1962dff7197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091783318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1091783318
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2159395107
Short name T322
Test name
Test status
Simulation time 169116925037 ps
CPU time 105.64 seconds
Started May 14 02:57:05 PM PDT 24
Finished May 14 02:58:51 PM PDT 24
Peak memory 201872 kb
Host smart-04d964df-0fb7-48cc-9e3d-b1850abfd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159395107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2159395107
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2346425682
Short name T432
Test name
Test status
Simulation time 493857923715 ps
CPU time 340.68 seconds
Started May 14 02:57:06 PM PDT 24
Finished May 14 03:02:48 PM PDT 24
Peak memory 201684 kb
Host smart-eb5651e5-cbdf-4f01-b788-722a551a08c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346425682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2346425682
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1465667908
Short name T183
Test name
Test status
Simulation time 317646845744 ps
CPU time 188.98 seconds
Started May 14 02:56:56 PM PDT 24
Finished May 14 03:00:06 PM PDT 24
Peak memory 201784 kb
Host smart-638b42a2-f361-4647-bb68-0fd6a767b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465667908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1465667908
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.17738292
Short name T714
Test name
Test status
Simulation time 162072054382 ps
CPU time 403.63 seconds
Started May 14 02:56:55 PM PDT 24
Finished May 14 03:03:40 PM PDT 24
Peak memory 201856 kb
Host smart-ced4def4-1238-466b-9322-a16e9a15d800
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=17738292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.17738292
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.676974484
Short name T696
Test name
Test status
Simulation time 381157178979 ps
CPU time 884.07 seconds
Started May 14 02:57:07 PM PDT 24
Finished May 14 03:11:52 PM PDT 24
Peak memory 201772 kb
Host smart-3d4095d6-200f-482d-8605-afaac1d5119a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676974484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.676974484
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3288538535
Short name T247
Test name
Test status
Simulation time 606493501501 ps
CPU time 739.72 seconds
Started May 14 02:57:06 PM PDT 24
Finished May 14 03:09:27 PM PDT 24
Peak memory 201800 kb
Host smart-da8e9d3b-555a-4781-981b-66df2d21b531
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288538535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3288538535
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.489498568
Short name T214
Test name
Test status
Simulation time 98633082350 ps
CPU time 399.13 seconds
Started May 14 02:57:15 PM PDT 24
Finished May 14 03:03:55 PM PDT 24
Peak memory 202080 kb
Host smart-a8dab7c6-05ad-428b-b938-b5c4f159f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489498568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.489498568
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3360252586
Short name T530
Test name
Test status
Simulation time 28238836594 ps
CPU time 67.8 seconds
Started May 14 02:57:15 PM PDT 24
Finished May 14 02:58:24 PM PDT 24
Peak memory 201704 kb
Host smart-9f8cba3c-b253-4f5a-bd53-8c1e124e77ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360252586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3360252586
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3126318263
Short name T750
Test name
Test status
Simulation time 4433042983 ps
CPU time 11.49 seconds
Started May 14 02:57:16 PM PDT 24
Finished May 14 02:57:28 PM PDT 24
Peak memory 201588 kb
Host smart-2f856885-ffa0-484a-af7a-ed2ca3e2aad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126318263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3126318263
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.511105254
Short name T72
Test name
Test status
Simulation time 8080063837 ps
CPU time 12.78 seconds
Started May 14 02:57:16 PM PDT 24
Finished May 14 02:57:30 PM PDT 24
Peak memory 217392 kb
Host smart-4da24134-2512-40fe-b715-7d4dc10a66d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511105254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.511105254
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3944302274
Short name T751
Test name
Test status
Simulation time 5824872287 ps
CPU time 13.99 seconds
Started May 14 02:56:56 PM PDT 24
Finished May 14 02:57:11 PM PDT 24
Peak memory 201572 kb
Host smart-e89bc060-9487-41a1-acc7-02eee757402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944302274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3944302274
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3015906511
Short name T612
Test name
Test status
Simulation time 226834296869 ps
CPU time 273.77 seconds
Started May 14 02:57:15 PM PDT 24
Finished May 14 03:01:50 PM PDT 24
Peak memory 201860 kb
Host smart-e08ffdbd-7a9c-4cd2-9633-94a725238a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015906511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3015906511
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.4157297412
Short name T342
Test name
Test status
Simulation time 248754563312 ps
CPU time 120.51 seconds
Started May 14 02:57:15 PM PDT 24
Finished May 14 02:59:16 PM PDT 24
Peak memory 210428 kb
Host smart-d76d0820-08ef-4f8c-bbab-dac59763d9f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157297412 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.4157297412
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3771538601
Short name T731
Test name
Test status
Simulation time 427969760 ps
CPU time 1.52 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:00:54 PM PDT 24
Peak memory 201492 kb
Host smart-afcb260a-9056-489a-ba87-b87027080095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771538601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3771538601
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2848426536
Short name T267
Test name
Test status
Simulation time 588461280796 ps
CPU time 241.04 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:04:43 PM PDT 24
Peak memory 201828 kb
Host smart-01e5e830-7104-4bf4-a998-7fd1f0997ebd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848426536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2848426536
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.286179283
Short name T341
Test name
Test status
Simulation time 389379701857 ps
CPU time 486.11 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:08:47 PM PDT 24
Peak memory 201816 kb
Host smart-4d85f269-0e32-487a-879e-640d761560e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286179283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.286179283
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3485254615
Short name T777
Test name
Test status
Simulation time 161236477959 ps
CPU time 371.56 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:06:54 PM PDT 24
Peak memory 201788 kb
Host smart-b33d340e-b710-4748-8acc-04c75dfb3f0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485254615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3485254615
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3279651117
Short name T488
Test name
Test status
Simulation time 165304819558 ps
CPU time 177.59 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:03:39 PM PDT 24
Peak memory 201792 kb
Host smart-aea43d62-344b-4e2b-8be3-491a8cf5cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279651117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3279651117
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3387488082
Short name T474
Test name
Test status
Simulation time 485013650027 ps
CPU time 1205.36 seconds
Started May 14 03:00:41 PM PDT 24
Finished May 14 03:20:48 PM PDT 24
Peak memory 201736 kb
Host smart-3018a80b-32b1-4d6c-ba97-84087121e250
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387488082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3387488082
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1104000139
Short name T275
Test name
Test status
Simulation time 183642656934 ps
CPU time 432.82 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:07:55 PM PDT 24
Peak memory 201816 kb
Host smart-ae7f548e-5292-49d1-9b3e-8e332a58d9f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104000139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1104000139
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1720612755
Short name T477
Test name
Test status
Simulation time 425641531266 ps
CPU time 158.13 seconds
Started May 14 03:00:41 PM PDT 24
Finished May 14 03:03:21 PM PDT 24
Peak memory 201824 kb
Host smart-2c02c3e0-7c9b-49ba-97eb-030f15ba1833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720612755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1720612755
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3504727344
Short name T349
Test name
Test status
Simulation time 105545461136 ps
CPU time 445.12 seconds
Started May 14 03:00:41 PM PDT 24
Finished May 14 03:08:08 PM PDT 24
Peak memory 202136 kb
Host smart-c4bbcd07-a029-4de8-b50f-0a1dc13b9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504727344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3504727344
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.357264579
Short name T482
Test name
Test status
Simulation time 32110832064 ps
CPU time 40.37 seconds
Started May 14 03:00:41 PM PDT 24
Finished May 14 03:01:23 PM PDT 24
Peak memory 201680 kb
Host smart-ecb53b9c-a60d-43e7-97ad-568698a157c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357264579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.357264579
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.135825599
Short name T591
Test name
Test status
Simulation time 4850634711 ps
CPU time 5.94 seconds
Started May 14 03:00:41 PM PDT 24
Finished May 14 03:00:49 PM PDT 24
Peak memory 201680 kb
Host smart-3ca8bed4-8b6d-4636-acb3-41ef2b510121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135825599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.135825599
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2877697904
Short name T799
Test name
Test status
Simulation time 6004134802 ps
CPU time 4.08 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:00:45 PM PDT 24
Peak memory 201588 kb
Host smart-b174fc68-f5e7-4f5e-8d67-c78ae08be095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877697904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2877697904
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3470329268
Short name T333
Test name
Test status
Simulation time 188155695332 ps
CPU time 145.83 seconds
Started May 14 03:00:51 PM PDT 24
Finished May 14 03:03:21 PM PDT 24
Peak memory 201808 kb
Host smart-f78c8045-c687-4240-b66e-9e4c2fef9fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470329268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3470329268
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3793327940
Short name T18
Test name
Test status
Simulation time 127240494774 ps
CPU time 117.17 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:02:51 PM PDT 24
Peak memory 210464 kb
Host smart-107b4818-59b9-4f20-97c1-e1d0bb8cae69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793327940 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3793327940
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3667983517
Short name T558
Test name
Test status
Simulation time 423723169 ps
CPU time 0.72 seconds
Started May 14 03:00:48 PM PDT 24
Finished May 14 03:00:50 PM PDT 24
Peak memory 201480 kb
Host smart-2ff96fab-4bc6-47bd-84c6-931597503e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667983517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3667983517
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1148212826
Short name T268
Test name
Test status
Simulation time 349049073126 ps
CPU time 835.98 seconds
Started May 14 03:00:51 PM PDT 24
Finished May 14 03:14:51 PM PDT 24
Peak memory 201872 kb
Host smart-ca1561d4-a8bf-4470-a6e5-aab3ce00b0db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148212826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1148212826
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.242956418
Short name T648
Test name
Test status
Simulation time 330806732442 ps
CPU time 159.45 seconds
Started May 14 03:00:52 PM PDT 24
Finished May 14 03:03:35 PM PDT 24
Peak memory 201868 kb
Host smart-e0ec7e04-bbc2-4a1d-a2ab-ae07c369be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242956418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.242956418
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1680228246
Short name T134
Test name
Test status
Simulation time 323961496534 ps
CPU time 690.84 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:12:24 PM PDT 24
Peak memory 201920 kb
Host smart-d134bce1-b75c-43b7-a8a6-35f2e507e770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680228246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1680228246
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2455807821
Short name T470
Test name
Test status
Simulation time 497923097530 ps
CPU time 1152.82 seconds
Started May 14 03:00:48 PM PDT 24
Finished May 14 03:20:02 PM PDT 24
Peak memory 201816 kb
Host smart-758f02c1-2649-484c-a50d-37ccddc0eba8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455807821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2455807821
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1293155107
Short name T525
Test name
Test status
Simulation time 273066844521 ps
CPU time 646.06 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:11:39 PM PDT 24
Peak memory 201880 kb
Host smart-29e69851-8e41-4ae0-a3b7-f16708aa9b11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293155107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1293155107
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3264982821
Short name T434
Test name
Test status
Simulation time 597847328799 ps
CPU time 1383.9 seconds
Started May 14 03:00:51 PM PDT 24
Finished May 14 03:23:58 PM PDT 24
Peak memory 201868 kb
Host smart-2e9c5f05-400d-4376-8897-3606dca1eb12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264982821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3264982821
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1841212828
Short name T453
Test name
Test status
Simulation time 92415821919 ps
CPU time 330.23 seconds
Started May 14 03:00:51 PM PDT 24
Finished May 14 03:06:25 PM PDT 24
Peak memory 202032 kb
Host smart-49402ba6-dd12-4ac9-8557-a580e0f5e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841212828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1841212828
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2683901613
Short name T483
Test name
Test status
Simulation time 22386635411 ps
CPU time 11.62 seconds
Started May 14 03:00:48 PM PDT 24
Finished May 14 03:01:00 PM PDT 24
Peak memory 201552 kb
Host smart-5da87b87-bf30-4eb0-a871-ec275809a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683901613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2683901613
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1561033621
Short name T697
Test name
Test status
Simulation time 3710578803 ps
CPU time 2.88 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:00:54 PM PDT 24
Peak memory 201560 kb
Host smart-d75cd9ba-bb7d-4b09-b85a-92730df96e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561033621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1561033621
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4091949090
Short name T385
Test name
Test status
Simulation time 5670291423 ps
CPU time 13.68 seconds
Started May 14 03:00:47 PM PDT 24
Finished May 14 03:01:02 PM PDT 24
Peak memory 201624 kb
Host smart-51e73b07-e9d8-458b-bc4c-d3226b47d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091949090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4091949090
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1658724416
Short name T289
Test name
Test status
Simulation time 731990222204 ps
CPU time 1573.87 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:27:07 PM PDT 24
Peak memory 201852 kb
Host smart-42eb4735-2609-4cb3-ab60-9b9d2fb034da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658724416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1658724416
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3761031012
Short name T256
Test name
Test status
Simulation time 253876435699 ps
CPU time 177.76 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:03:51 PM PDT 24
Peak memory 210552 kb
Host smart-07d4c6e5-0781-4fb0-af1b-2c0be36d245c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761031012 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3761031012
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3914294058
Short name T636
Test name
Test status
Simulation time 323754444 ps
CPU time 1.4 seconds
Started May 14 03:00:58 PM PDT 24
Finished May 14 03:01:03 PM PDT 24
Peak memory 201536 kb
Host smart-0170d55c-9272-4b01-a9d1-85af9f434b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914294058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3914294058
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3246498074
Short name T481
Test name
Test status
Simulation time 326551030181 ps
CPU time 410.45 seconds
Started May 14 03:00:51 PM PDT 24
Finished May 14 03:07:45 PM PDT 24
Peak memory 201808 kb
Host smart-e6acd185-0a4b-4fd2-b16b-65cb28e65222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246498074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3246498074
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4092952243
Short name T317
Test name
Test status
Simulation time 486280613319 ps
CPU time 1019.62 seconds
Started May 14 03:00:52 PM PDT 24
Finished May 14 03:17:55 PM PDT 24
Peak memory 201716 kb
Host smart-c07e6954-df94-4f85-bbda-bb99b8d80d25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092952243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4092952243
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3179347554
Short name T88
Test name
Test status
Simulation time 487568561318 ps
CPU time 1093.48 seconds
Started May 14 03:00:51 PM PDT 24
Finished May 14 03:19:08 PM PDT 24
Peak memory 201808 kb
Host smart-f34ab7ab-e3bb-4191-bce1-df53c4a33b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179347554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3179347554
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2037982174
Short name T368
Test name
Test status
Simulation time 162291644160 ps
CPU time 60.34 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:01:54 PM PDT 24
Peak memory 201840 kb
Host smart-f0f1f395-8e60-450a-b8d2-a767beb1d187
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037982174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2037982174
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2586042251
Short name T85
Test name
Test status
Simulation time 215304676122 ps
CPU time 114.83 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:02:47 PM PDT 24
Peak memory 201804 kb
Host smart-3f8111c5-997b-440a-8dc8-3b25242261af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586042251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2586042251
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3441521395
Short name T429
Test name
Test status
Simulation time 623141997466 ps
CPU time 901.69 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:15:55 PM PDT 24
Peak memory 201912 kb
Host smart-970a6fe3-d4d4-4af2-bc45-5b33ec92e35d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441521395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3441521395
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4023943016
Short name T445
Test name
Test status
Simulation time 119964063231 ps
CPU time 646.67 seconds
Started May 14 03:00:59 PM PDT 24
Finished May 14 03:11:49 PM PDT 24
Peak memory 202048 kb
Host smart-aa01e54b-b7c7-4229-ae97-926271458e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023943016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4023943016
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3873568214
Short name T609
Test name
Test status
Simulation time 37893485718 ps
CPU time 84.63 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:02:17 PM PDT 24
Peak memory 201640 kb
Host smart-c0854315-5908-4f5d-bfcc-3282e52062ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873568214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3873568214
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1850424857
Short name T789
Test name
Test status
Simulation time 3954367685 ps
CPU time 7.94 seconds
Started May 14 03:00:49 PM PDT 24
Finished May 14 03:01:01 PM PDT 24
Peak memory 201572 kb
Host smart-e8693aee-d018-4191-b2ec-5a86330219db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850424857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1850424857
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2244976366
Short name T417
Test name
Test status
Simulation time 5677729337 ps
CPU time 4.66 seconds
Started May 14 03:00:50 PM PDT 24
Finished May 14 03:00:58 PM PDT 24
Peak memory 201624 kb
Host smart-e24b5c11-7023-449d-ba37-84d30cc45970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244976366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2244976366
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3874626072
Short name T29
Test name
Test status
Simulation time 191316810219 ps
CPU time 237.45 seconds
Started May 14 03:00:59 PM PDT 24
Finished May 14 03:05:00 PM PDT 24
Peak memory 212476 kb
Host smart-8f11cff1-2e6f-4d5b-90b6-2bb228dbb69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874626072 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3874626072
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2030132488
Short name T544
Test name
Test status
Simulation time 178081890300 ps
CPU time 423.93 seconds
Started May 14 03:01:09 PM PDT 24
Finished May 14 03:08:14 PM PDT 24
Peak memory 201852 kb
Host smart-9c607645-55f7-4275-9736-5c5f46030e23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030132488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2030132488
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2978880950
Short name T21
Test name
Test status
Simulation time 178492145659 ps
CPU time 436.54 seconds
Started May 14 03:01:24 PM PDT 24
Finished May 14 03:08:41 PM PDT 24
Peak memory 201716 kb
Host smart-c3abed1e-a8cf-48a1-b8d4-d85f3f7a7ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978880950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2978880950
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4271868670
Short name T670
Test name
Test status
Simulation time 487551793188 ps
CPU time 580.55 seconds
Started May 14 03:01:09 PM PDT 24
Finished May 14 03:10:50 PM PDT 24
Peak memory 201804 kb
Host smart-f0990676-8837-4036-b44c-068af7c169d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271868670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.4271868670
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2571808486
Short name T681
Test name
Test status
Simulation time 162602059480 ps
CPU time 106.18 seconds
Started May 14 03:00:59 PM PDT 24
Finished May 14 03:02:49 PM PDT 24
Peak memory 201876 kb
Host smart-a97bddac-427e-44e1-9faf-59ef4f8f7c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571808486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2571808486
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.699350326
Short name T443
Test name
Test status
Simulation time 330425968878 ps
CPU time 804 seconds
Started May 14 03:00:59 PM PDT 24
Finished May 14 03:14:27 PM PDT 24
Peak memory 201820 kb
Host smart-67da8768-ca8e-4e2a-a967-b18b137da7d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=699350326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.699350326
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1645245079
Short name T428
Test name
Test status
Simulation time 404932991635 ps
CPU time 1012.02 seconds
Started May 14 03:01:09 PM PDT 24
Finished May 14 03:18:02 PM PDT 24
Peak memory 201800 kb
Host smart-e1eee654-dc99-4f57-823b-e44feccde3d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645245079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1645245079
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.465953672
Short name T627
Test name
Test status
Simulation time 104299068686 ps
CPU time 561.12 seconds
Started May 14 03:01:24 PM PDT 24
Finished May 14 03:10:46 PM PDT 24
Peak memory 202120 kb
Host smart-588e8b63-aa5f-4639-9715-227f825bf011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465953672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.465953672
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2676199499
Short name T457
Test name
Test status
Simulation time 35870595484 ps
CPU time 78.64 seconds
Started May 14 03:01:22 PM PDT 24
Finished May 14 03:02:42 PM PDT 24
Peak memory 201624 kb
Host smart-01a151e2-fc37-447e-a75f-450b045c2505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676199499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2676199499
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4224368626
Short name T503
Test name
Test status
Simulation time 5047854082 ps
CPU time 7.36 seconds
Started May 14 03:01:24 PM PDT 24
Finished May 14 03:01:32 PM PDT 24
Peak memory 201740 kb
Host smart-2dfe0220-acff-462d-88ea-a0f0e4c8afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224368626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4224368626
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.872334451
Short name T194
Test name
Test status
Simulation time 6199257942 ps
CPU time 7.74 seconds
Started May 14 03:00:59 PM PDT 24
Finished May 14 03:01:10 PM PDT 24
Peak memory 201632 kb
Host smart-a1c1c91f-8230-4194-8426-0654790e52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872334451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.872334451
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.334865288
Short name T283
Test name
Test status
Simulation time 353447844937 ps
CPU time 779.54 seconds
Started May 14 03:01:25 PM PDT 24
Finished May 14 03:14:25 PM PDT 24
Peak memory 201900 kb
Host smart-e0880dc3-b713-4333-84d4-0680f01810dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334865288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
334865288
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3095884845
Short name T294
Test name
Test status
Simulation time 102906602479 ps
CPU time 215.86 seconds
Started May 14 03:01:22 PM PDT 24
Finished May 14 03:04:59 PM PDT 24
Peak memory 210176 kb
Host smart-3a3c1183-e1f7-490d-96ed-06324482dd05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095884845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3095884845
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2649799376
Short name T568
Test name
Test status
Simulation time 524996405 ps
CPU time 1.87 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:01:36 PM PDT 24
Peak memory 201424 kb
Host smart-13b5eafe-a646-462a-8f80-27611aba7db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649799376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2649799376
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1679589284
Short name T540
Test name
Test status
Simulation time 162120216974 ps
CPU time 311.21 seconds
Started May 14 03:01:32 PM PDT 24
Finished May 14 03:06:44 PM PDT 24
Peak memory 201796 kb
Host smart-09ec1293-6b76-4e80-8c0e-61f97874e90c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679589284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1679589284
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3344313571
Short name T522
Test name
Test status
Simulation time 530194081433 ps
CPU time 662.86 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:12:38 PM PDT 24
Peak memory 201948 kb
Host smart-94e1dd2d-6224-4e22-87cd-2183bc7a74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344313571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3344313571
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3644342394
Short name T302
Test name
Test status
Simulation time 160306632707 ps
CPU time 94.12 seconds
Started May 14 03:01:21 PM PDT 24
Finished May 14 03:02:56 PM PDT 24
Peak memory 201776 kb
Host smart-68126ea9-4f34-400c-8458-b251c8b900f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644342394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3644342394
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1349696488
Short name T424
Test name
Test status
Simulation time 492854183506 ps
CPU time 293.2 seconds
Started May 14 03:01:22 PM PDT 24
Finished May 14 03:06:16 PM PDT 24
Peak memory 201752 kb
Host smart-711784ba-8ead-431d-8a1d-3cf1eaec389d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349696488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1349696488
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2185349176
Short name T630
Test name
Test status
Simulation time 320961787842 ps
CPU time 374.08 seconds
Started May 14 03:01:23 PM PDT 24
Finished May 14 03:07:37 PM PDT 24
Peak memory 201780 kb
Host smart-d4ea0e41-abca-4ca9-b3a5-fd94f291aa9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185349176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2185349176
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3800320843
Short name T619
Test name
Test status
Simulation time 379266977364 ps
CPU time 864.6 seconds
Started May 14 03:01:24 PM PDT 24
Finished May 14 03:15:49 PM PDT 24
Peak memory 201880 kb
Host smart-cff68873-12cf-4a16-8e89-7f60da9d6ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800320843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3800320843
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3849592877
Short name T693
Test name
Test status
Simulation time 596709617561 ps
CPU time 228.04 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:05:23 PM PDT 24
Peak memory 201860 kb
Host smart-b304bc0f-ff23-46d3-a2a4-8e16a3ac5a18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849592877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3849592877
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3473368352
Short name T600
Test name
Test status
Simulation time 105264052603 ps
CPU time 547.46 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:10:42 PM PDT 24
Peak memory 202264 kb
Host smart-d855cd56-30cd-483c-bef1-bf5a31a088a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473368352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3473368352
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2349454389
Short name T452
Test name
Test status
Simulation time 34209694875 ps
CPU time 12.94 seconds
Started May 14 03:01:35 PM PDT 24
Finished May 14 03:01:50 PM PDT 24
Peak memory 201584 kb
Host smart-57d4daf8-2057-4ad6-91da-4e0e9e62195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349454389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2349454389
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2865917891
Short name T703
Test name
Test status
Simulation time 4327395674 ps
CPU time 5.9 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:01:40 PM PDT 24
Peak memory 201604 kb
Host smart-f197b9b1-f06f-415f-b7e1-c7da5df2102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865917891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2865917891
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1363390164
Short name T744
Test name
Test status
Simulation time 6083031300 ps
CPU time 7.24 seconds
Started May 14 03:01:22 PM PDT 24
Finished May 14 03:01:30 PM PDT 24
Peak memory 201712 kb
Host smart-2dfdae12-3c9f-4940-8f08-15b26f94b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363390164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1363390164
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3029186582
Short name T143
Test name
Test status
Simulation time 358920014128 ps
CPU time 697.75 seconds
Started May 14 03:01:34 PM PDT 24
Finished May 14 03:13:13 PM PDT 24
Peak memory 201992 kb
Host smart-a382c946-d8ec-407f-99cd-4ee02751f15f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029186582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3029186582
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1328174564
Short name T588
Test name
Test status
Simulation time 9689860672 ps
CPU time 28.39 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:02:02 PM PDT 24
Peak memory 210408 kb
Host smart-cc8e22b9-9f4d-4910-a63f-7573f2b5a85b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328174564 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1328174564
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.176426386
Short name T362
Test name
Test status
Simulation time 521882571 ps
CPU time 0.92 seconds
Started May 14 03:01:43 PM PDT 24
Finished May 14 03:01:45 PM PDT 24
Peak memory 201544 kb
Host smart-9d0087fe-5ac7-493f-b64b-9ccdd4625369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176426386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.176426386
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.424645207
Short name T661
Test name
Test status
Simulation time 324155959652 ps
CPU time 741.16 seconds
Started May 14 03:01:42 PM PDT 24
Finished May 14 03:14:04 PM PDT 24
Peak memory 201840 kb
Host smart-e1a0d9f7-4ee2-4ebc-812c-d2964a59e07a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424645207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.424645207
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.794341153
Short name T686
Test name
Test status
Simulation time 540092579483 ps
CPU time 1262.34 seconds
Started May 14 03:01:43 PM PDT 24
Finished May 14 03:22:46 PM PDT 24
Peak memory 201828 kb
Host smart-d6e9ea29-d20d-4d87-9e00-fa740fb6d3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794341153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.794341153
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3045109118
Short name T495
Test name
Test status
Simulation time 331731761336 ps
CPU time 197.37 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:04:52 PM PDT 24
Peak memory 201904 kb
Host smart-ff7e1901-b28b-49b4-9a0e-1212bb9588fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045109118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3045109118
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.961282779
Short name T723
Test name
Test status
Simulation time 163781093347 ps
CPU time 101.75 seconds
Started May 14 03:01:33 PM PDT 24
Finished May 14 03:03:16 PM PDT 24
Peak memory 201776 kb
Host smart-7fe1fb9d-aaf0-4955-9840-31e3fbb6d4ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=961282779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.961282779
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1728615528
Short name T204
Test name
Test status
Simulation time 495691938210 ps
CPU time 79.44 seconds
Started May 14 03:01:35 PM PDT 24
Finished May 14 03:02:56 PM PDT 24
Peak memory 201884 kb
Host smart-c4915c15-bd0d-4a5c-a77c-718e2d8c0392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728615528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1728615528
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3705290487
Short name T402
Test name
Test status
Simulation time 162785284492 ps
CPU time 407.16 seconds
Started May 14 03:01:36 PM PDT 24
Finished May 14 03:08:24 PM PDT 24
Peak memory 201740 kb
Host smart-81bafe07-c210-47a6-bd3d-532e17400e47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705290487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3705290487
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3325719876
Short name T178
Test name
Test status
Simulation time 204809204483 ps
CPU time 75.5 seconds
Started May 14 03:01:34 PM PDT 24
Finished May 14 03:02:51 PM PDT 24
Peak memory 201836 kb
Host smart-c8dbad06-e73a-41d5-9baa-f1b38d0e0047
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325719876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3325719876
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2590058699
Short name T397
Test name
Test status
Simulation time 25780511084 ps
CPU time 32.4 seconds
Started May 14 03:01:42 PM PDT 24
Finished May 14 03:02:16 PM PDT 24
Peak memory 201556 kb
Host smart-5f2a32bf-d9ec-4c79-8196-3234543cf21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590058699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2590058699
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.55168535
Short name T610
Test name
Test status
Simulation time 3639656014 ps
CPU time 2.85 seconds
Started May 14 03:01:45 PM PDT 24
Finished May 14 03:01:48 PM PDT 24
Peak memory 201616 kb
Host smart-07c872b3-f806-40be-ba9e-47bfd7f02153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55168535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.55168535
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2170832831
Short name T412
Test name
Test status
Simulation time 6071672526 ps
CPU time 4.63 seconds
Started May 14 03:01:34 PM PDT 24
Finished May 14 03:01:40 PM PDT 24
Peak memory 201628 kb
Host smart-1eaacfac-9a75-41e7-9d97-311ced95252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170832831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2170832831
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1149492519
Short name T156
Test name
Test status
Simulation time 185182677579 ps
CPU time 122.08 seconds
Started May 14 03:01:43 PM PDT 24
Finished May 14 03:03:47 PM PDT 24
Peak memory 201796 kb
Host smart-bfcbd98b-c980-4e7d-8e71-171edf0cad4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149492519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1149492519
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2895447277
Short name T676
Test name
Test status
Simulation time 577134855 ps
CPU time 0.75 seconds
Started May 14 03:01:59 PM PDT 24
Finished May 14 03:02:01 PM PDT 24
Peak memory 201752 kb
Host smart-bdfcd852-0668-46d7-baa8-3970b2aa0d85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895447277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2895447277
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1821832370
Short name T308
Test name
Test status
Simulation time 166023206512 ps
CPU time 177.95 seconds
Started May 14 03:01:51 PM PDT 24
Finished May 14 03:04:50 PM PDT 24
Peak memory 201788 kb
Host smart-a5276abc-d7ae-4385-a4ea-58e4b39859b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821832370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1821832370
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2697359783
Short name T128
Test name
Test status
Simulation time 164004660491 ps
CPU time 377.64 seconds
Started May 14 03:01:42 PM PDT 24
Finished May 14 03:08:01 PM PDT 24
Peak memory 201828 kb
Host smart-5e0b9e32-82bf-475a-9871-e297f740c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697359783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2697359783
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4049510455
Short name T666
Test name
Test status
Simulation time 490697660219 ps
CPU time 622.44 seconds
Started May 14 03:01:43 PM PDT 24
Finished May 14 03:12:07 PM PDT 24
Peak memory 201772 kb
Host smart-191b0dc0-e60d-4106-89d2-75639e437122
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049510455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4049510455
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3010589584
Short name T122
Test name
Test status
Simulation time 492900685365 ps
CPU time 1127.32 seconds
Started May 14 03:01:42 PM PDT 24
Finished May 14 03:20:31 PM PDT 24
Peak memory 201824 kb
Host smart-481e83f6-4b4d-4fc6-9a24-fbe0335ac102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010589584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3010589584
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2144083751
Short name T720
Test name
Test status
Simulation time 496632728627 ps
CPU time 584.45 seconds
Started May 14 03:01:46 PM PDT 24
Finished May 14 03:11:32 PM PDT 24
Peak memory 201844 kb
Host smart-2481ce58-2368-4b3e-988a-9e0c5fbf37a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144083751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2144083751
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1940833200
Short name T704
Test name
Test status
Simulation time 597647318930 ps
CPU time 703.01 seconds
Started May 14 03:01:52 PM PDT 24
Finished May 14 03:13:36 PM PDT 24
Peak memory 201996 kb
Host smart-25c9cca7-7e55-4382-a3df-bb618c6401a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940833200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1940833200
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3981307128
Short name T680
Test name
Test status
Simulation time 589267009203 ps
CPU time 1405.14 seconds
Started May 14 03:01:55 PM PDT 24
Finished May 14 03:25:21 PM PDT 24
Peak memory 201916 kb
Host smart-b2b1f124-74bd-4562-8835-eac8f71184ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981307128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3981307128
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3771113322
Short name T646
Test name
Test status
Simulation time 89189307351 ps
CPU time 384.43 seconds
Started May 14 03:01:50 PM PDT 24
Finished May 14 03:08:16 PM PDT 24
Peak memory 202176 kb
Host smart-ac7c79ae-ef67-4ce4-8927-f821463814c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771113322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3771113322
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3238448390
Short name T435
Test name
Test status
Simulation time 39048567760 ps
CPU time 24.4 seconds
Started May 14 03:01:56 PM PDT 24
Finished May 14 03:02:21 PM PDT 24
Peak memory 201744 kb
Host smart-4e7b72bf-1fb9-4762-b72d-52b98c567d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238448390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3238448390
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2313674539
Short name T86
Test name
Test status
Simulation time 4524002432 ps
CPU time 12.01 seconds
Started May 14 03:01:51 PM PDT 24
Finished May 14 03:02:04 PM PDT 24
Peak memory 201672 kb
Host smart-c0dc1345-09c6-4bed-b179-e1c5ae021857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313674539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2313674539
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.104541140
Short name T354
Test name
Test status
Simulation time 5989171252 ps
CPU time 8.31 seconds
Started May 14 03:01:42 PM PDT 24
Finished May 14 03:01:51 PM PDT 24
Peak memory 201624 kb
Host smart-88b934b9-f258-46e9-927d-7bd64b5088a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104541140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.104541140
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2515143780
Short name T5
Test name
Test status
Simulation time 465506989528 ps
CPU time 403.85 seconds
Started May 14 03:01:50 PM PDT 24
Finished May 14 03:08:35 PM PDT 24
Peak memory 212760 kb
Host smart-8fd94177-37ce-4dfd-8a19-919fbbe29c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515143780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2515143780
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1869939620
Short name T57
Test name
Test status
Simulation time 289896666 ps
CPU time 1.31 seconds
Started May 14 03:02:26 PM PDT 24
Finished May 14 03:02:29 PM PDT 24
Peak memory 201504 kb
Host smart-7f3f5b1c-7439-498c-a869-b4d75d453104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869939620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1869939620
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1968921203
Short name T273
Test name
Test status
Simulation time 358088912123 ps
CPU time 238.43 seconds
Started May 14 03:02:09 PM PDT 24
Finished May 14 03:06:09 PM PDT 24
Peak memory 201836 kb
Host smart-67da62ab-b64a-4435-b8ff-ae8217dbbdee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968921203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1968921203
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.701567981
Short name T123
Test name
Test status
Simulation time 167196186987 ps
CPU time 191.68 seconds
Started May 14 03:02:08 PM PDT 24
Finished May 14 03:05:21 PM PDT 24
Peak memory 201832 kb
Host smart-daebeb5c-d013-4f09-8509-35347d703790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701567981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.701567981
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1628717396
Short name T639
Test name
Test status
Simulation time 162971922707 ps
CPU time 388.31 seconds
Started May 14 03:02:01 PM PDT 24
Finished May 14 03:08:30 PM PDT 24
Peak memory 201764 kb
Host smart-53752000-f249-45d8-a526-f0ffb0e23b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628717396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1628717396
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3361956694
Short name T678
Test name
Test status
Simulation time 335134525990 ps
CPU time 108.92 seconds
Started May 14 03:02:09 PM PDT 24
Finished May 14 03:03:58 PM PDT 24
Peak memory 201876 kb
Host smart-8ac3bb5a-b180-4aff-bd91-81213df7f7f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361956694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3361956694
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2430222453
Short name T493
Test name
Test status
Simulation time 162813125888 ps
CPU time 21.84 seconds
Started May 14 03:01:59 PM PDT 24
Finished May 14 03:02:22 PM PDT 24
Peak memory 201760 kb
Host smart-1dbdd13e-44cc-40f3-8dde-c72b69976219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430222453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2430222453
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1530438369
Short name T762
Test name
Test status
Simulation time 326364804074 ps
CPU time 63.73 seconds
Started May 14 03:01:59 PM PDT 24
Finished May 14 03:03:04 PM PDT 24
Peak memory 201840 kb
Host smart-d303adc0-287b-44e4-a90e-74259ecfac86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530438369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1530438369
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4209217880
Short name T243
Test name
Test status
Simulation time 365230061559 ps
CPU time 861.61 seconds
Started May 14 03:02:09 PM PDT 24
Finished May 14 03:16:32 PM PDT 24
Peak memory 201872 kb
Host smart-f6d092e6-b90d-47a3-b21b-ae15fd339e9f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209217880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4209217880
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2484180561
Short name T563
Test name
Test status
Simulation time 403182518805 ps
CPU time 192.42 seconds
Started May 14 03:02:09 PM PDT 24
Finished May 14 03:05:23 PM PDT 24
Peak memory 201824 kb
Host smart-3e1f6e32-2ff7-46f9-a1d1-59ca8714b905
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484180561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2484180561
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.186766831
Short name T207
Test name
Test status
Simulation time 119917409259 ps
CPU time 532.12 seconds
Started May 14 03:02:17 PM PDT 24
Finished May 14 03:11:10 PM PDT 24
Peak memory 202100 kb
Host smart-fb6c191c-59d1-4f58-9367-4a3b1b164b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186766831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.186766831
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1758600735
Short name T374
Test name
Test status
Simulation time 26780776663 ps
CPU time 7.44 seconds
Started May 14 03:02:17 PM PDT 24
Finished May 14 03:02:26 PM PDT 24
Peak memory 201596 kb
Host smart-9f9a30a4-a973-4d54-a119-5277dbe48184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758600735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1758600735
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3707262477
Short name T444
Test name
Test status
Simulation time 3572430051 ps
CPU time 1.27 seconds
Started May 14 03:02:21 PM PDT 24
Finished May 14 03:02:23 PM PDT 24
Peak memory 201668 kb
Host smart-0ea61668-3582-4bb6-b93d-4ed35d0d493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707262477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3707262477
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1452632977
Short name T458
Test name
Test status
Simulation time 5831607165 ps
CPU time 14.15 seconds
Started May 14 03:02:00 PM PDT 24
Finished May 14 03:02:15 PM PDT 24
Peak memory 201588 kb
Host smart-6e8ada17-39d0-48d8-8e4f-86be547aade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452632977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1452632977
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3764419764
Short name T41
Test name
Test status
Simulation time 329503803748 ps
CPU time 338.01 seconds
Started May 14 03:02:25 PM PDT 24
Finished May 14 03:08:04 PM PDT 24
Peak memory 201740 kb
Host smart-192f15e4-8db1-4434-af15-34265cb962b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764419764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3764419764
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2292881621
Short name T80
Test name
Test status
Simulation time 68754211735 ps
CPU time 76.77 seconds
Started May 14 03:02:16 PM PDT 24
Finished May 14 03:03:34 PM PDT 24
Peak memory 217728 kb
Host smart-276063bb-4336-4f2a-8f98-9c6a12b78552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292881621 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2292881621
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2112397950
Short name T484
Test name
Test status
Simulation time 317346314 ps
CPU time 0.74 seconds
Started May 14 03:02:42 PM PDT 24
Finished May 14 03:02:43 PM PDT 24
Peak memory 201508 kb
Host smart-87c34af5-7bfc-487f-8b21-5fced0e007e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112397950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2112397950
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3273227412
Short name T94
Test name
Test status
Simulation time 165841423080 ps
CPU time 203.43 seconds
Started May 14 03:02:26 PM PDT 24
Finished May 14 03:05:50 PM PDT 24
Peak memory 201800 kb
Host smart-caba3bea-5a42-4a5e-9957-6f2a5e7e9b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273227412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3273227412
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4078702320
Short name T462
Test name
Test status
Simulation time 328235573198 ps
CPU time 225.47 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:06:21 PM PDT 24
Peak memory 201768 kb
Host smart-029c3083-7100-4e07-b288-95cc81b03e12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078702320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4078702320
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.494232084
Short name T300
Test name
Test status
Simulation time 329620578791 ps
CPU time 198.15 seconds
Started May 14 03:02:25 PM PDT 24
Finished May 14 03:05:44 PM PDT 24
Peak memory 201776 kb
Host smart-4247e3e6-c4dd-47ab-9c1c-17d1b018c31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494232084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.494232084
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3553327795
Short name T514
Test name
Test status
Simulation time 166535436660 ps
CPU time 106.07 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:04:22 PM PDT 24
Peak memory 201860 kb
Host smart-74e596de-399b-420b-a1ff-e0cfdb77b8dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553327795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3553327795
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1568331580
Short name T277
Test name
Test status
Simulation time 361963836179 ps
CPU time 841.26 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:16:37 PM PDT 24
Peak memory 201804 kb
Host smart-0445286e-f1ac-4491-bff0-c2258784f0f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568331580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1568331580
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2307581281
Short name T622
Test name
Test status
Simulation time 194766957974 ps
CPU time 126.99 seconds
Started May 14 03:02:36 PM PDT 24
Finished May 14 03:04:44 PM PDT 24
Peak memory 201984 kb
Host smart-0968ce28-2d8d-41df-a5c3-8890ecd3bed7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307581281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2307581281
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1617822242
Short name T615
Test name
Test status
Simulation time 100382343211 ps
CPU time 447.27 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:10:03 PM PDT 24
Peak memory 202452 kb
Host smart-fe8c58c6-b5cf-455a-b0af-06aaad616264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617822242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1617822242
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1949522922
Short name T581
Test name
Test status
Simulation time 23971015079 ps
CPU time 52.7 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:03:28 PM PDT 24
Peak memory 201608 kb
Host smart-0a3f5a15-ab1b-439b-93ee-bd35ec6d747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949522922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1949522922
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3127887023
Short name T608
Test name
Test status
Simulation time 3786657878 ps
CPU time 2.27 seconds
Started May 14 03:02:36 PM PDT 24
Finished May 14 03:02:39 PM PDT 24
Peak memory 201680 kb
Host smart-f90cbedf-f7c2-40bf-8f30-a657ea975b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127887023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3127887023
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.130645357
Short name T705
Test name
Test status
Simulation time 5779578198 ps
CPU time 14.16 seconds
Started May 14 03:02:27 PM PDT 24
Finished May 14 03:02:42 PM PDT 24
Peak memory 201700 kb
Host smart-e072a57d-361b-4a31-8c62-3f133dee0e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130645357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.130645357
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2088240882
Short name T660
Test name
Test status
Simulation time 41502282556 ps
CPU time 89.4 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:04:04 PM PDT 24
Peak memory 201756 kb
Host smart-d5d9d807-b02b-41cd-a69d-d5aabfa4621a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088240882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2088240882
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.211191007
Short name T12
Test name
Test status
Simulation time 134488280488 ps
CPU time 175.45 seconds
Started May 14 03:02:34 PM PDT 24
Finished May 14 03:05:31 PM PDT 24
Peak memory 210476 kb
Host smart-52cdda1b-fdfa-4ed9-ba07-b9278c8d0491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211191007 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.211191007
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2839848925
Short name T768
Test name
Test status
Simulation time 360136915 ps
CPU time 0.89 seconds
Started May 14 03:03:01 PM PDT 24
Finished May 14 03:03:03 PM PDT 24
Peak memory 201524 kb
Host smart-9060ac0d-7950-422b-af4f-6577e535198b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839848925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2839848925
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.856079360
Short name T220
Test name
Test status
Simulation time 172609371898 ps
CPU time 205.15 seconds
Started May 14 03:02:51 PM PDT 24
Finished May 14 03:06:17 PM PDT 24
Peak memory 201732 kb
Host smart-b7dbd694-38ab-42e9-adfb-16e039881ad2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856079360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.856079360
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1773991452
Short name T534
Test name
Test status
Simulation time 169028678667 ps
CPU time 79.61 seconds
Started May 14 03:02:43 PM PDT 24
Finished May 14 03:04:03 PM PDT 24
Peak memory 201860 kb
Host smart-4887d08d-4d89-4a92-8f8a-ab93ee2c2c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773991452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1773991452
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3557375907
Short name T422
Test name
Test status
Simulation time 508051444403 ps
CPU time 1139.34 seconds
Started May 14 03:02:52 PM PDT 24
Finished May 14 03:21:52 PM PDT 24
Peak memory 201828 kb
Host smart-699c0ce5-28cd-4a68-a33b-51d590c1104f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557375907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3557375907
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1728142751
Short name T325
Test name
Test status
Simulation time 486153171754 ps
CPU time 331 seconds
Started May 14 03:02:42 PM PDT 24
Finished May 14 03:08:14 PM PDT 24
Peak memory 201772 kb
Host smart-a059eb1b-dc13-4e81-bf8a-f2b0f4475316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728142751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1728142751
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1453527559
Short name T439
Test name
Test status
Simulation time 327085577039 ps
CPU time 719.97 seconds
Started May 14 03:02:42 PM PDT 24
Finished May 14 03:14:43 PM PDT 24
Peak memory 201764 kb
Host smart-3d3cc65a-95a7-460b-a9da-93b586e7f283
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453527559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1453527559
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1828029542
Short name T339
Test name
Test status
Simulation time 359192134455 ps
CPU time 219.39 seconds
Started May 14 03:02:50 PM PDT 24
Finished May 14 03:06:30 PM PDT 24
Peak memory 201836 kb
Host smart-2ca13749-22c5-4af6-b62d-47d7c186f5f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828029542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1828029542
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2875885358
Short name T192
Test name
Test status
Simulation time 605823488161 ps
CPU time 403.04 seconds
Started May 14 03:02:52 PM PDT 24
Finished May 14 03:09:36 PM PDT 24
Peak memory 201796 kb
Host smart-5ee63740-cd46-4f79-98b6-0e06137ad70e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875885358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2875885358
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1663071850
Short name T404
Test name
Test status
Simulation time 139730776413 ps
CPU time 751.5 seconds
Started May 14 03:02:52 PM PDT 24
Finished May 14 03:15:24 PM PDT 24
Peak memory 202376 kb
Host smart-47539113-541b-40fc-a422-ed5ce78811e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663071850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1663071850
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2047986002
Short name T486
Test name
Test status
Simulation time 26580551482 ps
CPU time 16.69 seconds
Started May 14 03:02:52 PM PDT 24
Finished May 14 03:03:10 PM PDT 24
Peak memory 201628 kb
Host smart-9c03d8cd-17aa-4ebe-9e55-3e66e6f933b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047986002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2047986002
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3961418610
Short name T702
Test name
Test status
Simulation time 4723110373 ps
CPU time 6.56 seconds
Started May 14 03:02:51 PM PDT 24
Finished May 14 03:02:58 PM PDT 24
Peak memory 201648 kb
Host smart-d9728823-b8d4-42cc-80b4-e8c95d4882c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961418610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3961418610
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1020243915
Short name T190
Test name
Test status
Simulation time 5837236435 ps
CPU time 15.43 seconds
Started May 14 03:02:42 PM PDT 24
Finished May 14 03:02:58 PM PDT 24
Peak memory 201684 kb
Host smart-35a6a821-ea43-464d-bb6f-4bf90eba6489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020243915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1020243915
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.203712212
Short name T564
Test name
Test status
Simulation time 81266827003 ps
CPU time 326.76 seconds
Started May 14 03:03:01 PM PDT 24
Finished May 14 03:08:29 PM PDT 24
Peak memory 202116 kb
Host smart-04745962-922f-4a27-8703-944ed422094a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203712212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
203712212
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3485456595
Short name T146
Test name
Test status
Simulation time 140281697459 ps
CPU time 169.87 seconds
Started May 14 03:03:02 PM PDT 24
Finished May 14 03:05:53 PM PDT 24
Peak memory 210476 kb
Host smart-1a9203eb-f94a-4854-936b-85e530665512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485456595 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3485456595
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1106360196
Short name T539
Test name
Test status
Simulation time 402645357 ps
CPU time 1.58 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 02:57:36 PM PDT 24
Peak memory 201432 kb
Host smart-cf3f0850-7a20-493c-8f5e-53a2c3c60d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106360196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1106360196
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1969523779
Short name T263
Test name
Test status
Simulation time 374286727425 ps
CPU time 892.43 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 03:12:27 PM PDT 24
Peak memory 201868 kb
Host smart-78f2544e-d1a9-46b5-a065-5f7ba97a3c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969523779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1969523779
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.503794797
Short name T459
Test name
Test status
Simulation time 165686940797 ps
CPU time 373.4 seconds
Started May 14 02:57:24 PM PDT 24
Finished May 14 03:03:38 PM PDT 24
Peak memory 201856 kb
Host smart-7f6b9f9c-2e4b-4bcb-89bb-dc9b6b4723a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503794797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.503794797
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2414413286
Short name T561
Test name
Test status
Simulation time 321881968710 ps
CPU time 772.96 seconds
Started May 14 02:57:24 PM PDT 24
Finished May 14 03:10:18 PM PDT 24
Peak memory 201716 kb
Host smart-639727dc-ed8b-4835-b955-c1ba37ce6d45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414413286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2414413286
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3755288918
Short name T147
Test name
Test status
Simulation time 165093131964 ps
CPU time 200.08 seconds
Started May 14 02:57:16 PM PDT 24
Finished May 14 03:00:37 PM PDT 24
Peak memory 201860 kb
Host smart-d15c84f0-7c36-44c0-95b1-0511aedd9ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755288918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3755288918
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2864717792
Short name T523
Test name
Test status
Simulation time 496926837869 ps
CPU time 122.71 seconds
Started May 14 02:57:25 PM PDT 24
Finished May 14 02:59:29 PM PDT 24
Peak memory 201952 kb
Host smart-147b2a56-6bf4-4c78-a2b9-29120707fdca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864717792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2864717792
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2411726469
Short name T774
Test name
Test status
Simulation time 394962293982 ps
CPU time 120.93 seconds
Started May 14 02:57:23 PM PDT 24
Finished May 14 02:59:25 PM PDT 24
Peak memory 201796 kb
Host smart-288fc5b1-bdb6-48cf-9c9f-09fad3f39551
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411726469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2411726469
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1313317018
Short name T752
Test name
Test status
Simulation time 32667030789 ps
CPU time 17.97 seconds
Started May 14 02:57:34 PM PDT 24
Finished May 14 02:57:53 PM PDT 24
Peak memory 201616 kb
Host smart-0ab544bb-9f6c-4e8d-97fb-fddc48ada53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313317018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1313317018
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2918464880
Short name T401
Test name
Test status
Simulation time 2926241772 ps
CPU time 7.73 seconds
Started May 14 02:57:34 PM PDT 24
Finished May 14 02:57:43 PM PDT 24
Peak memory 201576 kb
Host smart-0d982688-05e2-4c2a-9324-2d0067492e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918464880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2918464880
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2411621493
Short name T50
Test name
Test status
Simulation time 7227024375 ps
CPU time 8.46 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 02:57:43 PM PDT 24
Peak memory 218508 kb
Host smart-5fb028ef-6541-4c20-b907-d15e24a417d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411621493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2411621493
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.874164323
Short name T366
Test name
Test status
Simulation time 5906278888 ps
CPU time 2.03 seconds
Started May 14 02:57:14 PM PDT 24
Finished May 14 02:57:17 PM PDT 24
Peak memory 201636 kb
Host smart-16f5355c-5ac3-4163-83c5-6f85bc14a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874164323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.874164323
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1006796823
Short name T603
Test name
Test status
Simulation time 253787430285 ps
CPU time 358.66 seconds
Started May 14 02:57:34 PM PDT 24
Finished May 14 03:03:34 PM PDT 24
Peak memory 210520 kb
Host smart-db8fee9f-4a4e-453c-bb81-b311d089040d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006796823 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1006796823
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1093799830
Short name T426
Test name
Test status
Simulation time 500856619 ps
CPU time 0.93 seconds
Started May 14 03:03:10 PM PDT 24
Finished May 14 03:03:11 PM PDT 24
Peak memory 201488 kb
Host smart-6996dd3b-0806-4797-9ce7-e7d7bd675c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093799830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1093799830
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2097411156
Short name T556
Test name
Test status
Simulation time 161474807751 ps
CPU time 353.21 seconds
Started May 14 03:03:00 PM PDT 24
Finished May 14 03:08:54 PM PDT 24
Peak memory 201792 kb
Host smart-9bd1acb0-c9a4-491e-8036-c2f60d8ab08d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097411156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2097411156
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.51317786
Short name T162
Test name
Test status
Simulation time 168424019532 ps
CPU time 31.44 seconds
Started May 14 03:03:00 PM PDT 24
Finished May 14 03:03:32 PM PDT 24
Peak memory 201848 kb
Host smart-54b43ab9-66e1-4787-8d4a-6872ed5af2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51317786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.51317786
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.968263077
Short name T594
Test name
Test status
Simulation time 159847503968 ps
CPU time 194.83 seconds
Started May 14 03:03:01 PM PDT 24
Finished May 14 03:06:17 PM PDT 24
Peak memory 201860 kb
Host smart-75edb3af-fac5-44e3-8cd1-61699d64bb5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=968263077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.968263077
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3555227958
Short name T538
Test name
Test status
Simulation time 600204702853 ps
CPU time 337.46 seconds
Started May 14 03:03:01 PM PDT 24
Finished May 14 03:08:39 PM PDT 24
Peak memory 201808 kb
Host smart-05444e62-8813-476f-acee-bbfdf8c907a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555227958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3555227958
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2215868968
Short name T549
Test name
Test status
Simulation time 142673295327 ps
CPU time 762.06 seconds
Started May 14 03:03:10 PM PDT 24
Finished May 14 03:15:53 PM PDT 24
Peak memory 202284 kb
Host smart-b1880bd2-56b9-4b21-87a8-21deec057235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215868968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2215868968
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.94386333
Short name T359
Test name
Test status
Simulation time 37911202764 ps
CPU time 72.63 seconds
Started May 14 03:03:10 PM PDT 24
Finished May 14 03:04:24 PM PDT 24
Peak memory 201604 kb
Host smart-0e7bc880-2937-4407-a88f-5ca0da7888b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94386333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.94386333
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.500136819
Short name T369
Test name
Test status
Simulation time 4174203849 ps
CPU time 3.34 seconds
Started May 14 03:03:11 PM PDT 24
Finished May 14 03:03:15 PM PDT 24
Peak memory 201640 kb
Host smart-944cb2fb-feef-4c2f-a680-179c846a908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500136819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.500136819
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1038973542
Short name T560
Test name
Test status
Simulation time 5933420410 ps
CPU time 14.48 seconds
Started May 14 03:03:01 PM PDT 24
Finished May 14 03:03:17 PM PDT 24
Peak memory 201640 kb
Host smart-1937cb16-5df2-41f4-8be8-889294c230ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038973542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1038973542
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.99937943
Short name T139
Test name
Test status
Simulation time 334747352947 ps
CPU time 773.2 seconds
Started May 14 03:03:10 PM PDT 24
Finished May 14 03:16:04 PM PDT 24
Peak memory 201788 kb
Host smart-04a025ab-1348-46c8-8242-71aefa619ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99937943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.99937943
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1118994263
Short name T332
Test name
Test status
Simulation time 416845353278 ps
CPU time 218.46 seconds
Started May 14 03:03:09 PM PDT 24
Finished May 14 03:06:49 PM PDT 24
Peak memory 210176 kb
Host smart-dcbf300d-b307-476f-aab6-e7ae3493363a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118994263 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1118994263
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2912977234
Short name T749
Test name
Test status
Simulation time 312242622 ps
CPU time 0.8 seconds
Started May 14 03:03:30 PM PDT 24
Finished May 14 03:03:32 PM PDT 24
Peak memory 201432 kb
Host smart-c8b6f547-db0d-4db7-9b7f-32981af0eda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912977234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2912977234
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2139609034
Short name T555
Test name
Test status
Simulation time 169532594408 ps
CPU time 96.02 seconds
Started May 14 03:03:20 PM PDT 24
Finished May 14 03:04:57 PM PDT 24
Peak memory 201844 kb
Host smart-27f2ddaa-10e7-48ef-afd0-bceb6e2c2157
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139609034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2139609034
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4240381959
Short name T736
Test name
Test status
Simulation time 176937573932 ps
CPU time 108.21 seconds
Started May 14 03:03:19 PM PDT 24
Finished May 14 03:05:08 PM PDT 24
Peak memory 201828 kb
Host smart-345a075e-f854-4125-8a43-4e52727fac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240381959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4240381959
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1659979933
Short name T265
Test name
Test status
Simulation time 164720486572 ps
CPU time 375.39 seconds
Started May 14 03:03:17 PM PDT 24
Finished May 14 03:09:33 PM PDT 24
Peak memory 201728 kb
Host smart-e959ae4f-3e84-4282-b0f0-892d0b39acdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659979933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1659979933
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1353233676
Short name T753
Test name
Test status
Simulation time 332011470616 ps
CPU time 233.89 seconds
Started May 14 03:03:19 PM PDT 24
Finished May 14 03:07:14 PM PDT 24
Peak memory 201864 kb
Host smart-ec9e291b-f514-4422-b684-524db867ecde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353233676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1353233676
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3569964907
Short name T266
Test name
Test status
Simulation time 169959264058 ps
CPU time 200.48 seconds
Started May 14 03:03:19 PM PDT 24
Finished May 14 03:06:40 PM PDT 24
Peak memory 201856 kb
Host smart-b537b55e-ee03-49c9-8cf9-ad47adc10c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569964907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3569964907
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1507716924
Short name T456
Test name
Test status
Simulation time 162411475567 ps
CPU time 207.35 seconds
Started May 14 03:03:17 PM PDT 24
Finished May 14 03:06:45 PM PDT 24
Peak memory 201804 kb
Host smart-9f1f86a2-64a5-40cb-8dbe-14abb87beed4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507716924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1507716924
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1167652909
Short name T437
Test name
Test status
Simulation time 595234226476 ps
CPU time 1484.31 seconds
Started May 14 03:03:18 PM PDT 24
Finished May 14 03:28:04 PM PDT 24
Peak memory 202032 kb
Host smart-bff412d1-681d-4419-94cb-37a4789a164e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167652909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1167652909
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2992476669
Short name T692
Test name
Test status
Simulation time 83903878116 ps
CPU time 283.81 seconds
Started May 14 03:03:28 PM PDT 24
Finished May 14 03:08:13 PM PDT 24
Peak memory 202072 kb
Host smart-35df2de7-2f7e-4b97-8fe9-056967079fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992476669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2992476669
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1426485957
Short name T464
Test name
Test status
Simulation time 42700507680 ps
CPU time 25.91 seconds
Started May 14 03:03:27 PM PDT 24
Finished May 14 03:03:54 PM PDT 24
Peak memory 201608 kb
Host smart-a7f2611a-d6d2-4e6e-b79a-b2b4d24699ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426485957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1426485957
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3941528335
Short name T367
Test name
Test status
Simulation time 4203903465 ps
CPU time 10.78 seconds
Started May 14 03:03:30 PM PDT 24
Finished May 14 03:03:42 PM PDT 24
Peak memory 201496 kb
Host smart-dc859e33-297a-4625-9a4c-4591ede7b9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941528335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3941528335
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2698741484
Short name T352
Test name
Test status
Simulation time 6055919434 ps
CPU time 14.11 seconds
Started May 14 03:03:18 PM PDT 24
Finished May 14 03:03:33 PM PDT 24
Peak memory 201668 kb
Host smart-8fab4dcf-e0ca-42cf-8f3f-93c0bd39bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698741484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2698741484
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.78509767
Short name T526
Test name
Test status
Simulation time 369657758041 ps
CPU time 137.14 seconds
Started May 14 03:03:27 PM PDT 24
Finished May 14 03:05:46 PM PDT 24
Peak memory 201836 kb
Host smart-a974f6e9-218e-43ec-8523-324462669ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78509767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.78509767
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.470087758
Short name T16
Test name
Test status
Simulation time 128830886306 ps
CPU time 138.22 seconds
Started May 14 03:03:32 PM PDT 24
Finished May 14 03:05:52 PM PDT 24
Peak memory 201900 kb
Host smart-6d0f7a68-3c4b-41c5-96ab-2b0913cb6ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470087758 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.470087758
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4018668268
Short name T795
Test name
Test status
Simulation time 314398064 ps
CPU time 1.3 seconds
Started May 14 03:03:39 PM PDT 24
Finished May 14 03:03:41 PM PDT 24
Peak memory 201492 kb
Host smart-e3a3c4a9-e3b6-4ba5-8db4-6531ca499751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018668268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4018668268
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1862481843
Short name T662
Test name
Test status
Simulation time 208149425554 ps
CPU time 466.2 seconds
Started May 14 03:03:28 PM PDT 24
Finished May 14 03:11:16 PM PDT 24
Peak memory 201956 kb
Host smart-9f272dbe-cb91-4a57-9eea-60ed6882eaf8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862481843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1862481843
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1638602737
Short name T656
Test name
Test status
Simulation time 179312751790 ps
CPU time 111.22 seconds
Started May 14 03:03:27 PM PDT 24
Finished May 14 03:05:20 PM PDT 24
Peak memory 201840 kb
Host smart-67b41e15-b7bc-4c2b-9265-e8a932ff72ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638602737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1638602737
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3994230096
Short name T694
Test name
Test status
Simulation time 494704429812 ps
CPU time 180.78 seconds
Started May 14 03:03:27 PM PDT 24
Finished May 14 03:06:29 PM PDT 24
Peak memory 201856 kb
Host smart-67a8b838-4f18-45c3-855b-9bfaeaf5666b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994230096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3994230096
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1576743055
Short name T754
Test name
Test status
Simulation time 326495051304 ps
CPU time 176.51 seconds
Started May 14 03:03:32 PM PDT 24
Finished May 14 03:06:30 PM PDT 24
Peak memory 201776 kb
Host smart-531c14d7-9e4d-4573-b3b9-a7526a68849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576743055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1576743055
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3245622865
Short name T562
Test name
Test status
Simulation time 499085021535 ps
CPU time 1175.42 seconds
Started May 14 03:03:27 PM PDT 24
Finished May 14 03:23:05 PM PDT 24
Peak memory 201756 kb
Host smart-a735f3cb-344d-4942-a0c7-905d8f17043f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245622865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3245622865
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3418141080
Short name T157
Test name
Test status
Simulation time 167188529566 ps
CPU time 104.32 seconds
Started May 14 03:03:28 PM PDT 24
Finished May 14 03:05:14 PM PDT 24
Peak memory 201804 kb
Host smart-91317ef0-24e5-455e-9705-7dda1a129b91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418141080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3418141080
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2939171468
Short name T635
Test name
Test status
Simulation time 211593518403 ps
CPU time 488.78 seconds
Started May 14 03:03:31 PM PDT 24
Finished May 14 03:11:42 PM PDT 24
Peak memory 201784 kb
Host smart-261f33c1-184e-477e-8099-4ca61e99548d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939171468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2939171468
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2080442746
Short name T652
Test name
Test status
Simulation time 104580491107 ps
CPU time 576.01 seconds
Started May 14 03:03:37 PM PDT 24
Finished May 14 03:13:14 PM PDT 24
Peak memory 202176 kb
Host smart-f02b6479-aef1-4f88-a428-b9dff55ddccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080442746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2080442746
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1456489335
Short name T421
Test name
Test status
Simulation time 46064701057 ps
CPU time 94.85 seconds
Started May 14 03:03:38 PM PDT 24
Finished May 14 03:05:13 PM PDT 24
Peak memory 201652 kb
Host smart-626543c2-b551-4427-a921-d1ac878677f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456489335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1456489335
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1317336257
Short name T559
Test name
Test status
Simulation time 4252133800 ps
CPU time 10.99 seconds
Started May 14 03:03:36 PM PDT 24
Finished May 14 03:03:48 PM PDT 24
Peak memory 201636 kb
Host smart-d6d42d77-32b3-455f-9c4a-1302f1bbc809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317336257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1317336257
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1968056973
Short name T410
Test name
Test status
Simulation time 5897827841 ps
CPU time 8.09 seconds
Started May 14 03:03:33 PM PDT 24
Finished May 14 03:03:42 PM PDT 24
Peak memory 201624 kb
Host smart-83d0465b-e361-49bc-ae4e-d0364fe1f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968056973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1968056973
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4216208921
Short name T24
Test name
Test status
Simulation time 486200764691 ps
CPU time 108.64 seconds
Started May 14 03:03:36 PM PDT 24
Finished May 14 03:05:26 PM PDT 24
Peak memory 201736 kb
Host smart-9712665a-0d36-41a1-bdd3-e555a3487897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216208921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4216208921
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.785753199
Short name T336
Test name
Test status
Simulation time 323472322715 ps
CPU time 145.18 seconds
Started May 14 03:03:36 PM PDT 24
Finished May 14 03:06:02 PM PDT 24
Peak memory 210728 kb
Host smart-90763164-cc61-40c1-b231-3266e3fc048c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785753199 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.785753199
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.44122168
Short name T448
Test name
Test status
Simulation time 539848068 ps
CPU time 0.93 seconds
Started May 14 03:03:55 PM PDT 24
Finished May 14 03:03:57 PM PDT 24
Peak memory 201616 kb
Host smart-ec0d790b-5d76-4bea-93a3-efb13edbc228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44122168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.44122168
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1941890823
Short name T130
Test name
Test status
Simulation time 194147531900 ps
CPU time 216.14 seconds
Started May 14 03:03:43 PM PDT 24
Finished May 14 03:07:21 PM PDT 24
Peak memory 201804 kb
Host smart-b8c59782-fc85-401f-b421-0988db1149f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941890823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1941890823
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3503377379
Short name T311
Test name
Test status
Simulation time 178534256050 ps
CPU time 47.75 seconds
Started May 14 03:03:45 PM PDT 24
Finished May 14 03:04:33 PM PDT 24
Peak memory 201808 kb
Host smart-66a6a68b-beb3-4b65-bd84-b7bf5916e151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503377379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3503377379
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2497520075
Short name T138
Test name
Test status
Simulation time 327794669733 ps
CPU time 181.39 seconds
Started May 14 03:03:36 PM PDT 24
Finished May 14 03:06:39 PM PDT 24
Peak memory 201852 kb
Host smart-d2820ab4-d842-429a-b1eb-8f08da9aa7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497520075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2497520075
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3012603064
Short name T427
Test name
Test status
Simulation time 161528776876 ps
CPU time 126.23 seconds
Started May 14 03:03:45 PM PDT 24
Finished May 14 03:05:52 PM PDT 24
Peak memory 201808 kb
Host smart-4b519f9e-4970-4e66-b1be-37de7d7cb097
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012603064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3012603064
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4208493344
Short name T740
Test name
Test status
Simulation time 166044338016 ps
CPU time 187.53 seconds
Started May 14 03:03:35 PM PDT 24
Finished May 14 03:06:43 PM PDT 24
Peak memory 201876 kb
Host smart-d9b28496-08cf-40be-b43d-ed9be888a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208493344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4208493344
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.78779626
Short name T650
Test name
Test status
Simulation time 498257533027 ps
CPU time 1167.77 seconds
Started May 14 03:03:37 PM PDT 24
Finished May 14 03:23:06 PM PDT 24
Peak memory 201812 kb
Host smart-c01460da-4515-4268-a5cf-4d98945ddf0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=78779626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed
.78779626
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1318516626
Short name T343
Test name
Test status
Simulation time 196138321212 ps
CPU time 79.74 seconds
Started May 14 03:03:44 PM PDT 24
Finished May 14 03:05:05 PM PDT 24
Peak memory 201888 kb
Host smart-2f0ff6f3-828c-408d-8851-c5b3c022dda7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318516626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1318516626
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.293129738
Short name T782
Test name
Test status
Simulation time 202365256319 ps
CPU time 122.12 seconds
Started May 14 03:03:45 PM PDT 24
Finished May 14 03:05:48 PM PDT 24
Peak memory 201844 kb
Host smart-3a884386-f3ff-481a-ad4e-bf560e967997
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293129738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.293129738
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2209111757
Short name T212
Test name
Test status
Simulation time 108367928939 ps
CPU time 329.13 seconds
Started May 14 03:03:55 PM PDT 24
Finished May 14 03:09:25 PM PDT 24
Peak memory 202164 kb
Host smart-0d05e4eb-230b-4a22-84e8-264753ca378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209111757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2209111757
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2863539266
Short name T361
Test name
Test status
Simulation time 33787503079 ps
CPU time 19.95 seconds
Started May 14 03:03:54 PM PDT 24
Finished May 14 03:04:15 PM PDT 24
Peak memory 201744 kb
Host smart-307edf04-3955-439c-beee-3a22d7f8a252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863539266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2863539266
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1862415797
Short name T440
Test name
Test status
Simulation time 3915073176 ps
CPU time 3.03 seconds
Started May 14 03:03:44 PM PDT 24
Finished May 14 03:03:48 PM PDT 24
Peak memory 201584 kb
Host smart-ffba7e47-c850-4919-b22f-9ad7c4196b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862415797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1862415797
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1047709073
Short name T75
Test name
Test status
Simulation time 6020708607 ps
CPU time 15.28 seconds
Started May 14 03:03:37 PM PDT 24
Finished May 14 03:03:53 PM PDT 24
Peak memory 201668 kb
Host smart-231cfdac-7dc0-41c8-bcdf-76f258849f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047709073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1047709073
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1786429146
Short name T489
Test name
Test status
Simulation time 492417387 ps
CPU time 1.75 seconds
Started May 14 03:04:10 PM PDT 24
Finished May 14 03:04:12 PM PDT 24
Peak memory 201484 kb
Host smart-96c3398c-2e54-4f96-9161-6582f448fc69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786429146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1786429146
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3350132098
Short name T743
Test name
Test status
Simulation time 328587294592 ps
CPU time 382.84 seconds
Started May 14 03:04:01 PM PDT 24
Finished May 14 03:10:26 PM PDT 24
Peak memory 201796 kb
Host smart-2442e0fe-b0fc-4103-bef1-da878fedc414
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350132098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3350132098
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3207235931
Short name T634
Test name
Test status
Simulation time 325687516197 ps
CPU time 368.33 seconds
Started May 14 03:04:01 PM PDT 24
Finished May 14 03:10:11 PM PDT 24
Peak memory 201732 kb
Host smart-4736b910-9359-4522-aa71-7d8aa11205fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207235931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3207235931
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3905846969
Short name T498
Test name
Test status
Simulation time 328962920963 ps
CPU time 203.52 seconds
Started May 14 03:04:00 PM PDT 24
Finished May 14 03:07:25 PM PDT 24
Peak memory 201860 kb
Host smart-8aa2446d-00e3-4584-a462-1ada59fc8645
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905846969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3905846969
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1518745499
Short name T685
Test name
Test status
Simulation time 491830106674 ps
CPU time 301.64 seconds
Started May 14 03:03:54 PM PDT 24
Finished May 14 03:08:56 PM PDT 24
Peak memory 201868 kb
Host smart-2c949cc8-3fd9-4715-867b-38f2fa8bd84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518745499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1518745499
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.565008192
Short name T713
Test name
Test status
Simulation time 495985104213 ps
CPU time 1239.93 seconds
Started May 14 03:04:00 PM PDT 24
Finished May 14 03:24:42 PM PDT 24
Peak memory 201840 kb
Host smart-7c3ff46f-f4a4-48c7-803d-fdc8c4d25dac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=565008192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.565008192
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1638478340
Short name T187
Test name
Test status
Simulation time 404039444862 ps
CPU time 975.18 seconds
Started May 14 03:04:01 PM PDT 24
Finished May 14 03:20:18 PM PDT 24
Peak memory 201856 kb
Host smart-3007168c-ffd3-4d13-829f-6a3be53106db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638478340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1638478340
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1153961268
Short name T96
Test name
Test status
Simulation time 131719879413 ps
CPU time 533.86 seconds
Started May 14 03:04:10 PM PDT 24
Finished May 14 03:13:05 PM PDT 24
Peak memory 202156 kb
Host smart-42a18833-bd94-4dfb-9a73-6c8dc7a9d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153961268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1153961268
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2612007249
Short name T79
Test name
Test status
Simulation time 35032028101 ps
CPU time 71.04 seconds
Started May 14 03:04:01 PM PDT 24
Finished May 14 03:05:14 PM PDT 24
Peak memory 201596 kb
Host smart-713b59cd-8c93-43f8-8ebc-c9bc112dc5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612007249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2612007249
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.405353373
Short name T604
Test name
Test status
Simulation time 3174982229 ps
CPU time 3.04 seconds
Started May 14 03:04:01 PM PDT 24
Finished May 14 03:04:06 PM PDT 24
Peak memory 201532 kb
Host smart-2f2fb1e8-b26c-45e1-a2b6-ab454b4e2ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405353373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.405353373
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1519149230
Short name T569
Test name
Test status
Simulation time 5732357896 ps
CPU time 4.43 seconds
Started May 14 03:03:56 PM PDT 24
Finished May 14 03:04:01 PM PDT 24
Peak memory 201568 kb
Host smart-44ca855a-4980-4754-8a3f-5bb63e984ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519149230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1519149230
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3904645580
Short name T679
Test name
Test status
Simulation time 245790471030 ps
CPU time 496.03 seconds
Started May 14 03:04:09 PM PDT 24
Finished May 14 03:12:26 PM PDT 24
Peak memory 201808 kb
Host smart-a1ee254a-d270-4473-9a28-ba6c00ec3451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904645580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3904645580
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2516209332
Short name T20
Test name
Test status
Simulation time 26895864345 ps
CPU time 77.92 seconds
Started May 14 03:04:08 PM PDT 24
Finished May 14 03:05:27 PM PDT 24
Peak memory 210488 kb
Host smart-212f9b1e-3646-4850-bdfe-4679184800d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516209332 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2516209332
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3692253215
Short name T699
Test name
Test status
Simulation time 345775091 ps
CPU time 0.76 seconds
Started May 14 03:04:25 PM PDT 24
Finished May 14 03:04:27 PM PDT 24
Peak memory 201508 kb
Host smart-bbd28890-0d68-43ae-ac89-b5eb4afb1f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692253215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3692253215
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2696757800
Short name T798
Test name
Test status
Simulation time 500441282097 ps
CPU time 1070.65 seconds
Started May 14 03:04:19 PM PDT 24
Finished May 14 03:22:12 PM PDT 24
Peak memory 201852 kb
Host smart-d490a310-ed26-4479-aa07-8095f92b5565
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696757800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2696757800
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1260561561
Short name T202
Test name
Test status
Simulation time 515849555406 ps
CPU time 136.39 seconds
Started May 14 03:04:20 PM PDT 24
Finished May 14 03:06:39 PM PDT 24
Peak memory 201732 kb
Host smart-f2942535-fba4-42e0-a94e-2bb7e78932f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260561561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1260561561
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1797452257
Short name T163
Test name
Test status
Simulation time 493683239355 ps
CPU time 289.88 seconds
Started May 14 03:04:19 PM PDT 24
Finished May 14 03:09:11 PM PDT 24
Peak memory 201776 kb
Host smart-79ffcd28-8f58-40c7-a5b6-159b9150b520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797452257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1797452257
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1100185577
Short name T394
Test name
Test status
Simulation time 489053443085 ps
CPU time 1120.84 seconds
Started May 14 03:04:18 PM PDT 24
Finished May 14 03:23:02 PM PDT 24
Peak memory 201780 kb
Host smart-86c98ff9-eb08-44b7-a3a6-9601d86f4a7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100185577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1100185577
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3107506018
Short name T757
Test name
Test status
Simulation time 170842964273 ps
CPU time 406.97 seconds
Started May 14 03:04:09 PM PDT 24
Finished May 14 03:10:57 PM PDT 24
Peak memory 201828 kb
Host smart-15b1ee86-0214-4a00-84b8-054e469a1693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107506018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3107506018
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1832502012
Short name T515
Test name
Test status
Simulation time 486639183491 ps
CPU time 280.5 seconds
Started May 14 03:04:17 PM PDT 24
Finished May 14 03:09:00 PM PDT 24
Peak memory 201776 kb
Host smart-10dced0c-e044-4e59-95d6-13db57b3d918
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832502012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1832502012
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3800533320
Short name T779
Test name
Test status
Simulation time 186574116456 ps
CPU time 469.17 seconds
Started May 14 03:04:17 PM PDT 24
Finished May 14 03:12:08 PM PDT 24
Peak memory 201776 kb
Host smart-8b899d08-78fb-4076-befa-9ebc22ced18f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800533320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3800533320
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3864556357
Short name T161
Test name
Test status
Simulation time 195632135792 ps
CPU time 62.84 seconds
Started May 14 03:04:20 PM PDT 24
Finished May 14 03:05:25 PM PDT 24
Peak memory 201720 kb
Host smart-e377d6ba-4e93-4366-870d-ad27f3d93017
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864556357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3864556357
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3526194020
Short name T672
Test name
Test status
Simulation time 31968321830 ps
CPU time 72.45 seconds
Started May 14 03:04:17 PM PDT 24
Finished May 14 03:05:32 PM PDT 24
Peak memory 201664 kb
Host smart-93e88ecd-e045-4397-ab22-2af8e4563313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526194020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3526194020
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1084802082
Short name T800
Test name
Test status
Simulation time 3198490143 ps
CPU time 4.16 seconds
Started May 14 03:04:18 PM PDT 24
Finished May 14 03:04:25 PM PDT 24
Peak memory 201560 kb
Host smart-3c74a821-0067-4c18-83b8-da26b187b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084802082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1084802082
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.527489873
Short name T420
Test name
Test status
Simulation time 5891582826 ps
CPU time 4.1 seconds
Started May 14 03:04:09 PM PDT 24
Finished May 14 03:04:14 PM PDT 24
Peak memory 201568 kb
Host smart-0c9e816a-ddfa-42e3-ba78-bdb1782c758d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527489873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.527489873
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2235652555
Short name T166
Test name
Test status
Simulation time 337944024479 ps
CPU time 702.19 seconds
Started May 14 03:04:26 PM PDT 24
Finished May 14 03:16:10 PM PDT 24
Peak memory 201900 kb
Host smart-c4325066-eede-4e8f-a8b9-84426f1b084f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235652555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2235652555
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1695369864
Short name T45
Test name
Test status
Simulation time 275474096803 ps
CPU time 466.19 seconds
Started May 14 03:04:27 PM PDT 24
Finished May 14 03:12:14 PM PDT 24
Peak memory 210416 kb
Host smart-44af25e8-2ac6-49fd-99a3-7bb12f24d936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695369864 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1695369864
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.408162795
Short name T56
Test name
Test status
Simulation time 520695686 ps
CPU time 1.75 seconds
Started May 14 03:04:35 PM PDT 24
Finished May 14 03:04:38 PM PDT 24
Peak memory 201616 kb
Host smart-31f52f31-b7c4-4a6c-a5b8-52bd641f87ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408162795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.408162795
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3285327658
Short name T683
Test name
Test status
Simulation time 202174815364 ps
CPU time 206.81 seconds
Started May 14 03:04:27 PM PDT 24
Finished May 14 03:07:55 PM PDT 24
Peak memory 201800 kb
Host smart-fd8e302c-d639-4681-ab9c-01eea44d9995
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285327658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3285327658
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4052800964
Short name T167
Test name
Test status
Simulation time 493036444110 ps
CPU time 115.44 seconds
Started May 14 03:04:27 PM PDT 24
Finished May 14 03:06:24 PM PDT 24
Peak memory 201784 kb
Host smart-b50aed17-b484-404e-a05b-4170378f37e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052800964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4052800964
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1992771929
Short name T451
Test name
Test status
Simulation time 165052218936 ps
CPU time 62.12 seconds
Started May 14 03:04:24 PM PDT 24
Finished May 14 03:05:27 PM PDT 24
Peak memory 201904 kb
Host smart-228ab57f-0e6d-4b67-a4ba-2d46479edfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992771929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1992771929
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2034337616
Short name T573
Test name
Test status
Simulation time 328561873712 ps
CPU time 417.74 seconds
Started May 14 03:04:24 PM PDT 24
Finished May 14 03:11:24 PM PDT 24
Peak memory 201912 kb
Host smart-7bf36434-44e9-4265-ae7e-a29c425adfd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034337616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2034337616
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3499458887
Short name T738
Test name
Test status
Simulation time 328532708822 ps
CPU time 203.95 seconds
Started May 14 03:04:26 PM PDT 24
Finished May 14 03:07:51 PM PDT 24
Peak memory 201840 kb
Host smart-3689b43d-08ca-4f5c-a5e6-abcdb51c2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499458887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3499458887
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1080007146
Short name T516
Test name
Test status
Simulation time 484511250526 ps
CPU time 1064.5 seconds
Started May 14 03:04:24 PM PDT 24
Finished May 14 03:22:10 PM PDT 24
Peak memory 201768 kb
Host smart-12fd16b2-50be-4322-8e90-0c2dc3ecaed9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080007146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1080007146
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.280433805
Short name T272
Test name
Test status
Simulation time 204810291365 ps
CPU time 457.26 seconds
Started May 14 03:04:24 PM PDT 24
Finished May 14 03:12:02 PM PDT 24
Peak memory 201920 kb
Host smart-bb27d274-91c0-4be2-8098-e64cc4d6e582
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280433805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.280433805
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.223724774
Short name T543
Test name
Test status
Simulation time 408640196195 ps
CPU time 235.92 seconds
Started May 14 03:04:26 PM PDT 24
Finished May 14 03:08:23 PM PDT 24
Peak memory 201868 kb
Host smart-f309edeb-9191-4040-a5d3-c0e575993a13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223724774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.223724774
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1200347676
Short name T35
Test name
Test status
Simulation time 129765541581 ps
CPU time 527.33 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:13:22 PM PDT 24
Peak memory 202104 kb
Host smart-732a6c98-503f-40c1-ac6e-5ea4ebc2bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200347676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1200347676
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4162488538
Short name T90
Test name
Test status
Simulation time 36514010898 ps
CPU time 77.41 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:05:52 PM PDT 24
Peak memory 201620 kb
Host smart-2b958086-8b45-40ef-9567-1fb9947a8e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162488538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4162488538
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3981124347
Short name T473
Test name
Test status
Simulation time 4249698092 ps
CPU time 3.27 seconds
Started May 14 03:04:25 PM PDT 24
Finished May 14 03:04:30 PM PDT 24
Peak memory 201608 kb
Host smart-4d484460-42dc-4db4-9a86-fb8e703125c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981124347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3981124347
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2130735951
Short name T373
Test name
Test status
Simulation time 5884823649 ps
CPU time 5.4 seconds
Started May 14 03:04:25 PM PDT 24
Finished May 14 03:04:32 PM PDT 24
Peak memory 201760 kb
Host smart-a09e1e86-59dd-4c1e-9857-ebae6a56e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130735951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2130735951
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4026293289
Short name T93
Test name
Test status
Simulation time 1885633064100 ps
CPU time 593.28 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:14:28 PM PDT 24
Peak memory 210328 kb
Host smart-4881674d-290c-40a1-9032-c7bb111ef462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026293289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4026293289
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4043761090
Short name T737
Test name
Test status
Simulation time 147615902895 ps
CPU time 147.49 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:07:03 PM PDT 24
Peak memory 210408 kb
Host smart-b3259c9f-e581-41a5-8ceb-fe398e75a28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043761090 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4043761090
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1658722528
Short name T590
Test name
Test status
Simulation time 478094088 ps
CPU time 1.17 seconds
Started May 14 03:04:42 PM PDT 24
Finished May 14 03:04:45 PM PDT 24
Peak memory 201544 kb
Host smart-94abd3a2-7bd5-487c-8727-c01642f520ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658722528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1658722528
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3265090242
Short name T344
Test name
Test status
Simulation time 354379492291 ps
CPU time 125.3 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:06:40 PM PDT 24
Peak memory 201832 kb
Host smart-ce19fbf7-481f-40ad-98c0-4299faad92fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265090242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3265090242
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2078143259
Short name T132
Test name
Test status
Simulation time 331665163862 ps
CPU time 307.45 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:09:42 PM PDT 24
Peak memory 201748 kb
Host smart-71a1e65d-3d52-4916-b15c-e5fd10865bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078143259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2078143259
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2829577865
Short name T579
Test name
Test status
Simulation time 485080193008 ps
CPU time 1058.87 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:22:13 PM PDT 24
Peak memory 201916 kb
Host smart-7fc3d907-5e74-4f42-8b9e-9305e21ccef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829577865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2829577865
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1559228107
Short name T657
Test name
Test status
Simulation time 325908518339 ps
CPU time 56.75 seconds
Started May 14 03:04:36 PM PDT 24
Finished May 14 03:05:34 PM PDT 24
Peak memory 201824 kb
Host smart-bc4237c9-a1fb-47a3-a7b8-744408560aa0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559228107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1559228107
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.463864775
Short name T182
Test name
Test status
Simulation time 488515198838 ps
CPU time 270 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:09:05 PM PDT 24
Peak memory 201872 kb
Host smart-575dc985-4a62-4bcd-8eb2-70e79e2d4e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463864775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.463864775
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2864133158
Short name T376
Test name
Test status
Simulation time 327940919421 ps
CPU time 657.47 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:15:33 PM PDT 24
Peak memory 201876 kb
Host smart-ef914ca1-cc7d-4964-a43d-27d8c9416f25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864133158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2864133158
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3018510528
Short name T641
Test name
Test status
Simulation time 176980102446 ps
CPU time 77.65 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:05:53 PM PDT 24
Peak memory 201804 kb
Host smart-a1cf1a72-97b6-476c-8e94-04a382fe37a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018510528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3018510528
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2331999513
Short name T541
Test name
Test status
Simulation time 399560480665 ps
CPU time 911.85 seconds
Started May 14 03:04:35 PM PDT 24
Finished May 14 03:19:49 PM PDT 24
Peak memory 201820 kb
Host smart-f23ae11a-95ef-4b40-bdbe-2d68c4e90760
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331999513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2331999513
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.463129040
Short name T505
Test name
Test status
Simulation time 78327108181 ps
CPU time 259.36 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:08:53 PM PDT 24
Peak memory 202164 kb
Host smart-4dcec281-70c7-49d5-ae6c-fd90542c373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463129040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.463129040
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3722139640
Short name T2
Test name
Test status
Simulation time 46787500459 ps
CPU time 25.09 seconds
Started May 14 03:04:35 PM PDT 24
Finished May 14 03:05:01 PM PDT 24
Peak memory 201632 kb
Host smart-01f6bdcc-6e9c-4937-bd28-cc6277e6060b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722139640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3722139640
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3706280601
Short name T389
Test name
Test status
Simulation time 3749953324 ps
CPU time 8.91 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:04:45 PM PDT 24
Peak memory 201684 kb
Host smart-7b388f8b-1e5e-4aaa-ad72-f0e655c3b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706280601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3706280601
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.915878984
Short name T395
Test name
Test status
Simulation time 5553803310 ps
CPU time 6.48 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:04:42 PM PDT 24
Peak memory 201628 kb
Host smart-199e549f-d604-44c3-b7ea-0b3bbeaec5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915878984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.915878984
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4216389837
Short name T321
Test name
Test status
Simulation time 498197437912 ps
CPU time 287.56 seconds
Started May 14 03:04:34 PM PDT 24
Finished May 14 03:09:24 PM PDT 24
Peak memory 201868 kb
Host smart-fdd40c47-de9b-4a82-abca-cce2c53a369e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216389837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4216389837
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.93572539
Short name T81
Test name
Test status
Simulation time 182255576661 ps
CPU time 256.97 seconds
Started May 14 03:04:33 PM PDT 24
Finished May 14 03:08:51 PM PDT 24
Peak memory 210460 kb
Host smart-553ac213-f3a5-4108-9d2c-86535079b05a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93572539 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.93572539
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.409089249
Short name T527
Test name
Test status
Simulation time 508494372 ps
CPU time 1.83 seconds
Started May 14 03:04:52 PM PDT 24
Finished May 14 03:04:55 PM PDT 24
Peak memory 201616 kb
Host smart-4d673fd9-0205-4f87-8084-f09473a2be20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409089249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.409089249
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.546355450
Short name T684
Test name
Test status
Simulation time 173612880179 ps
CPU time 97.46 seconds
Started May 14 03:04:42 PM PDT 24
Finished May 14 03:06:21 PM PDT 24
Peak memory 201828 kb
Host smart-be6a1a6d-2d6c-472b-beb1-4ae88073eca5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546355450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.546355450
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3746961160
Short name T269
Test name
Test status
Simulation time 516160257126 ps
CPU time 581.08 seconds
Started May 14 03:04:51 PM PDT 24
Finished May 14 03:14:34 PM PDT 24
Peak memory 201868 kb
Host smart-af9ae1f0-7306-43d0-95c9-2d38a43362a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746961160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3746961160
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1107696243
Short name T201
Test name
Test status
Simulation time 485341892885 ps
CPU time 293.2 seconds
Started May 14 03:04:43 PM PDT 24
Finished May 14 03:09:37 PM PDT 24
Peak memory 201700 kb
Host smart-b0426c64-5a06-4e57-97ad-7d574e065b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107696243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1107696243
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1893930055
Short name T379
Test name
Test status
Simulation time 495270331683 ps
CPU time 585.85 seconds
Started May 14 03:04:44 PM PDT 24
Finished May 14 03:14:31 PM PDT 24
Peak memory 201728 kb
Host smart-76f29d24-e44e-4fd2-91d4-92987be64500
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893930055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1893930055
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3890727335
Short name T148
Test name
Test status
Simulation time 322069127625 ps
CPU time 65.64 seconds
Started May 14 03:04:43 PM PDT 24
Finished May 14 03:05:50 PM PDT 24
Peak memory 201940 kb
Host smart-08d3b93d-ffea-4dc8-b8cf-f9efb2bf8655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890727335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3890727335
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.501149420
Short name T645
Test name
Test status
Simulation time 169088126770 ps
CPU time 390.57 seconds
Started May 14 03:04:44 PM PDT 24
Finished May 14 03:11:15 PM PDT 24
Peak memory 201708 kb
Host smart-5b4c9b73-319d-4dab-9078-c131543e4fcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=501149420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.501149420
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2393573278
Short name T770
Test name
Test status
Simulation time 230352741206 ps
CPU time 125.28 seconds
Started May 14 03:04:42 PM PDT 24
Finished May 14 03:06:49 PM PDT 24
Peak memory 201924 kb
Host smart-e09673b9-4d03-460b-affc-1ea95ba752f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393573278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2393573278
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3859245075
Short name T632
Test name
Test status
Simulation time 606928314310 ps
CPU time 352.45 seconds
Started May 14 03:04:43 PM PDT 24
Finished May 14 03:10:37 PM PDT 24
Peak memory 201920 kb
Host smart-0c887e46-5096-4795-8ec7-3c891eed9bbc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859245075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3859245075
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2462309363
Short name T415
Test name
Test status
Simulation time 31211513301 ps
CPU time 18.12 seconds
Started May 14 03:04:50 PM PDT 24
Finished May 14 03:05:09 PM PDT 24
Peak memory 201552 kb
Host smart-fd71d3dc-6121-45d6-ad4e-195d1861513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462309363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2462309363
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3346481603
Short name T384
Test name
Test status
Simulation time 4351108821 ps
CPU time 11.92 seconds
Started May 14 03:04:58 PM PDT 24
Finished May 14 03:05:10 PM PDT 24
Peak memory 201684 kb
Host smart-9778697c-a3ba-4aa2-a4f7-c5fadbd78e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346481603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3346481603
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1461386889
Short name T357
Test name
Test status
Simulation time 5743606806 ps
CPU time 7.7 seconds
Started May 14 03:04:42 PM PDT 24
Finished May 14 03:04:51 PM PDT 24
Peak memory 201700 kb
Host smart-5f2b3b78-1130-4aa1-9abd-bd7e0b290e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461386889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1461386889
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4147393267
Short name T506
Test name
Test status
Simulation time 112769910297 ps
CPU time 616.54 seconds
Started May 14 03:04:53 PM PDT 24
Finished May 14 03:15:11 PM PDT 24
Peak memory 202168 kb
Host smart-09d190aa-397e-4ca7-b16f-0b6f8089e149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147393267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4147393267
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4094099302
Short name T718
Test name
Test status
Simulation time 486304425 ps
CPU time 0.89 seconds
Started May 14 03:05:13 PM PDT 24
Finished May 14 03:05:14 PM PDT 24
Peak memory 201580 kb
Host smart-fd76ab1f-c68a-4f60-8152-3573ce40d258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094099302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4094099302
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.316319128
Short name T164
Test name
Test status
Simulation time 375689017668 ps
CPU time 434.85 seconds
Started May 14 03:05:10 PM PDT 24
Finished May 14 03:12:26 PM PDT 24
Peak memory 201812 kb
Host smart-65d46f0a-e891-496e-8b41-152a7f898f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316319128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.316319128
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4255422036
Short name T602
Test name
Test status
Simulation time 323620453184 ps
CPU time 244.27 seconds
Started May 14 03:05:00 PM PDT 24
Finished May 14 03:09:06 PM PDT 24
Peak memory 201808 kb
Host smart-17971592-43b4-45f5-b7bf-e561206183dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255422036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4255422036
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1576131249
Short name T649
Test name
Test status
Simulation time 338666804349 ps
CPU time 767.4 seconds
Started May 14 03:05:02 PM PDT 24
Finished May 14 03:17:51 PM PDT 24
Peak memory 201788 kb
Host smart-c0d9460e-d6ae-4012-a6c8-fb4367e10352
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576131249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1576131249
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.974358662
Short name T553
Test name
Test status
Simulation time 327796162447 ps
CPU time 736.55 seconds
Started May 14 03:05:01 PM PDT 24
Finished May 14 03:17:19 PM PDT 24
Peak memory 201876 kb
Host smart-00c072c3-74f9-4f5d-8b9b-89f0d7e408e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974358662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.974358662
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2848080158
Short name T601
Test name
Test status
Simulation time 169304509517 ps
CPU time 190.95 seconds
Started May 14 03:05:00 PM PDT 24
Finished May 14 03:08:12 PM PDT 24
Peak memory 201880 kb
Host smart-1647ce5d-7f93-4185-a50b-93f151491908
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848080158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2848080158
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1277107919
Short name T504
Test name
Test status
Simulation time 343024857477 ps
CPU time 849.21 seconds
Started May 14 03:05:02 PM PDT 24
Finished May 14 03:19:13 PM PDT 24
Peak memory 201792 kb
Host smart-47b59920-2959-4b29-809f-e72db14272ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277107919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1277107919
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1824572298
Short name T741
Test name
Test status
Simulation time 202225598734 ps
CPU time 489.82 seconds
Started May 14 03:05:00 PM PDT 24
Finished May 14 03:13:11 PM PDT 24
Peak memory 201856 kb
Host smart-57c86cc6-cc42-4dec-a504-3c89fd62d274
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824572298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1824572298
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2748764623
Short name T210
Test name
Test status
Simulation time 115197802552 ps
CPU time 633.32 seconds
Started May 14 03:05:13 PM PDT 24
Finished May 14 03:15:47 PM PDT 24
Peak memory 202244 kb
Host smart-649f525d-7e87-4642-8ac1-bff4cdc05777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748764623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2748764623
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.647873501
Short name T425
Test name
Test status
Simulation time 44306403066 ps
CPU time 27.86 seconds
Started May 14 03:05:09 PM PDT 24
Finished May 14 03:05:38 PM PDT 24
Peak memory 201668 kb
Host smart-6e21580f-14a9-4219-9536-cf7fd4a20116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647873501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.647873501
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3269609256
Short name T82
Test name
Test status
Simulation time 5500743092 ps
CPU time 3.73 seconds
Started May 14 03:05:11 PM PDT 24
Finished May 14 03:05:16 PM PDT 24
Peak memory 201744 kb
Host smart-c35cb349-a6d2-4f70-b2cd-a796f7b1cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269609256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3269609256
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1998965235
Short name T631
Test name
Test status
Simulation time 5924384858 ps
CPU time 7.99 seconds
Started May 14 03:05:00 PM PDT 24
Finished May 14 03:05:09 PM PDT 24
Peak memory 201704 kb
Host smart-9be7d681-8c34-48c4-a234-c27a847fc74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998965235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1998965235
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1729469797
Short name T237
Test name
Test status
Simulation time 84447454089 ps
CPU time 207.73 seconds
Started May 14 03:05:11 PM PDT 24
Finished May 14 03:08:40 PM PDT 24
Peak memory 210628 kb
Host smart-0c43eafd-dccd-4521-9430-f7135445acb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729469797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1729469797
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1400386057
Short name T173
Test name
Test status
Simulation time 444249383 ps
CPU time 0.87 seconds
Started May 14 02:57:54 PM PDT 24
Finished May 14 02:57:57 PM PDT 24
Peak memory 201492 kb
Host smart-c62ead00-1a65-4323-b24b-951e698e4b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400386057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1400386057
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1517957043
Short name T682
Test name
Test status
Simulation time 169536730337 ps
CPU time 197.86 seconds
Started May 14 02:57:42 PM PDT 24
Finished May 14 03:01:01 PM PDT 24
Peak memory 201796 kb
Host smart-0a8a71ff-ea48-4317-9149-ac794c9a6172
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517957043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1517957043
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.393133246
Short name T313
Test name
Test status
Simulation time 333478901925 ps
CPU time 130.77 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 02:59:45 PM PDT 24
Peak memory 201856 kb
Host smart-8be311f0-99db-4425-943b-94c35233e06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393133246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.393133246
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3715670488
Short name T383
Test name
Test status
Simulation time 493815066570 ps
CPU time 232.02 seconds
Started May 14 02:57:33 PM PDT 24
Finished May 14 03:01:26 PM PDT 24
Peak memory 201768 kb
Host smart-d5d45e62-7993-4334-a1e6-863697126ad6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715670488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3715670488
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3826749117
Short name T788
Test name
Test status
Simulation time 371646120314 ps
CPU time 928.12 seconds
Started May 14 02:57:44 PM PDT 24
Finished May 14 03:13:14 PM PDT 24
Peak memory 201920 kb
Host smart-86bdfb4b-9b4b-4fae-bf8b-fccd99ef96f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826749117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3826749117
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3191519094
Short name T206
Test name
Test status
Simulation time 206634930667 ps
CPU time 128.47 seconds
Started May 14 02:57:44 PM PDT 24
Finished May 14 02:59:54 PM PDT 24
Peak memory 201872 kb
Host smart-538684e9-ea3c-41c6-887a-17c57a2b10ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191519094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3191519094
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3521906608
Short name T651
Test name
Test status
Simulation time 104387247679 ps
CPU time 550.3 seconds
Started May 14 02:57:54 PM PDT 24
Finished May 14 03:07:06 PM PDT 24
Peak memory 202132 kb
Host smart-389660f2-030d-42c2-ab4a-49ee4b810f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521906608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3521906608
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2473749198
Short name T611
Test name
Test status
Simulation time 28361446559 ps
CPU time 72.21 seconds
Started May 14 02:57:54 PM PDT 24
Finished May 14 02:59:07 PM PDT 24
Peak memory 201560 kb
Host smart-82ef427d-6969-4c7c-ae3d-0556cc514c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473749198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2473749198
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3424285694
Short name T654
Test name
Test status
Simulation time 4207043975 ps
CPU time 5.77 seconds
Started May 14 02:57:55 PM PDT 24
Finished May 14 02:58:03 PM PDT 24
Peak memory 201596 kb
Host smart-02de3a80-3dcc-48d7-8ae5-d09b82634307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424285694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3424285694
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3849316467
Short name T51
Test name
Test status
Simulation time 8803393608 ps
CPU time 5.42 seconds
Started May 14 02:57:55 PM PDT 24
Finished May 14 02:58:02 PM PDT 24
Peak memory 218352 kb
Host smart-541557bb-3fa9-4b9e-87d8-429bcfb61e6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849316467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3849316467
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1103887427
Short name T771
Test name
Test status
Simulation time 5912032602 ps
CPU time 12.91 seconds
Started May 14 02:57:34 PM PDT 24
Finished May 14 02:57:48 PM PDT 24
Peak memory 201592 kb
Host smart-3e68f800-3cff-42d4-9f22-485c8ff3dcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103887427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1103887427
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.260670799
Short name T761
Test name
Test status
Simulation time 160833201844 ps
CPU time 404.75 seconds
Started May 14 02:57:55 PM PDT 24
Finished May 14 03:04:42 PM PDT 24
Peak memory 201804 kb
Host smart-7a297675-1edf-4322-b7e5-f427768289ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260670799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.260670799
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4242623445
Short name T25
Test name
Test status
Simulation time 19551383295 ps
CPU time 55.65 seconds
Started May 14 02:57:54 PM PDT 24
Finished May 14 02:58:52 PM PDT 24
Peak memory 210404 kb
Host smart-b1fff8a4-d386-4b1d-b117-654af68543b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242623445 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4242623445
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1044309731
Short name T386
Test name
Test status
Simulation time 313841990 ps
CPU time 1.34 seconds
Started May 14 03:05:31 PM PDT 24
Finished May 14 03:05:34 PM PDT 24
Peak memory 201544 kb
Host smart-135ff34f-a633-45ac-bb3b-1407f5e1e4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044309731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1044309731
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4213776659
Short name T4
Test name
Test status
Simulation time 162182818806 ps
CPU time 183.3 seconds
Started May 14 03:05:19 PM PDT 24
Finished May 14 03:08:23 PM PDT 24
Peak memory 201720 kb
Host smart-d9ae37c7-de24-41fc-bb76-ee506183cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213776659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4213776659
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2678139972
Short name T597
Test name
Test status
Simulation time 330540751991 ps
CPU time 731.19 seconds
Started May 14 03:05:20 PM PDT 24
Finished May 14 03:17:32 PM PDT 24
Peak memory 201876 kb
Host smart-361679bb-4924-4566-a0f0-f1c0a4c6fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678139972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2678139972
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.529276335
Short name T533
Test name
Test status
Simulation time 491467231935 ps
CPU time 546.24 seconds
Started May 14 03:05:20 PM PDT 24
Finished May 14 03:14:27 PM PDT 24
Peak memory 201808 kb
Host smart-7380aa14-44b2-4126-8933-f148f54c7ea4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=529276335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.529276335
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2799381455
Short name T786
Test name
Test status
Simulation time 164587301259 ps
CPU time 84.95 seconds
Started May 14 03:05:22 PM PDT 24
Finished May 14 03:06:48 PM PDT 24
Peak memory 201932 kb
Host smart-58a3813c-9162-439d-b584-f4f47abf0b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799381455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2799381455
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3630826025
Short name T687
Test name
Test status
Simulation time 331759163517 ps
CPU time 210.72 seconds
Started May 14 03:05:17 PM PDT 24
Finished May 14 03:08:49 PM PDT 24
Peak memory 201764 kb
Host smart-9fe5e242-0b06-4c1b-9021-eb4e82673af7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630826025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3630826025
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3729947387
Short name T500
Test name
Test status
Simulation time 493240412716 ps
CPU time 92.74 seconds
Started May 14 03:05:20 PM PDT 24
Finished May 14 03:06:53 PM PDT 24
Peak memory 201860 kb
Host smart-2dad8cec-cabf-405d-b621-b1bf37b4ef4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729947387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3729947387
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1427556119
Short name T365
Test name
Test status
Simulation time 410296399265 ps
CPU time 994.47 seconds
Started May 14 03:05:20 PM PDT 24
Finished May 14 03:21:55 PM PDT 24
Peak memory 201948 kb
Host smart-0ecd83ba-2375-44f5-8b63-3a719ab28a47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427556119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1427556119
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2539562148
Short name T215
Test name
Test status
Simulation time 87731831284 ps
CPU time 317.72 seconds
Started May 14 03:05:32 PM PDT 24
Finished May 14 03:10:51 PM PDT 24
Peak memory 202248 kb
Host smart-1c8aef92-1cf3-4ef3-b701-4b81cf66f70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539562148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2539562148
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3654905773
Short name T557
Test name
Test status
Simulation time 26694486435 ps
CPU time 15.51 seconds
Started May 14 03:05:33 PM PDT 24
Finished May 14 03:05:50 PM PDT 24
Peak memory 201608 kb
Host smart-8ce7bf23-c098-4f91-826e-156c0c8c170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654905773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3654905773
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2292878870
Short name T766
Test name
Test status
Simulation time 4304855677 ps
CPU time 2.74 seconds
Started May 14 03:05:19 PM PDT 24
Finished May 14 03:05:22 PM PDT 24
Peak memory 201612 kb
Host smart-ae91a028-b389-4912-bc0d-31380a48385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292878870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2292878870
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2442558156
Short name T430
Test name
Test status
Simulation time 5905722774 ps
CPU time 7.67 seconds
Started May 14 03:05:11 PM PDT 24
Finished May 14 03:05:20 PM PDT 24
Peak memory 201704 kb
Host smart-dcbc37d1-ad75-4100-905f-fd5c429b4c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442558156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2442558156
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4122451600
Short name T282
Test name
Test status
Simulation time 279243262553 ps
CPU time 545.68 seconds
Started May 14 03:05:31 PM PDT 24
Finished May 14 03:14:38 PM PDT 24
Peak memory 210384 kb
Host smart-ddbbd2d2-fc46-4b66-b75e-2d6f08b20897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122451600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4122451600
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3922770668
Short name T30
Test name
Test status
Simulation time 95532376506 ps
CPU time 187.37 seconds
Started May 14 03:05:32 PM PDT 24
Finished May 14 03:08:41 PM PDT 24
Peak memory 216364 kb
Host smart-14028b82-958c-49bd-952d-cd580880eb2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922770668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3922770668
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2168617208
Short name T388
Test name
Test status
Simulation time 471251067 ps
CPU time 1.65 seconds
Started May 14 03:05:42 PM PDT 24
Finished May 14 03:05:44 PM PDT 24
Peak memory 201568 kb
Host smart-1611b639-0f9b-44ac-bc9f-fb1cbd3aaf31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168617208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2168617208
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.184464377
Short name T258
Test name
Test status
Simulation time 159009842689 ps
CPU time 334.3 seconds
Started May 14 03:05:42 PM PDT 24
Finished May 14 03:11:18 PM PDT 24
Peak memory 201852 kb
Host smart-57408a43-1573-4255-9e62-c22e13eee250
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184464377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.184464377
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.766627426
Short name T196
Test name
Test status
Simulation time 496823525736 ps
CPU time 292.43 seconds
Started May 14 03:05:32 PM PDT 24
Finished May 14 03:10:26 PM PDT 24
Peak memory 201868 kb
Host smart-fb58c7a0-722e-45c6-9b93-9cbec18f2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766627426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.766627426
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.814807885
Short name T467
Test name
Test status
Simulation time 162873125464 ps
CPU time 398.13 seconds
Started May 14 03:05:30 PM PDT 24
Finished May 14 03:12:09 PM PDT 24
Peak memory 201740 kb
Host smart-436787b5-6f41-42e3-bdfa-c3019d57b5ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=814807885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.814807885
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3394531526
Short name T787
Test name
Test status
Simulation time 494218749809 ps
CPU time 282.78 seconds
Started May 14 03:05:31 PM PDT 24
Finished May 14 03:10:15 PM PDT 24
Peak memory 201868 kb
Host smart-e8e635eb-a815-49e0-b12f-81198c4d4ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394531526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3394531526
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3161390473
Short name T423
Test name
Test status
Simulation time 317400656492 ps
CPU time 743.56 seconds
Started May 14 03:05:34 PM PDT 24
Finished May 14 03:17:59 PM PDT 24
Peak memory 201764 kb
Host smart-ee5fb9be-2be6-4596-8e24-977c2d68f1dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161390473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3161390473
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1980380784
Short name T172
Test name
Test status
Simulation time 196518312308 ps
CPU time 66.75 seconds
Started May 14 03:05:32 PM PDT 24
Finished May 14 03:06:40 PM PDT 24
Peak memory 201996 kb
Host smart-bcda87ad-cd3b-4b28-930a-04ecfe2e2701
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980380784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1980380784
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.353364189
Short name T393
Test name
Test status
Simulation time 204134516772 ps
CPU time 235.62 seconds
Started May 14 03:05:31 PM PDT 24
Finished May 14 03:09:28 PM PDT 24
Peak memory 201864 kb
Host smart-410017db-9027-4cf1-898e-93b6a8281e59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353364189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.353364189
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2613693378
Short name T640
Test name
Test status
Simulation time 75534074100 ps
CPU time 319.87 seconds
Started May 14 03:05:40 PM PDT 24
Finished May 14 03:11:00 PM PDT 24
Peak memory 202104 kb
Host smart-52d25bd1-7115-4d98-a3e2-d3567707487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613693378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2613693378
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.895956213
Short name T728
Test name
Test status
Simulation time 39475017234 ps
CPU time 45.15 seconds
Started May 14 03:05:46 PM PDT 24
Finished May 14 03:06:32 PM PDT 24
Peak memory 201752 kb
Host smart-2a586777-d669-4205-9a6d-89c9d64c72bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895956213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.895956213
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.50607515
Short name T390
Test name
Test status
Simulation time 4866827297 ps
CPU time 3.65 seconds
Started May 14 03:05:42 PM PDT 24
Finished May 14 03:05:46 PM PDT 24
Peak memory 201652 kb
Host smart-8e40913d-5bc6-4c31-aed4-8520352f6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50607515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.50607515
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.513143893
Short name T512
Test name
Test status
Simulation time 5946328102 ps
CPU time 13.97 seconds
Started May 14 03:05:31 PM PDT 24
Finished May 14 03:05:46 PM PDT 24
Peak memory 201656 kb
Host smart-85deeab0-65f0-4fb4-aad7-388e0bdc1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513143893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.513143893
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4291431569
Short name T233
Test name
Test status
Simulation time 384161200109 ps
CPU time 487 seconds
Started May 14 03:05:43 PM PDT 24
Finished May 14 03:13:51 PM PDT 24
Peak memory 201696 kb
Host smart-34dbb357-27de-488a-930d-61c3144c870a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291431569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4291431569
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2580224136
Short name T19
Test name
Test status
Simulation time 30016982440 ps
CPU time 30.38 seconds
Started May 14 03:05:41 PM PDT 24
Finished May 14 03:06:12 PM PDT 24
Peak memory 201916 kb
Host smart-634d029d-e4b6-402b-88d1-31a988ae7f2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580224136 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2580224136
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4008791109
Short name T494
Test name
Test status
Simulation time 432301158 ps
CPU time 1.64 seconds
Started May 14 03:05:52 PM PDT 24
Finished May 14 03:05:55 PM PDT 24
Peak memory 201492 kb
Host smart-35a24f02-f2f3-46b6-9d86-7f367fa3fd37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008791109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4008791109
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.811870677
Short name T584
Test name
Test status
Simulation time 544098679568 ps
CPU time 1175.13 seconds
Started May 14 03:05:50 PM PDT 24
Finished May 14 03:25:26 PM PDT 24
Peak memory 201700 kb
Host smart-53804341-837f-4698-a72d-ee6a05b19b69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811870677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.811870677
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1925228480
Short name T613
Test name
Test status
Simulation time 163882721394 ps
CPU time 161.05 seconds
Started May 14 03:05:45 PM PDT 24
Finished May 14 03:08:28 PM PDT 24
Peak memory 201948 kb
Host smart-ef328290-351c-4db4-8916-91dc2ed52367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925228480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1925228480
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3425865042
Short name T701
Test name
Test status
Simulation time 484653889660 ps
CPU time 300.29 seconds
Started May 14 03:05:53 PM PDT 24
Finished May 14 03:10:54 PM PDT 24
Peak memory 201832 kb
Host smart-dc395154-6d27-4c61-809f-36a90906b1b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425865042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3425865042
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1124997827
Short name T721
Test name
Test status
Simulation time 501591902547 ps
CPU time 1186.89 seconds
Started May 14 03:05:41 PM PDT 24
Finished May 14 03:25:29 PM PDT 24
Peak memory 201712 kb
Host smart-aeff4d64-ccde-48ea-aebf-4497347213f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124997827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1124997827
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.735182260
Short name T756
Test name
Test status
Simulation time 492842321437 ps
CPU time 575.83 seconds
Started May 14 03:05:41 PM PDT 24
Finished May 14 03:15:18 PM PDT 24
Peak memory 201788 kb
Host smart-0694ed16-bca0-4851-8aee-95af63c4fa0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735182260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.735182260
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1370090045
Short name T487
Test name
Test status
Simulation time 203346825729 ps
CPU time 488.39 seconds
Started May 14 03:05:50 PM PDT 24
Finished May 14 03:13:59 PM PDT 24
Peak memory 201760 kb
Host smart-ad1bc07b-00d4-4fcf-ad3f-4b2d02349014
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370090045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1370090045
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3840580319
Short name T764
Test name
Test status
Simulation time 137426172432 ps
CPU time 710.1 seconds
Started May 14 03:05:54 PM PDT 24
Finished May 14 03:17:46 PM PDT 24
Peak memory 202164 kb
Host smart-c0d8e3e4-d51d-4260-9336-377808862cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840580319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3840580319
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1497556604
Short name T381
Test name
Test status
Simulation time 29516399455 ps
CPU time 71.51 seconds
Started May 14 03:05:52 PM PDT 24
Finished May 14 03:07:05 PM PDT 24
Peak memory 201660 kb
Host smart-3890f62b-c499-4d40-aefd-5f06f4c2650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497556604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1497556604
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1280912699
Short name T765
Test name
Test status
Simulation time 4358500102 ps
CPU time 1.41 seconds
Started May 14 03:05:54 PM PDT 24
Finished May 14 03:05:57 PM PDT 24
Peak memory 201672 kb
Host smart-f5775142-d00b-4b32-afd6-a3691cfaf7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280912699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1280912699
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.390848850
Short name T735
Test name
Test status
Simulation time 5749350622 ps
CPU time 4.33 seconds
Started May 14 03:05:45 PM PDT 24
Finished May 14 03:05:50 PM PDT 24
Peak memory 201764 kb
Host smart-d9ad858f-dc10-495f-8f1b-95e50ed1802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390848850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.390848850
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2731728843
Short name T691
Test name
Test status
Simulation time 77761108800 ps
CPU time 194.29 seconds
Started May 14 03:05:51 PM PDT 24
Finished May 14 03:09:07 PM PDT 24
Peak memory 210476 kb
Host smart-c9703ae1-f907-4895-a917-bd12daecfcb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731728843 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2731728843
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1974239656
Short name T171
Test name
Test status
Simulation time 346891353 ps
CPU time 0.79 seconds
Started May 14 03:06:12 PM PDT 24
Finished May 14 03:06:15 PM PDT 24
Peak memory 201488 kb
Host smart-cb5c1a13-adb2-406d-9c70-7a616e1c233e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974239656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1974239656
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.912078045
Short name T168
Test name
Test status
Simulation time 595030132657 ps
CPU time 853.9 seconds
Started May 14 03:05:59 PM PDT 24
Finished May 14 03:20:14 PM PDT 24
Peak memory 201876 kb
Host smart-7c49135d-8c75-4078-901e-bdfc339f1b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912078045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.912078045
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1784839439
Short name T315
Test name
Test status
Simulation time 167041955886 ps
CPU time 167.3 seconds
Started May 14 03:06:00 PM PDT 24
Finished May 14 03:08:49 PM PDT 24
Peak memory 201840 kb
Host smart-553c7cd7-9b5a-4608-a340-45d3c12b942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784839439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1784839439
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.348386267
Short name T638
Test name
Test status
Simulation time 324331568137 ps
CPU time 142.91 seconds
Started May 14 03:06:00 PM PDT 24
Finished May 14 03:08:24 PM PDT 24
Peak memory 201904 kb
Host smart-9b276cab-3ed4-48c8-ab4e-942a6f0b88a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=348386267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.348386267
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3970139387
Short name T307
Test name
Test status
Simulation time 325073349748 ps
CPU time 781.88 seconds
Started May 14 03:06:01 PM PDT 24
Finished May 14 03:19:04 PM PDT 24
Peak memory 201816 kb
Host smart-b500083c-e366-48bc-a23c-22b9ca801acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970139387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3970139387
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4010240920
Short name T154
Test name
Test status
Simulation time 335601986882 ps
CPU time 165.74 seconds
Started May 14 03:06:01 PM PDT 24
Finished May 14 03:08:49 PM PDT 24
Peak memory 201836 kb
Host smart-982f7b51-8637-4d98-8830-07e77895ef9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010240920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4010240920
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3445062720
Short name T345
Test name
Test status
Simulation time 182512261936 ps
CPU time 443.3 seconds
Started May 14 03:06:03 PM PDT 24
Finished May 14 03:13:28 PM PDT 24
Peak memory 201840 kb
Host smart-10836213-baea-4ddd-915c-3979a280860f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445062720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3445062720
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3863861625
Short name T586
Test name
Test status
Simulation time 390113419278 ps
CPU time 840.77 seconds
Started May 14 03:06:01 PM PDT 24
Finished May 14 03:20:03 PM PDT 24
Peak memory 201848 kb
Host smart-a707538e-4832-45e1-9205-93c077ec8d59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863861625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3863861625
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2830611230
Short name T216
Test name
Test status
Simulation time 122812363423 ps
CPU time 643.52 seconds
Started May 14 03:06:10 PM PDT 24
Finished May 14 03:16:55 PM PDT 24
Peak memory 202164 kb
Host smart-672b00cb-ae4a-45d4-8163-fcdb12919f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830611230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2830611230
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3693026145
Short name T491
Test name
Test status
Simulation time 24201258178 ps
CPU time 31.03 seconds
Started May 14 03:06:10 PM PDT 24
Finished May 14 03:06:42 PM PDT 24
Peak memory 201660 kb
Host smart-4fb02944-e921-4db1-bbb2-5c04976091e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693026145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3693026145
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.227370063
Short name T356
Test name
Test status
Simulation time 4020300668 ps
CPU time 3.34 seconds
Started May 14 03:06:13 PM PDT 24
Finished May 14 03:06:18 PM PDT 24
Peak memory 201580 kb
Host smart-e5b5b790-1f12-49bf-969d-b78a9e4587c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227370063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.227370063
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4015768416
Short name T785
Test name
Test status
Simulation time 5823651485 ps
CPU time 7.13 seconds
Started May 14 03:05:54 PM PDT 24
Finished May 14 03:06:03 PM PDT 24
Peak memory 201680 kb
Host smart-32d0ac4d-1730-49f6-ac58-71699823aee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015768416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4015768416
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3450504263
Short name T607
Test name
Test status
Simulation time 14347578179 ps
CPU time 9.91 seconds
Started May 14 03:06:13 PM PDT 24
Finished May 14 03:06:25 PM PDT 24
Peak memory 210124 kb
Host smart-44c9fd12-5ba3-486f-be89-a634e0c46ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450504263 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3450504263
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2524299705
Short name T689
Test name
Test status
Simulation time 358039520 ps
CPU time 0.73 seconds
Started May 14 03:06:19 PM PDT 24
Finished May 14 03:06:23 PM PDT 24
Peak memory 201580 kb
Host smart-dbc8c6a6-d7f4-442b-84d8-5bd6b3ae0a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524299705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2524299705
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4208025032
Short name T144
Test name
Test status
Simulation time 340444168241 ps
CPU time 155.48 seconds
Started May 14 03:06:18 PM PDT 24
Finished May 14 03:08:55 PM PDT 24
Peak memory 201864 kb
Host smart-747d02b8-b8bd-4500-8a96-9f1c79d40a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208025032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4208025032
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1281151742
Short name T529
Test name
Test status
Simulation time 328905199462 ps
CPU time 191.67 seconds
Started May 14 03:06:13 PM PDT 24
Finished May 14 03:09:26 PM PDT 24
Peak memory 201912 kb
Host smart-351d9f28-daef-45c6-8ef7-68d411953007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281151742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1281151742
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1500908522
Short name T203
Test name
Test status
Simulation time 167326099928 ps
CPU time 217.86 seconds
Started May 14 03:06:12 PM PDT 24
Finished May 14 03:09:51 PM PDT 24
Peak memory 201720 kb
Host smart-ba3fe9f1-ff4e-4c12-a078-fabbe77c2fd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500908522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1500908522
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1404625823
Short name T730
Test name
Test status
Simulation time 482134761431 ps
CPU time 267.02 seconds
Started May 14 03:06:11 PM PDT 24
Finished May 14 03:10:39 PM PDT 24
Peak memory 201712 kb
Host smart-0a770e02-95fd-418e-920e-70f562f53f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404625823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1404625823
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.935326886
Short name T355
Test name
Test status
Simulation time 162838614294 ps
CPU time 194.33 seconds
Started May 14 03:06:11 PM PDT 24
Finished May 14 03:09:26 PM PDT 24
Peak memory 201832 kb
Host smart-0d87ed5e-778a-4ef8-89f7-a5a4698d0126
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=935326886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.935326886
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1601344559
Short name T511
Test name
Test status
Simulation time 184900851743 ps
CPU time 95.5 seconds
Started May 14 03:06:11 PM PDT 24
Finished May 14 03:07:48 PM PDT 24
Peak memory 201852 kb
Host smart-57e8e775-6f06-4c82-a2aa-fd005aa6c22d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601344559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1601344559
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.117370981
Short name T719
Test name
Test status
Simulation time 388979155208 ps
CPU time 466.3 seconds
Started May 14 03:06:19 PM PDT 24
Finished May 14 03:14:07 PM PDT 24
Peak memory 201812 kb
Host smart-5fb26459-b927-41da-b031-ad8768561400
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117370981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.117370981
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.97112315
Short name T499
Test name
Test status
Simulation time 64890750957 ps
CPU time 222.62 seconds
Started May 14 03:06:19 PM PDT 24
Finished May 14 03:10:04 PM PDT 24
Peak memory 202372 kb
Host smart-e7f11f8f-16ef-4675-b2bf-8fb8bd6f6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97112315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.97112315
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2106893123
Short name T763
Test name
Test status
Simulation time 28325431206 ps
CPU time 20.8 seconds
Started May 14 03:06:19 PM PDT 24
Finished May 14 03:06:42 PM PDT 24
Peak memory 201552 kb
Host smart-f4b01582-6ecd-4131-8013-878ceae94447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106893123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2106893123
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1211470828
Short name T151
Test name
Test status
Simulation time 3122215981 ps
CPU time 1.95 seconds
Started May 14 03:06:20 PM PDT 24
Finished May 14 03:06:25 PM PDT 24
Peak memory 201584 kb
Host smart-6cfde598-096c-4bf6-a201-3228e5de9477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211470828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1211470828
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.554881135
Short name T382
Test name
Test status
Simulation time 5641745249 ps
CPU time 3.99 seconds
Started May 14 03:06:11 PM PDT 24
Finished May 14 03:06:17 PM PDT 24
Peak memory 201672 kb
Host smart-5af1adaa-3d54-4f31-b5a6-38fe4f4e92fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554881135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.554881135
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.929379250
Short name T23
Test name
Test status
Simulation time 138112183793 ps
CPU time 461.02 seconds
Started May 14 03:06:20 PM PDT 24
Finished May 14 03:14:03 PM PDT 24
Peak memory 210328 kb
Host smart-28870a64-de81-492f-94fc-a6dc5a2a8634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929379250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
929379250
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.147371825
Short name T314
Test name
Test status
Simulation time 28599982600 ps
CPU time 102.27 seconds
Started May 14 03:06:18 PM PDT 24
Finished May 14 03:08:02 PM PDT 24
Peak memory 210456 kb
Host smart-12cc0eee-818c-4e20-9b7b-7cb1de0df611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147371825 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.147371825
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.434232827
Short name T371
Test name
Test status
Simulation time 310261436 ps
CPU time 1.13 seconds
Started May 14 03:06:34 PM PDT 24
Finished May 14 03:06:36 PM PDT 24
Peak memory 201508 kb
Host smart-5ba028a0-6a61-4289-95b4-4e22c5720a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434232827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.434232827
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3384559447
Short name T261
Test name
Test status
Simulation time 368888618219 ps
CPU time 404.08 seconds
Started May 14 03:06:28 PM PDT 24
Finished May 14 03:13:13 PM PDT 24
Peak memory 201884 kb
Host smart-454c6541-3034-4eac-b59f-005ef90712fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384559447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3384559447
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3749917820
Short name T664
Test name
Test status
Simulation time 337350001810 ps
CPU time 170.73 seconds
Started May 14 03:06:29 PM PDT 24
Finished May 14 03:09:21 PM PDT 24
Peak memory 201824 kb
Host smart-1d53af7b-2381-48d0-b985-3884437d49fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749917820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3749917820
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.315486598
Short name T205
Test name
Test status
Simulation time 485893934206 ps
CPU time 1186.1 seconds
Started May 14 03:06:35 PM PDT 24
Finished May 14 03:26:24 PM PDT 24
Peak memory 201888 kb
Host smart-ea8bdb51-05d2-4aad-9496-0ce43a94d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315486598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.315486598
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3718144776
Short name T669
Test name
Test status
Simulation time 496981326579 ps
CPU time 250.93 seconds
Started May 14 03:06:34 PM PDT 24
Finished May 14 03:10:46 PM PDT 24
Peak memory 201920 kb
Host smart-661463cd-1faf-4c74-9444-7fd7245e86c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718144776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3718144776
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1693476523
Short name T617
Test name
Test status
Simulation time 480081595204 ps
CPU time 604.37 seconds
Started May 14 03:06:20 PM PDT 24
Finished May 14 03:16:27 PM PDT 24
Peak memory 201828 kb
Host smart-691c80dd-fc67-4755-9d3f-1e241bba0952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693476523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1693476523
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1305053701
Short name T729
Test name
Test status
Simulation time 160860544655 ps
CPU time 191.72 seconds
Started May 14 03:06:36 PM PDT 24
Finished May 14 03:09:50 PM PDT 24
Peak memory 201904 kb
Host smart-85834d2e-df49-41a4-acae-261531246ba6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305053701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1305053701
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1872798839
Short name T304
Test name
Test status
Simulation time 536387538515 ps
CPU time 600.25 seconds
Started May 14 03:06:28 PM PDT 24
Finished May 14 03:16:30 PM PDT 24
Peak memory 201832 kb
Host smart-5cd0f46c-e56d-4da3-bd39-4b0b97913e56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872798839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1872798839
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4132110505
Short name T796
Test name
Test status
Simulation time 398881982584 ps
CPU time 189.27 seconds
Started May 14 03:06:35 PM PDT 24
Finished May 14 03:09:47 PM PDT 24
Peak memory 201788 kb
Host smart-9d7c27db-0fa8-4c81-a8c3-ce9c1fff8653
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132110505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4132110505
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.926358041
Short name T37
Test name
Test status
Simulation time 132087771581 ps
CPU time 701.59 seconds
Started May 14 03:06:36 PM PDT 24
Finished May 14 03:18:20 PM PDT 24
Peak memory 201940 kb
Host smart-89604ca9-1873-4183-833d-d157f8fe109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926358041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.926358041
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2930513606
Short name T791
Test name
Test status
Simulation time 28553598992 ps
CPU time 67.55 seconds
Started May 14 03:06:36 PM PDT 24
Finished May 14 03:07:46 PM PDT 24
Peak memory 201672 kb
Host smart-282e67d9-c1ae-4618-9c00-569087745fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930513606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2930513606
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.397876725
Short name T725
Test name
Test status
Simulation time 3041402665 ps
CPU time 8.32 seconds
Started May 14 03:06:27 PM PDT 24
Finished May 14 03:06:37 PM PDT 24
Peak memory 201548 kb
Host smart-930ee128-5352-43b2-9b25-7aaa165f4818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397876725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.397876725
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2484011936
Short name T509
Test name
Test status
Simulation time 5700586739 ps
CPU time 13.11 seconds
Started May 14 03:06:20 PM PDT 24
Finished May 14 03:06:35 PM PDT 24
Peak memory 201760 kb
Host smart-5857b7d2-d40f-4440-8a31-815ab43dc229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484011936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2484011936
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3108716056
Short name T246
Test name
Test status
Simulation time 1278315001484 ps
CPU time 1808.16 seconds
Started May 14 03:06:34 PM PDT 24
Finished May 14 03:36:44 PM PDT 24
Peak memory 202104 kb
Host smart-92d71608-0699-425a-aea5-fe895acfff79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108716056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3108716056
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2281535191
Short name T213
Test name
Test status
Simulation time 747831822379 ps
CPU time 1427.16 seconds
Started May 14 03:06:34 PM PDT 24
Finished May 14 03:30:24 PM PDT 24
Peak memory 210480 kb
Host smart-7cc8d4be-f779-496e-86c6-e70461700af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281535191 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2281535191
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2664885037
Short name T490
Test name
Test status
Simulation time 436956903 ps
CPU time 1.65 seconds
Started May 14 03:06:48 PM PDT 24
Finished May 14 03:06:50 PM PDT 24
Peak memory 201468 kb
Host smart-1138f98e-bc40-489d-a800-dab14c0be839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664885037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2664885037
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3299587259
Short name T642
Test name
Test status
Simulation time 329512269168 ps
CPU time 218.92 seconds
Started May 14 03:06:36 PM PDT 24
Finished May 14 03:10:18 PM PDT 24
Peak memory 201852 kb
Host smart-d72cfde2-b84d-4d7d-8d85-1e50d84e5461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299587259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3299587259
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4226586804
Short name T129
Test name
Test status
Simulation time 326715902161 ps
CPU time 397.78 seconds
Started May 14 03:06:29 PM PDT 24
Finished May 14 03:13:09 PM PDT 24
Peak memory 202144 kb
Host smart-25a959a8-2818-4948-97bb-9ffa95a1c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226586804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4226586804
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2769424588
Short name T665
Test name
Test status
Simulation time 326933909337 ps
CPU time 313.63 seconds
Started May 14 03:06:36 PM PDT 24
Finished May 14 03:11:52 PM PDT 24
Peak memory 201640 kb
Host smart-d502b9d5-a236-45d9-8c25-a622a84adf38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769424588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2769424588
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2253586117
Short name T126
Test name
Test status
Simulation time 323073085990 ps
CPU time 738.84 seconds
Started May 14 03:06:28 PM PDT 24
Finished May 14 03:18:49 PM PDT 24
Peak memory 201828 kb
Host smart-d61c6893-254a-4559-8aa5-c684f4b44e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253586117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2253586117
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4066615111
Short name T797
Test name
Test status
Simulation time 502367400839 ps
CPU time 1317.21 seconds
Started May 14 03:06:34 PM PDT 24
Finished May 14 03:28:33 PM PDT 24
Peak memory 201780 kb
Host smart-e1a23975-8104-4763-9857-0ede5f44d03e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066615111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4066615111
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3530049749
Short name T284
Test name
Test status
Simulation time 185860001197 ps
CPU time 407.7 seconds
Started May 14 03:06:39 PM PDT 24
Finished May 14 03:13:28 PM PDT 24
Peak memory 201740 kb
Host smart-c0808198-6bff-4509-906f-5790d4d75413
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530049749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3530049749
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3283154383
Short name T441
Test name
Test status
Simulation time 46452635001 ps
CPU time 13.05 seconds
Started May 14 03:06:38 PM PDT 24
Finished May 14 03:06:53 PM PDT 24
Peak memory 201752 kb
Host smart-6a59f9ea-fb35-4792-b89a-9e1830acff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283154383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3283154383
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.664282127
Short name T176
Test name
Test status
Simulation time 5035872175 ps
CPU time 6.09 seconds
Started May 14 03:06:37 PM PDT 24
Finished May 14 03:06:45 PM PDT 24
Peak memory 201672 kb
Host smart-f7c70fa4-3b3f-4e9a-82b7-ea6573b994c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664282127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.664282127
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.371128225
Short name T351
Test name
Test status
Simulation time 5815562119 ps
CPU time 4.45 seconds
Started May 14 03:06:34 PM PDT 24
Finished May 14 03:06:40 PM PDT 24
Peak memory 201600 kb
Host smart-8a9114fb-e398-4bd3-8657-a1ea1fae048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371128225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.371128225
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.812475904
Short name T574
Test name
Test status
Simulation time 247556338137 ps
CPU time 903.58 seconds
Started May 14 03:06:48 PM PDT 24
Finished May 14 03:21:53 PM PDT 24
Peak memory 218424 kb
Host smart-5053a118-8221-46d8-b784-160d0b602bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812475904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
812475904
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3807839157
Short name T461
Test name
Test status
Simulation time 45196868745 ps
CPU time 44.6 seconds
Started May 14 03:06:38 PM PDT 24
Finished May 14 03:07:24 PM PDT 24
Peak memory 210308 kb
Host smart-35008566-6e91-4118-aaf0-1034fac310c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807839157 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3807839157
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.842286277
Short name T399
Test name
Test status
Simulation time 402779963 ps
CPU time 1.58 seconds
Started May 14 03:07:03 PM PDT 24
Finished May 14 03:07:06 PM PDT 24
Peak memory 201504 kb
Host smart-923e6b51-1107-47fe-aca6-b4142e2cf0e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842286277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.842286277
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4219823591
Short name T298
Test name
Test status
Simulation time 162065344035 ps
CPU time 94.94 seconds
Started May 14 03:06:55 PM PDT 24
Finished May 14 03:08:31 PM PDT 24
Peak memory 201732 kb
Host smart-fc6ab13a-6751-423e-be0e-5f2980081133
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219823591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4219823591
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.546508407
Short name T87
Test name
Test status
Simulation time 515736428689 ps
CPU time 1330.28 seconds
Started May 14 03:06:55 PM PDT 24
Finished May 14 03:29:07 PM PDT 24
Peak memory 201824 kb
Host smart-89cf175b-497d-4fad-a8b4-558df4188db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546508407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.546508407
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.450607597
Short name T653
Test name
Test status
Simulation time 160580886611 ps
CPU time 90.63 seconds
Started May 14 03:06:46 PM PDT 24
Finished May 14 03:08:18 PM PDT 24
Peak memory 201908 kb
Host smart-b5148eb3-d9bb-4fca-9268-90bed7c7956c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=450607597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.450607597
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3250083919
Short name T95
Test name
Test status
Simulation time 331671387751 ps
CPU time 192.31 seconds
Started May 14 03:06:45 PM PDT 24
Finished May 14 03:09:58 PM PDT 24
Peak memory 201772 kb
Host smart-c443eaa0-e806-4ef3-9eef-98c2fd090aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250083919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3250083919
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3240916554
Short name T413
Test name
Test status
Simulation time 328366379833 ps
CPU time 155.83 seconds
Started May 14 03:06:47 PM PDT 24
Finished May 14 03:09:23 PM PDT 24
Peak memory 201868 kb
Host smart-8c11a619-18e9-4bc6-b391-6086f98bfe5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240916554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3240916554
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3879015127
Short name T606
Test name
Test status
Simulation time 271402749799 ps
CPU time 630.15 seconds
Started May 14 03:06:46 PM PDT 24
Finished May 14 03:17:17 PM PDT 24
Peak memory 201892 kb
Host smart-9efa3b40-963b-4ff7-90b4-9cb0158b6f8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879015127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3879015127
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.611063306
Short name T626
Test name
Test status
Simulation time 401235835379 ps
CPU time 953.79 seconds
Started May 14 03:06:54 PM PDT 24
Finished May 14 03:22:49 PM PDT 24
Peak memory 201852 kb
Host smart-f4e2584c-42db-42cd-8942-84afebdbe069
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611063306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.611063306
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2683775165
Short name T708
Test name
Test status
Simulation time 75428263218 ps
CPU time 270.2 seconds
Started May 14 03:06:55 PM PDT 24
Finished May 14 03:11:27 PM PDT 24
Peak memory 202140 kb
Host smart-5e4137d0-1bd5-4d54-9300-e85597982892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683775165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2683775165
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3574799663
Short name T363
Test name
Test status
Simulation time 26962432456 ps
CPU time 60.97 seconds
Started May 14 03:06:55 PM PDT 24
Finished May 14 03:07:57 PM PDT 24
Peak memory 201632 kb
Host smart-16f26b7e-0846-4c81-a94d-3ffd638653fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574799663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3574799663
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.622503886
Short name T748
Test name
Test status
Simulation time 4419379019 ps
CPU time 6.12 seconds
Started May 14 03:06:53 PM PDT 24
Finished May 14 03:07:00 PM PDT 24
Peak memory 201700 kb
Host smart-c6cb9702-369c-475f-bf37-f193e76064fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622503886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.622503886
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2726332403
Short name T742
Test name
Test status
Simulation time 5957138481 ps
CPU time 15.89 seconds
Started May 14 03:06:46 PM PDT 24
Finished May 14 03:07:03 PM PDT 24
Peak memory 201888 kb
Host smart-143026e3-3131-4569-bb29-7187d7b6ac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726332403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2726332403
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.492717323
Short name T340
Test name
Test status
Simulation time 317136187433 ps
CPU time 731.98 seconds
Started May 14 03:06:55 PM PDT 24
Finished May 14 03:19:08 PM PDT 24
Peak memory 201824 kb
Host smart-14dea314-2fbc-4fde-b0c1-da045d275381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492717323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
492717323
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2811814496
Short name T677
Test name
Test status
Simulation time 52727569685 ps
CPU time 231.77 seconds
Started May 14 03:06:54 PM PDT 24
Finished May 14 03:10:47 PM PDT 24
Peak memory 210420 kb
Host smart-2c93e441-0204-4cae-9efb-cf36b2396553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811814496 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2811814496
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1815259026
Short name T589
Test name
Test status
Simulation time 289755513 ps
CPU time 0.96 seconds
Started May 14 03:07:08 PM PDT 24
Finished May 14 03:07:11 PM PDT 24
Peak memory 201424 kb
Host smart-ad9fd691-e963-4792-bd5e-c584cf86e602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815259026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1815259026
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2101140582
Short name T319
Test name
Test status
Simulation time 417027536407 ps
CPU time 941.27 seconds
Started May 14 03:07:02 PM PDT 24
Finished May 14 03:22:45 PM PDT 24
Peak memory 201872 kb
Host smart-e4c193e3-f8af-4562-ad25-a13c564bd47b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101140582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2101140582
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.433145726
Short name T83
Test name
Test status
Simulation time 165740325995 ps
CPU time 378.24 seconds
Started May 14 03:07:04 PM PDT 24
Finished May 14 03:13:24 PM PDT 24
Peak memory 201804 kb
Host smart-82e3153b-0c4c-4793-afb6-bd5c5938385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433145726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.433145726
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.510794588
Short name T595
Test name
Test status
Simulation time 331260257373 ps
CPU time 411.45 seconds
Started May 14 03:07:02 PM PDT 24
Finished May 14 03:13:55 PM PDT 24
Peak memory 201708 kb
Host smart-db1f1bfd-5d14-482c-bc99-5630260b2adc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=510794588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.510794588
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.672443884
Short name T169
Test name
Test status
Simulation time 162763983887 ps
CPU time 257.54 seconds
Started May 14 03:07:04 PM PDT 24
Finished May 14 03:11:23 PM PDT 24
Peak memory 201844 kb
Host smart-5f82b264-0c47-440e-bd2d-2bada0d1831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672443884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.672443884
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1896799066
Short name T465
Test name
Test status
Simulation time 328848763721 ps
CPU time 243.92 seconds
Started May 14 03:07:02 PM PDT 24
Finished May 14 03:11:08 PM PDT 24
Peak memory 201840 kb
Host smart-6279fb46-80a8-4929-9a2a-921d5f42b936
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896799066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1896799066
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2118749822
Short name T9
Test name
Test status
Simulation time 184657161338 ps
CPU time 46.22 seconds
Started May 14 03:07:02 PM PDT 24
Finished May 14 03:07:50 PM PDT 24
Peak memory 201916 kb
Host smart-649414ca-dcb7-44c3-943b-28ac5c0e3e70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118749822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2118749822
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1968406204
Short name T733
Test name
Test status
Simulation time 403552996585 ps
CPU time 255.37 seconds
Started May 14 03:07:02 PM PDT 24
Finished May 14 03:11:19 PM PDT 24
Peak memory 201764 kb
Host smart-cdcdee9a-9da5-4e18-b21f-077c175184cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968406204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1968406204
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1481081144
Short name T644
Test name
Test status
Simulation time 132772398556 ps
CPU time 430.69 seconds
Started May 14 03:07:01 PM PDT 24
Finished May 14 03:14:13 PM PDT 24
Peak memory 202140 kb
Host smart-381ae323-b345-48d4-9ac1-4fe507042e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481081144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1481081144
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2403008140
Short name T414
Test name
Test status
Simulation time 25699676749 ps
CPU time 24.14 seconds
Started May 14 03:07:01 PM PDT 24
Finished May 14 03:07:27 PM PDT 24
Peak memory 201616 kb
Host smart-77fd6ce5-1d68-41bb-ba1a-a25867864c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403008140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2403008140
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.895730450
Short name T177
Test name
Test status
Simulation time 5138237171 ps
CPU time 7.04 seconds
Started May 14 03:07:02 PM PDT 24
Finished May 14 03:07:11 PM PDT 24
Peak memory 201528 kb
Host smart-a992425d-9bf0-4e49-a65a-119240d9521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895730450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.895730450
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2158078539
Short name T772
Test name
Test status
Simulation time 5754594885 ps
CPU time 1.86 seconds
Started May 14 03:07:01 PM PDT 24
Finished May 14 03:07:04 PM PDT 24
Peak memory 201704 kb
Host smart-e103cf9e-94b0-4c0c-a11f-e0ef42ddc25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158078539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2158078539
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2705769917
Short name T583
Test name
Test status
Simulation time 173609665072 ps
CPU time 107.83 seconds
Started May 14 03:07:08 PM PDT 24
Finished May 14 03:08:57 PM PDT 24
Peak memory 201800 kb
Host smart-63aedfb7-6357-4306-98f6-47ac9673bb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705769917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2705769917
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2462010850
Short name T337
Test name
Test status
Simulation time 104429868587 ps
CPU time 114.57 seconds
Started May 14 03:07:01 PM PDT 24
Finished May 14 03:08:57 PM PDT 24
Peak memory 210196 kb
Host smart-b2791edf-069d-4382-aab4-7127888d24a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462010850 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2462010850
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3260842772
Short name T478
Test name
Test status
Simulation time 473868509 ps
CPU time 0.82 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:07:19 PM PDT 24
Peak memory 201432 kb
Host smart-39252b2b-a571-4e06-a670-b43607e8e031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260842772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3260842772
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3541798456
Short name T189
Test name
Test status
Simulation time 167791224928 ps
CPU time 124.47 seconds
Started May 14 03:07:08 PM PDT 24
Finished May 14 03:09:14 PM PDT 24
Peak memory 201828 kb
Host smart-35d279cd-4476-470e-bedd-8794695cb8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541798456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3541798456
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2430970672
Short name T550
Test name
Test status
Simulation time 489224921486 ps
CPU time 302.26 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:12:20 PM PDT 24
Peak memory 201844 kb
Host smart-18e04ce7-2b94-4d8d-9887-427ba14b28eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430970672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2430970672
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.939497620
Short name T197
Test name
Test status
Simulation time 338122872208 ps
CPU time 63.27 seconds
Started May 14 03:07:09 PM PDT 24
Finished May 14 03:08:13 PM PDT 24
Peak memory 201752 kb
Host smart-2c717f6e-6131-4e98-8726-1c013db6374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939497620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.939497620
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2755310557
Short name T442
Test name
Test status
Simulation time 497746052817 ps
CPU time 281.93 seconds
Started May 14 03:07:08 PM PDT 24
Finished May 14 03:11:51 PM PDT 24
Peak memory 201840 kb
Host smart-25e7efce-34f9-4196-b110-ca5d6d5a3689
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755310557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2755310557
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.759488362
Short name T446
Test name
Test status
Simulation time 594033354453 ps
CPU time 419.74 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:14:18 PM PDT 24
Peak memory 201824 kb
Host smart-2206b811-d5b0-4ec8-815c-0c523a2301da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759488362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.759488362
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2633756191
Short name T406
Test name
Test status
Simulation time 86074104424 ps
CPU time 471.23 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:15:10 PM PDT 24
Peak memory 202096 kb
Host smart-138542c1-f566-440b-b91c-98550da2f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633756191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2633756191
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2515689479
Short name T773
Test name
Test status
Simulation time 25556362402 ps
CPU time 61.56 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:08:20 PM PDT 24
Peak memory 201736 kb
Host smart-195f1fed-2738-4904-b5e9-a94fd70c1d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515689479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2515689479
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4219102426
Short name T460
Test name
Test status
Simulation time 4703936438 ps
CPU time 11.76 seconds
Started May 14 03:07:15 PM PDT 24
Finished May 14 03:07:29 PM PDT 24
Peak memory 201664 kb
Host smart-a54eb007-de52-46f6-8947-864b79ac1ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219102426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4219102426
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3032948709
Short name T469
Test name
Test status
Simulation time 5761164175 ps
CPU time 2.58 seconds
Started May 14 03:07:08 PM PDT 24
Finished May 14 03:07:12 PM PDT 24
Peak memory 201556 kb
Host smart-211db6c7-dfdf-4e3f-8d71-bb14c5b20da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032948709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3032948709
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3427322416
Short name T794
Test name
Test status
Simulation time 470976145808 ps
CPU time 1398.54 seconds
Started May 14 03:07:16 PM PDT 24
Finished May 14 03:30:37 PM PDT 24
Peak memory 218524 kb
Host smart-d79f312e-7041-4c4d-b13c-0228a70c4416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427322416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3427322416
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3503590734
Short name T26
Test name
Test status
Simulation time 72145083795 ps
CPU time 104.36 seconds
Started May 14 03:07:17 PM PDT 24
Finished May 14 03:09:04 PM PDT 24
Peak memory 210400 kb
Host smart-f50d275e-9d6a-4491-8ed6-d4feccbbca3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503590734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3503590734
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.240103271
Short name T58
Test name
Test status
Simulation time 319054216 ps
CPU time 0.79 seconds
Started May 14 02:58:15 PM PDT 24
Finished May 14 02:58:17 PM PDT 24
Peak memory 201580 kb
Host smart-0fed5076-2f92-44c3-8fbf-7f99d8cc085b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240103271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.240103271
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2448905425
Short name T328
Test name
Test status
Simulation time 329092640274 ps
CPU time 160.09 seconds
Started May 14 02:58:05 PM PDT 24
Finished May 14 03:00:46 PM PDT 24
Peak memory 201848 kb
Host smart-125ca233-2283-48ba-ad0a-6d561d96c38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448905425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2448905425
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.391656051
Short name T274
Test name
Test status
Simulation time 327286547288 ps
CPU time 742.56 seconds
Started May 14 02:57:56 PM PDT 24
Finished May 14 03:10:21 PM PDT 24
Peak memory 201784 kb
Host smart-aba32cb5-549f-47f4-92f0-1730f7f3f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391656051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.391656051
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4132211756
Short name T392
Test name
Test status
Simulation time 326191204883 ps
CPU time 743.92 seconds
Started May 14 02:57:56 PM PDT 24
Finished May 14 03:10:22 PM PDT 24
Peak memory 201816 kb
Host smart-d655262d-2f4a-420d-9f88-858308f38c71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132211756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4132211756
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.878068848
Short name T285
Test name
Test status
Simulation time 164689202736 ps
CPU time 364.45 seconds
Started May 14 02:57:54 PM PDT 24
Finished May 14 03:04:00 PM PDT 24
Peak memory 201900 kb
Host smart-b96b321d-ca54-4e51-9432-a9f588ee462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878068848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.878068848
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3316373649
Short name T152
Test name
Test status
Simulation time 485923874876 ps
CPU time 562.65 seconds
Started May 14 02:57:55 PM PDT 24
Finished May 14 03:07:20 PM PDT 24
Peak memory 201760 kb
Host smart-3b1adde0-158d-4083-b1a2-568853344350
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316373649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3316373649
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3051954162
Short name T259
Test name
Test status
Simulation time 529284004407 ps
CPU time 1209.73 seconds
Started May 14 02:57:56 PM PDT 24
Finished May 14 03:18:08 PM PDT 24
Peak memory 201844 kb
Host smart-f5b7c8e4-38d5-4e13-8426-c41b89066a24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051954162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3051954162
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2676289419
Short name T698
Test name
Test status
Simulation time 211835694059 ps
CPU time 157.57 seconds
Started May 14 02:57:56 PM PDT 24
Finished May 14 03:00:35 PM PDT 24
Peak memory 201880 kb
Host smart-43650eba-e2f1-4906-9da6-3a51965333cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676289419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2676289419
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.444812528
Short name T547
Test name
Test status
Simulation time 22902728887 ps
CPU time 13.14 seconds
Started May 14 02:58:14 PM PDT 24
Finished May 14 02:58:28 PM PDT 24
Peak memory 201652 kb
Host smart-d6e674e5-2ce2-44b0-bd9b-4946db002d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444812528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.444812528
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.821651845
Short name T476
Test name
Test status
Simulation time 3185978562 ps
CPU time 2.64 seconds
Started May 14 02:58:05 PM PDT 24
Finished May 14 02:58:08 PM PDT 24
Peak memory 201600 kb
Host smart-c4512dc3-cf23-40d5-abf7-2d5d7bbaeff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821651845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.821651845
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1327115647
Short name T73
Test name
Test status
Simulation time 7384912380 ps
CPU time 16.55 seconds
Started May 14 02:58:14 PM PDT 24
Finished May 14 02:58:31 PM PDT 24
Peak memory 217496 kb
Host smart-9b42c8bb-9f7d-4880-bb20-c6dbe43e7830
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327115647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1327115647
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1057251283
Short name T567
Test name
Test status
Simulation time 6071676025 ps
CPU time 4.49 seconds
Started May 14 02:57:56 PM PDT 24
Finished May 14 02:58:03 PM PDT 24
Peak memory 201708 kb
Host smart-815552b0-06d3-4aef-86d9-990ab2e96e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057251283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1057251283
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2502484193
Short name T234
Test name
Test status
Simulation time 576609938684 ps
CPU time 157.79 seconds
Started May 14 02:58:14 PM PDT 24
Finished May 14 03:00:53 PM PDT 24
Peak memory 210136 kb
Host smart-bac46ce8-d44c-4bf7-8405-99a59153ccd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502484193 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2502484193
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3271261980
Short name T360
Test name
Test status
Simulation time 454405945 ps
CPU time 1.15 seconds
Started May 14 03:07:31 PM PDT 24
Finished May 14 03:07:34 PM PDT 24
Peak memory 201468 kb
Host smart-dff1fb8a-eae1-420c-b492-9c30015dc288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271261980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3271261980
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1227074282
Short name T135
Test name
Test status
Simulation time 523517397213 ps
CPU time 320.25 seconds
Started May 14 03:07:25 PM PDT 24
Finished May 14 03:12:46 PM PDT 24
Peak memory 201876 kb
Host smart-2460349a-2cdc-42ce-aa3d-38f42fe9b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227074282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1227074282
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1381749086
Short name T310
Test name
Test status
Simulation time 323705497390 ps
CPU time 396.25 seconds
Started May 14 03:07:22 PM PDT 24
Finished May 14 03:13:59 PM PDT 24
Peak memory 201836 kb
Host smart-7d1539a7-82db-42f9-a49f-7d26c23d6e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381749086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1381749086
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2661796787
Short name T572
Test name
Test status
Simulation time 325961736200 ps
CPU time 134.79 seconds
Started May 14 03:07:24 PM PDT 24
Finished May 14 03:09:40 PM PDT 24
Peak memory 201796 kb
Host smart-4bd1c343-2fb7-4c8f-b19c-3eacf6a56bcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661796787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2661796787
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3646762490
Short name T7
Test name
Test status
Simulation time 328406955482 ps
CPU time 189.15 seconds
Started May 14 03:07:18 PM PDT 24
Finished May 14 03:10:29 PM PDT 24
Peak memory 201744 kb
Host smart-caf56c09-41da-4b1c-8862-bad15df967cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646762490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3646762490
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.555978789
Short name T528
Test name
Test status
Simulation time 333217715844 ps
CPU time 380.91 seconds
Started May 14 03:07:23 PM PDT 24
Finished May 14 03:13:45 PM PDT 24
Peak memory 201904 kb
Host smart-b80e38ff-a14d-4611-84c9-af14e878ab00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=555978789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.555978789
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.953555278
Short name T165
Test name
Test status
Simulation time 612743096948 ps
CPU time 1391.21 seconds
Started May 14 03:07:23 PM PDT 24
Finished May 14 03:30:35 PM PDT 24
Peak memory 201860 kb
Host smart-2df90a2a-3d6a-4c03-b49f-07a44272bde6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953555278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.953555278
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.218987151
Short name T531
Test name
Test status
Simulation time 201112873031 ps
CPU time 189.02 seconds
Started May 14 03:07:23 PM PDT 24
Finished May 14 03:10:34 PM PDT 24
Peak memory 201756 kb
Host smart-0d7f870f-bb65-4a5d-a729-4c42a19ce2fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218987151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.218987151
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.901587392
Short name T408
Test name
Test status
Simulation time 74079804021 ps
CPU time 336.01 seconds
Started May 14 03:07:23 PM PDT 24
Finished May 14 03:13:00 PM PDT 24
Peak memory 202136 kb
Host smart-cdd4d312-6afd-46e0-91dc-2da9d01643bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901587392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.901587392
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2626428883
Short name T675
Test name
Test status
Simulation time 34528070501 ps
CPU time 82.98 seconds
Started May 14 03:07:25 PM PDT 24
Finished May 14 03:08:49 PM PDT 24
Peak memory 201640 kb
Host smart-4dd9ff0e-b0d5-49b2-84eb-3a00343b421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626428883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2626428883
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4288595358
Short name T709
Test name
Test status
Simulation time 3865140877 ps
CPU time 10.05 seconds
Started May 14 03:07:23 PM PDT 24
Finished May 14 03:07:34 PM PDT 24
Peak memory 201612 kb
Host smart-526da5f6-23b4-43f4-b663-cf0710f070e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288595358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4288595358
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3367868121
Short name T633
Test name
Test status
Simulation time 5829625260 ps
CPU time 4.09 seconds
Started May 14 03:07:14 PM PDT 24
Finished May 14 03:07:20 PM PDT 24
Peak memory 201760 kb
Host smart-8161d8ca-aa91-4620-b1d2-84b2dc1699ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367868121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3367868121
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4175280516
Short name T13
Test name
Test status
Simulation time 101519786644 ps
CPU time 157.56 seconds
Started May 14 03:07:24 PM PDT 24
Finished May 14 03:10:03 PM PDT 24
Peak memory 211528 kb
Host smart-6dc6cdee-1c3d-444f-bb48-0aa2fa3a85e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175280516 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4175280516
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2202021321
Short name T732
Test name
Test status
Simulation time 295568039 ps
CPU time 1.26 seconds
Started May 14 03:07:48 PM PDT 24
Finished May 14 03:07:51 PM PDT 24
Peak memory 201508 kb
Host smart-47b24db3-852d-4355-8bde-b28e22802a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202021321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2202021321
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.5727274
Short name T620
Test name
Test status
Simulation time 365583839814 ps
CPU time 391.82 seconds
Started May 14 03:07:39 PM PDT 24
Finished May 14 03:14:12 PM PDT 24
Peak memory 201780 kb
Host smart-b420b9a6-431e-4008-94ae-9b554b5a03ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5727274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.5727274
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1378616459
Short name T291
Test name
Test status
Simulation time 163925199175 ps
CPU time 391.87 seconds
Started May 14 03:07:41 PM PDT 24
Finished May 14 03:14:14 PM PDT 24
Peak memory 201828 kb
Host smart-f3e2d18f-66a1-4962-ba84-09349d5a0e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378616459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1378616459
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4077671531
Short name T254
Test name
Test status
Simulation time 156565969767 ps
CPU time 90.76 seconds
Started May 14 03:07:32 PM PDT 24
Finished May 14 03:09:04 PM PDT 24
Peak memory 201952 kb
Host smart-1ab8b0b1-9427-40a8-87b8-c8984befa541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077671531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4077671531
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1210281910
Short name T707
Test name
Test status
Simulation time 492178239654 ps
CPU time 1193.46 seconds
Started May 14 03:07:39 PM PDT 24
Finished May 14 03:27:34 PM PDT 24
Peak memory 201868 kb
Host smart-9f196ed4-72b5-44a6-a61a-f9336d5fae21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210281910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1210281910
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1050171854
Short name T133
Test name
Test status
Simulation time 492901328733 ps
CPU time 1098.14 seconds
Started May 14 03:07:32 PM PDT 24
Finished May 14 03:25:52 PM PDT 24
Peak memory 201868 kb
Host smart-07d2889e-be46-4220-9ab1-bea5f74dd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050171854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1050171854
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3029163236
Short name T599
Test name
Test status
Simulation time 174239956314 ps
CPU time 56.52 seconds
Started May 14 03:07:30 PM PDT 24
Finished May 14 03:08:28 PM PDT 24
Peak memory 201712 kb
Host smart-6044e24f-d2d3-4b3b-be6b-3dbc74dc4c97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029163236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3029163236
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.709370542
Short name T1
Test name
Test status
Simulation time 207129076044 ps
CPU time 75.44 seconds
Started May 14 03:07:39 PM PDT 24
Finished May 14 03:08:56 PM PDT 24
Peak memory 201804 kb
Host smart-27a6f500-423f-44ab-af98-7e254bc0d3e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709370542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.709370542
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.947421770
Short name T209
Test name
Test status
Simulation time 76405753712 ps
CPU time 430.87 seconds
Started May 14 03:07:49 PM PDT 24
Finished May 14 03:15:01 PM PDT 24
Peak memory 202132 kb
Host smart-3d4c35f3-9ec0-4293-900b-d87089a95e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947421770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.947421770
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2386610693
Short name T391
Test name
Test status
Simulation time 36476638862 ps
CPU time 82.22 seconds
Started May 14 03:07:49 PM PDT 24
Finished May 14 03:09:12 PM PDT 24
Peak memory 201596 kb
Host smart-8bbbb71a-23ff-4881-9d24-9a983fc1b2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386610693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2386610693
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1312053467
Short name T78
Test name
Test status
Simulation time 4192959285 ps
CPU time 6.14 seconds
Started May 14 03:07:40 PM PDT 24
Finished May 14 03:07:47 PM PDT 24
Peak memory 201692 kb
Host smart-46809871-c55d-4061-828a-9706f733a4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312053467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1312053467
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2004527350
Short name T520
Test name
Test status
Simulation time 6037730193 ps
CPU time 4.33 seconds
Started May 14 03:07:30 PM PDT 24
Finished May 14 03:07:35 PM PDT 24
Peak memory 201612 kb
Host smart-78101108-6dfe-4c4c-a313-e30b32970e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004527350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2004527350
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2313147985
Short name T22
Test name
Test status
Simulation time 201182069450 ps
CPU time 238.27 seconds
Started May 14 03:07:47 PM PDT 24
Finished May 14 03:11:47 PM PDT 24
Peak memory 201708 kb
Host smart-29f384cb-b6e3-486d-85bd-8e4d93029051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313147985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2313147985
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1348520662
Short name T587
Test name
Test status
Simulation time 109709925823 ps
CPU time 66.16 seconds
Started May 14 03:07:47 PM PDT 24
Finished May 14 03:08:55 PM PDT 24
Peak memory 201872 kb
Host smart-2ac14239-2a0c-44a4-a78f-62216f5cb5d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348520662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1348520662
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1409303725
Short name T792
Test name
Test status
Simulation time 360151536 ps
CPU time 0.84 seconds
Started May 14 03:07:57 PM PDT 24
Finished May 14 03:08:00 PM PDT 24
Peak memory 201468 kb
Host smart-501fdff7-449d-43dc-9396-e06ce7d1102c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409303725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1409303725
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1224935705
Short name T727
Test name
Test status
Simulation time 164508133983 ps
CPU time 39.09 seconds
Started May 14 03:07:57 PM PDT 24
Finished May 14 03:08:38 PM PDT 24
Peak memory 201880 kb
Host smart-2a953b42-d7a3-4c4b-9727-553ae29fb339
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224935705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1224935705
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2796604019
Short name T480
Test name
Test status
Simulation time 558670704882 ps
CPU time 1039.64 seconds
Started May 14 03:07:56 PM PDT 24
Finished May 14 03:25:17 PM PDT 24
Peak memory 201800 kb
Host smart-a0777768-88e7-43bf-90da-866855866eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796604019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2796604019
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1642241860
Short name T185
Test name
Test status
Simulation time 328082543022 ps
CPU time 49.29 seconds
Started May 14 03:07:47 PM PDT 24
Finished May 14 03:08:37 PM PDT 24
Peak memory 201884 kb
Host smart-d3926044-d41c-4f6e-9bc8-50015884362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642241860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1642241860
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3480015999
Short name T229
Test name
Test status
Simulation time 484293313245 ps
CPU time 315.59 seconds
Started May 14 03:07:48 PM PDT 24
Finished May 14 03:13:04 PM PDT 24
Peak memory 201856 kb
Host smart-aee814fc-e4f2-4fea-b417-dd31e9621173
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480015999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3480015999
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3137997896
Short name T623
Test name
Test status
Simulation time 484069557038 ps
CPU time 305.05 seconds
Started May 14 03:07:48 PM PDT 24
Finished May 14 03:12:54 PM PDT 24
Peak memory 201852 kb
Host smart-ddc13bf8-fd6f-42a8-8d0d-289cebbd65f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137997896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3137997896
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3445486932
Short name T475
Test name
Test status
Simulation time 329904720666 ps
CPU time 780.91 seconds
Started May 14 03:07:48 PM PDT 24
Finished May 14 03:20:51 PM PDT 24
Peak memory 201740 kb
Host smart-e1707f5e-c59a-4cf8-8f09-baf372b38c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445486932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3445486932
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3676516719
Short name T793
Test name
Test status
Simulation time 351251313991 ps
CPU time 178.51 seconds
Started May 14 03:07:56 PM PDT 24
Finished May 14 03:10:56 PM PDT 24
Peak memory 201904 kb
Host smart-da674edd-dd28-4ab1-a281-fb36d4f92654
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676516719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3676516719
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2144158562
Short name T577
Test name
Test status
Simulation time 389231048940 ps
CPU time 897.7 seconds
Started May 14 03:08:01 PM PDT 24
Finished May 14 03:23:00 PM PDT 24
Peak memory 201828 kb
Host smart-fe41ea61-e299-4780-9f10-d080e4e5cedc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144158562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2144158562
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3799208426
Short name T755
Test name
Test status
Simulation time 82730623205 ps
CPU time 265.54 seconds
Started May 14 03:07:56 PM PDT 24
Finished May 14 03:12:23 PM PDT 24
Peak memory 202452 kb
Host smart-25a5b930-6108-44e9-b42e-40888c0d4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799208426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3799208426
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1787500015
Short name T717
Test name
Test status
Simulation time 30773484401 ps
CPU time 17.86 seconds
Started May 14 03:07:55 PM PDT 24
Finished May 14 03:08:14 PM PDT 24
Peak memory 201656 kb
Host smart-518bd5af-87a2-47c4-b5b7-64bcd29ccf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787500015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1787500015
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3389871953
Short name T449
Test name
Test status
Simulation time 4510695106 ps
CPU time 3.2 seconds
Started May 14 03:07:56 PM PDT 24
Finished May 14 03:08:01 PM PDT 24
Peak memory 201696 kb
Host smart-e825a59d-6d47-49a2-b804-86ddc7c91f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389871953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3389871953
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.497961565
Short name T150
Test name
Test status
Simulation time 6021155131 ps
CPU time 1.99 seconds
Started May 14 03:07:47 PM PDT 24
Finished May 14 03:07:51 PM PDT 24
Peak memory 201640 kb
Host smart-005a5c5a-043d-4e86-8055-6d406ffc7d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497961565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.497961565
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1287654102
Short name T724
Test name
Test status
Simulation time 169482580874 ps
CPU time 28.19 seconds
Started May 14 03:07:56 PM PDT 24
Finished May 14 03:08:26 PM PDT 24
Peak memory 201920 kb
Host smart-fd038784-738a-4e42-b575-2d6f64f4db4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287654102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1287654102
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3715784192
Short name T580
Test name
Test status
Simulation time 34246100137 ps
CPU time 57.53 seconds
Started May 14 03:07:55 PM PDT 24
Finished May 14 03:08:55 PM PDT 24
Peak memory 210044 kb
Host smart-249317d5-7d64-442a-b511-62851799efc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715784192 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3715784192
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3294875735
Short name T578
Test name
Test status
Simulation time 441998536 ps
CPU time 1.55 seconds
Started May 14 03:08:10 PM PDT 24
Finished May 14 03:08:12 PM PDT 24
Peak memory 201480 kb
Host smart-7b62e19c-539f-4890-b1fd-fc2adda62962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294875735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3294875735
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.296715238
Short name T671
Test name
Test status
Simulation time 155027710235 ps
CPU time 163.09 seconds
Started May 14 03:08:03 PM PDT 24
Finished May 14 03:10:47 PM PDT 24
Peak memory 201872 kb
Host smart-ab283e6e-2668-4b79-9e72-bbe6195d7042
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296715238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.296715238
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.964179390
Short name T674
Test name
Test status
Simulation time 209280487038 ps
CPU time 132.18 seconds
Started May 14 03:08:03 PM PDT 24
Finished May 14 03:10:16 PM PDT 24
Peak memory 201932 kb
Host smart-c7812481-6fbb-4664-b9c5-4303f1b95646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964179390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.964179390
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.4049945877
Short name T89
Test name
Test status
Simulation time 484181552756 ps
CPU time 1221.26 seconds
Started May 14 03:08:03 PM PDT 24
Finished May 14 03:28:25 PM PDT 24
Peak memory 201796 kb
Host smart-117824c1-f860-40e4-99fd-0731244e3f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049945877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4049945877
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1178287887
Short name T507
Test name
Test status
Simulation time 164163771802 ps
CPU time 99.85 seconds
Started May 14 03:08:03 PM PDT 24
Finished May 14 03:09:44 PM PDT 24
Peak memory 201728 kb
Host smart-445a6c07-4a7f-4e72-bb16-0873e2310de5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178287887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1178287887
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1995057398
Short name T746
Test name
Test status
Simulation time 492153680940 ps
CPU time 305.03 seconds
Started May 14 03:08:07 PM PDT 24
Finished May 14 03:13:13 PM PDT 24
Peak memory 201860 kb
Host smart-476f9f08-93ab-47af-82eb-d25432b2f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995057398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1995057398
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1301695075
Short name T545
Test name
Test status
Simulation time 485257322944 ps
CPU time 969.82 seconds
Started May 14 03:08:07 PM PDT 24
Finished May 14 03:24:18 PM PDT 24
Peak memory 201792 kb
Host smart-0ff37204-2b7f-4a82-af3c-0cd737704d06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301695075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1301695075
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.922247083
Short name T76
Test name
Test status
Simulation time 407690485673 ps
CPU time 912.46 seconds
Started May 14 03:08:03 PM PDT 24
Finished May 14 03:23:16 PM PDT 24
Peak memory 201936 kb
Host smart-29758564-12bf-46c9-afca-4c034253d9c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922247083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.922247083
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3801765685
Short name T767
Test name
Test status
Simulation time 598889120383 ps
CPU time 687.37 seconds
Started May 14 03:08:02 PM PDT 24
Finished May 14 03:19:30 PM PDT 24
Peak memory 201860 kb
Host smart-b6174da7-3676-41f8-abe3-631819b53596
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801765685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3801765685
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.107376741
Short name T625
Test name
Test status
Simulation time 81557001937 ps
CPU time 245.72 seconds
Started May 14 03:08:14 PM PDT 24
Finished May 14 03:12:20 PM PDT 24
Peak memory 202148 kb
Host smart-9a402052-2914-4f1c-a823-9b282cc902b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107376741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.107376741
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4161487395
Short name T726
Test name
Test status
Simulation time 27210434105 ps
CPU time 61.29 seconds
Started May 14 03:08:10 PM PDT 24
Finished May 14 03:09:12 PM PDT 24
Peak memory 201592 kb
Host smart-1ee236f8-a80a-486c-a907-996b077e2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161487395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4161487395
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1568316725
Short name T517
Test name
Test status
Simulation time 2958272703 ps
CPU time 1.74 seconds
Started May 14 03:08:04 PM PDT 24
Finished May 14 03:08:07 PM PDT 24
Peak memory 201524 kb
Host smart-d2bfe4f2-0fba-4a01-a68e-f8c937d99f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568316725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1568316725
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1530375493
Short name T492
Test name
Test status
Simulation time 5801767215 ps
CPU time 7.75 seconds
Started May 14 03:07:56 PM PDT 24
Finished May 14 03:08:05 PM PDT 24
Peak memory 201760 kb
Host smart-dbf4832c-4fe9-469a-abfb-0144779658a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530375493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1530375493
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1605763206
Short name T145
Test name
Test status
Simulation time 172004366295 ps
CPU time 108.43 seconds
Started May 14 03:08:12 PM PDT 24
Finished May 14 03:10:02 PM PDT 24
Peak memory 201816 kb
Host smart-68c2ee46-c536-4bed-ac29-8298b0d16872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605763206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1605763206
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1672718552
Short name T193
Test name
Test status
Simulation time 484685227 ps
CPU time 1.82 seconds
Started May 14 03:08:26 PM PDT 24
Finished May 14 03:08:28 PM PDT 24
Peak memory 201488 kb
Host smart-a8a58405-7399-4e35-b911-f7487888cd5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672718552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1672718552
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3712627572
Short name T200
Test name
Test status
Simulation time 505729508374 ps
CPU time 314.66 seconds
Started May 14 03:08:25 PM PDT 24
Finished May 14 03:13:40 PM PDT 24
Peak memory 201728 kb
Host smart-40b2a2e8-35b1-4c28-b240-e8b5321badc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712627572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3712627572
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2980426115
Short name T286
Test name
Test status
Simulation time 159343573775 ps
CPU time 275.22 seconds
Started May 14 03:08:20 PM PDT 24
Finished May 14 03:12:56 PM PDT 24
Peak memory 201904 kb
Host smart-2a123aeb-05d5-43f0-bb21-53a407451d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980426115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2980426115
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2762929133
Short name T438
Test name
Test status
Simulation time 159839945524 ps
CPU time 184.94 seconds
Started May 14 03:08:27 PM PDT 24
Finished May 14 03:11:33 PM PDT 24
Peak memory 201804 kb
Host smart-17a4a06b-00df-45e8-bab6-3fc24ad5062c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762929133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2762929133
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1620003234
Short name T270
Test name
Test status
Simulation time 320799963567 ps
CPU time 689.41 seconds
Started May 14 03:08:20 PM PDT 24
Finished May 14 03:19:51 PM PDT 24
Peak memory 201816 kb
Host smart-6b4f3ffa-6f58-478d-b61d-da2f1296d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620003234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1620003234
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1570972835
Short name T663
Test name
Test status
Simulation time 489023830060 ps
CPU time 716.53 seconds
Started May 14 03:08:20 PM PDT 24
Finished May 14 03:20:18 PM PDT 24
Peak memory 201796 kb
Host smart-3d317eef-d7b2-4eba-a566-2100eb43615b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570972835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1570972835
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3305444456
Short name T614
Test name
Test status
Simulation time 180337164053 ps
CPU time 114.5 seconds
Started May 14 03:08:24 PM PDT 24
Finished May 14 03:10:20 PM PDT 24
Peak memory 201920 kb
Host smart-1db94541-f76d-4ee0-bf3e-b8c9bac5290d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305444456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3305444456
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1389140974
Short name T450
Test name
Test status
Simulation time 609043840955 ps
CPU time 353.02 seconds
Started May 14 03:08:25 PM PDT 24
Finished May 14 03:14:19 PM PDT 24
Peak memory 201900 kb
Host smart-c534345a-8353-415d-9118-12bde3889309
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389140974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1389140974
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2119138882
Short name T153
Test name
Test status
Simulation time 124993900477 ps
CPU time 613.57 seconds
Started May 14 03:08:27 PM PDT 24
Finished May 14 03:18:42 PM PDT 24
Peak memory 202112 kb
Host smart-7c0c5967-5ec1-4f88-b78a-37dd34579b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119138882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2119138882
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.118322416
Short name T585
Test name
Test status
Simulation time 41633320198 ps
CPU time 97.77 seconds
Started May 14 03:08:26 PM PDT 24
Finished May 14 03:10:05 PM PDT 24
Peak memory 201620 kb
Host smart-591da11f-98ee-454a-9f16-43a49011e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118322416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.118322416
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2015398333
Short name T546
Test name
Test status
Simulation time 4612842317 ps
CPU time 11.88 seconds
Started May 14 03:08:26 PM PDT 24
Finished May 14 03:08:39 PM PDT 24
Peak memory 201660 kb
Host smart-2136b193-a3f4-4b7c-9e38-4408e351f5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015398333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2015398333
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1742816683
Short name T403
Test name
Test status
Simulation time 5832192479 ps
CPU time 2.21 seconds
Started May 14 03:08:12 PM PDT 24
Finished May 14 03:08:16 PM PDT 24
Peak memory 201676 kb
Host smart-cda4b8b4-d554-43ae-b188-b1971ab2d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742816683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1742816683
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.955990938
Short name T673
Test name
Test status
Simulation time 245389213024 ps
CPU time 774.53 seconds
Started May 14 03:08:26 PM PDT 24
Finished May 14 03:21:21 PM PDT 24
Peak memory 202064 kb
Host smart-58ab13b1-b5e9-4bed-b22c-053b5e13fa43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955990938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
955990938
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1717640689
Short name T472
Test name
Test status
Simulation time 36713767552 ps
CPU time 85.52 seconds
Started May 14 03:08:27 PM PDT 24
Finished May 14 03:09:54 PM PDT 24
Peak memory 210384 kb
Host smart-64ef02e1-e446-48d6-add5-a0ebc8e1d39a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717640689 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1717640689
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1491678979
Short name T175
Test name
Test status
Simulation time 290829718 ps
CPU time 1.22 seconds
Started May 14 03:08:46 PM PDT 24
Finished May 14 03:08:48 PM PDT 24
Peak memory 201520 kb
Host smart-55ee998e-86a0-41e4-ac00-a435c698a67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491678979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1491678979
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.269082586
Short name T179
Test name
Test status
Simulation time 575900140979 ps
CPU time 229.36 seconds
Started May 14 03:08:40 PM PDT 24
Finished May 14 03:12:31 PM PDT 24
Peak memory 201784 kb
Host smart-10dd088e-9353-4b1e-ad3b-ace33cce9469
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269082586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.269082586
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3787094320
Short name T303
Test name
Test status
Simulation time 166907597517 ps
CPU time 415 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:15:38 PM PDT 24
Peak memory 201896 kb
Host smart-c740c055-f600-4cf5-9a9a-e7f847ba667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787094320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3787094320
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.867400316
Short name T758
Test name
Test status
Simulation time 162658740678 ps
CPU time 98.99 seconds
Started May 14 03:08:36 PM PDT 24
Finished May 14 03:10:16 PM PDT 24
Peak memory 201808 kb
Host smart-f5e55917-6ab1-4fb9-a667-e833dcf21852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867400316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.867400316
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.993359683
Short name T628
Test name
Test status
Simulation time 504159372696 ps
CPU time 340.03 seconds
Started May 14 03:08:33 PM PDT 24
Finished May 14 03:14:14 PM PDT 24
Peak memory 201748 kb
Host smart-677f816c-478b-4d10-a836-ba9d946aebeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=993359683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.993359683
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.536194818
Short name T551
Test name
Test status
Simulation time 164377263173 ps
CPU time 376.53 seconds
Started May 14 03:08:34 PM PDT 24
Finished May 14 03:14:53 PM PDT 24
Peak memory 201772 kb
Host smart-0340960d-0f8a-4809-8896-846862a0b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536194818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.536194818
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1905834449
Short name T74
Test name
Test status
Simulation time 165663603315 ps
CPU time 404.15 seconds
Started May 14 03:08:40 PM PDT 24
Finished May 14 03:15:26 PM PDT 24
Peak memory 201844 kb
Host smart-43e9ada5-aeaa-4660-9103-85a404c34cf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905834449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1905834449
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3715791036
Short name T433
Test name
Test status
Simulation time 396281362469 ps
CPU time 975.78 seconds
Started May 14 03:08:40 PM PDT 24
Finished May 14 03:24:58 PM PDT 24
Peak memory 201728 kb
Host smart-24f4eb9e-06c6-4040-aada-112961702906
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715791036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3715791036
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2444117016
Short name T759
Test name
Test status
Simulation time 111051559319 ps
CPU time 567.69 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:18:11 PM PDT 24
Peak memory 202136 kb
Host smart-0d54184a-ea18-496f-85f3-f29da8754112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444117016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2444117016
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1237049998
Short name T571
Test name
Test status
Simulation time 23443584314 ps
CPU time 56.81 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:09:40 PM PDT 24
Peak memory 201588 kb
Host smart-f26ee500-41bf-45ac-a9af-f9cddd21e58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237049998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1237049998
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1916009215
Short name T647
Test name
Test status
Simulation time 3935081034 ps
CPU time 2.76 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:08:46 PM PDT 24
Peak memory 201492 kb
Host smart-608c1eab-c1aa-42b4-8890-282c8f3380bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916009215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1916009215
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3689775832
Short name T418
Test name
Test status
Simulation time 5827654763 ps
CPU time 4.24 seconds
Started May 14 03:08:36 PM PDT 24
Finished May 14 03:08:41 PM PDT 24
Peak memory 201556 kb
Host smart-fb5d5047-972d-4a70-93e1-61cb4d21262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689775832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3689775832
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3222552739
Short name T710
Test name
Test status
Simulation time 204123245883 ps
CPU time 142.62 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:11:06 PM PDT 24
Peak memory 201796 kb
Host smart-1c02a1c2-6305-4855-a00d-5f79cde0a603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222552739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3222552739
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.411494726
Short name T239
Test name
Test status
Simulation time 542757631794 ps
CPU time 699.83 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:20:23 PM PDT 24
Peak memory 210496 kb
Host smart-e01c098d-5b34-416c-b2c8-5a33a29a0b60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411494726 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.411494726
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2863710594
Short name T715
Test name
Test status
Simulation time 440016897 ps
CPU time 1.18 seconds
Started May 14 03:08:57 PM PDT 24
Finished May 14 03:08:59 PM PDT 24
Peak memory 201632 kb
Host smart-be57d8b8-ff12-43d0-af6d-02d72c1f3d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863710594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2863710594
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1413267467
Short name T485
Test name
Test status
Simulation time 592425531149 ps
CPU time 1460.1 seconds
Started May 14 03:08:49 PM PDT 24
Finished May 14 03:33:10 PM PDT 24
Peak memory 201764 kb
Host smart-3779179b-3da0-46c2-9651-b91f59673733
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413267467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1413267467
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4203596596
Short name T711
Test name
Test status
Simulation time 161177678466 ps
CPU time 34.24 seconds
Started May 14 03:08:50 PM PDT 24
Finished May 14 03:09:25 PM PDT 24
Peak memory 201812 kb
Host smart-5ac8affc-6b4f-4124-b24f-15bd130d0a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203596596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4203596596
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1406904833
Short name T502
Test name
Test status
Simulation time 330788614386 ps
CPU time 766.02 seconds
Started May 14 03:08:50 PM PDT 24
Finished May 14 03:21:37 PM PDT 24
Peak memory 201780 kb
Host smart-0f2a5a2e-1d83-4700-b66f-16d3578e08c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406904833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1406904833
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3253125875
Short name T781
Test name
Test status
Simulation time 496043571637 ps
CPU time 98.5 seconds
Started May 14 03:08:43 PM PDT 24
Finished May 14 03:10:23 PM PDT 24
Peak memory 201820 kb
Host smart-3251da16-1cf7-4275-928c-363091ddaf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253125875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3253125875
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1912834092
Short name T466
Test name
Test status
Simulation time 330440012284 ps
CPU time 313.44 seconds
Started May 14 03:08:50 PM PDT 24
Finished May 14 03:14:04 PM PDT 24
Peak memory 201732 kb
Host smart-b521b3a3-f2aa-4efc-a4cc-d26cb199934a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912834092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1912834092
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4261165474
Short name T596
Test name
Test status
Simulation time 193740826241 ps
CPU time 246.74 seconds
Started May 14 03:08:50 PM PDT 24
Finished May 14 03:12:58 PM PDT 24
Peak memory 201884 kb
Host smart-66857c84-06c7-4e7a-b58b-0c032016851d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261165474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4261165474
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1679867152
Short name T468
Test name
Test status
Simulation time 206075586442 ps
CPU time 473.81 seconds
Started May 14 03:08:50 PM PDT 24
Finished May 14 03:16:44 PM PDT 24
Peak memory 201784 kb
Host smart-0fcc76d5-7d1b-4c27-9ff1-a425573b1df2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679867152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1679867152
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1648461342
Short name T542
Test name
Test status
Simulation time 102110220951 ps
CPU time 418.42 seconds
Started May 14 03:08:57 PM PDT 24
Finished May 14 03:15:56 PM PDT 24
Peak memory 202060 kb
Host smart-eab9ece3-78a7-41a6-b2ce-2ca64ab75d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648461342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1648461342
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2417991544
Short name T576
Test name
Test status
Simulation time 39492818835 ps
CPU time 21.93 seconds
Started May 14 03:08:51 PM PDT 24
Finished May 14 03:09:14 PM PDT 24
Peak memory 201648 kb
Host smart-6c7a4277-47e5-4de9-88b6-99ba41dfaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417991544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2417991544
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2118330665
Short name T497
Test name
Test status
Simulation time 3332816926 ps
CPU time 8.63 seconds
Started May 14 03:08:49 PM PDT 24
Finished May 14 03:08:59 PM PDT 24
Peak memory 201556 kb
Host smart-9f55d7f1-a43f-49fe-9ea4-edb92bffe419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118330665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2118330665
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3162640412
Short name T605
Test name
Test status
Simulation time 6012088412 ps
CPU time 3.13 seconds
Started May 14 03:08:41 PM PDT 24
Finished May 14 03:08:46 PM PDT 24
Peak memory 201612 kb
Host smart-d3809ad8-689b-4723-b1a7-3c78227ec9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162640412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3162640412
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4003555052
Short name T690
Test name
Test status
Simulation time 262885128154 ps
CPU time 211.58 seconds
Started May 14 03:08:58 PM PDT 24
Finished May 14 03:12:31 PM PDT 24
Peak memory 218196 kb
Host smart-cf2efacf-8f86-4509-acdc-c7d868d58a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003555052 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4003555052
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.358826260
Short name T358
Test name
Test status
Simulation time 451628420 ps
CPU time 0.87 seconds
Started May 14 03:09:15 PM PDT 24
Finished May 14 03:09:17 PM PDT 24
Peak memory 201536 kb
Host smart-3cc34d42-9b53-4610-afb4-a656e07b0298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358826260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.358826260
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3543550848
Short name T279
Test name
Test status
Simulation time 354967433294 ps
CPU time 238.06 seconds
Started May 14 03:09:07 PM PDT 24
Finished May 14 03:13:06 PM PDT 24
Peak memory 201868 kb
Host smart-7623b1eb-7a7a-4b5b-bb8c-522b3f2b994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543550848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3543550848
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.607593568
Short name T288
Test name
Test status
Simulation time 321335842984 ps
CPU time 692.3 seconds
Started May 14 03:09:10 PM PDT 24
Finished May 14 03:20:43 PM PDT 24
Peak memory 201804 kb
Host smart-69f6e42c-bb61-44c2-82e8-fd635073b65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607593568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.607593568
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1863288125
Short name T416
Test name
Test status
Simulation time 328046660231 ps
CPU time 63.36 seconds
Started May 14 03:09:07 PM PDT 24
Finished May 14 03:10:11 PM PDT 24
Peak memory 201900 kb
Host smart-59c28b57-a077-423d-b7ce-b30465b4e9f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863288125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1863288125
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3698984914
Short name T170
Test name
Test status
Simulation time 496645654139 ps
CPU time 115.73 seconds
Started May 14 03:08:58 PM PDT 24
Finished May 14 03:10:55 PM PDT 24
Peak memory 201712 kb
Host smart-0d01c6a2-97f2-4021-ad7f-3276a92fcb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698984914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3698984914
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1915781424
Short name T454
Test name
Test status
Simulation time 325547772514 ps
CPU time 750.51 seconds
Started May 14 03:08:58 PM PDT 24
Finished May 14 03:21:30 PM PDT 24
Peak memory 201916 kb
Host smart-f752cfa9-5b55-4f9e-923f-9ae6c3a8cfa4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915781424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1915781424
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.932680575
Short name T331
Test name
Test status
Simulation time 356433258587 ps
CPU time 875.32 seconds
Started May 14 03:09:06 PM PDT 24
Finished May 14 03:23:42 PM PDT 24
Peak memory 201848 kb
Host smart-11bc7cf1-fdbd-4229-bb8c-3fc878d38564
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932680575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.932680575
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1745285417
Short name T518
Test name
Test status
Simulation time 607367538390 ps
CPU time 1192 seconds
Started May 14 03:09:07 PM PDT 24
Finished May 14 03:29:00 PM PDT 24
Peak memory 201788 kb
Host smart-1ec49a73-94dc-45d3-ba58-ba15c2116f09
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745285417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1745285417
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.963181701
Short name T208
Test name
Test status
Simulation time 129050196476 ps
CPU time 656.67 seconds
Started May 14 03:09:08 PM PDT 24
Finished May 14 03:20:06 PM PDT 24
Peak memory 202164 kb
Host smart-077a9306-74ce-4228-bf78-2557076ac090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963181701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.963181701
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3653325067
Short name T378
Test name
Test status
Simulation time 25518586248 ps
CPU time 52.7 seconds
Started May 14 03:09:09 PM PDT 24
Finished May 14 03:10:03 PM PDT 24
Peak memory 201552 kb
Host smart-005a6e5c-0f77-4d78-b5f2-6892538841a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653325067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3653325067
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3678277362
Short name T471
Test name
Test status
Simulation time 3700499282 ps
CPU time 2.32 seconds
Started May 14 03:09:07 PM PDT 24
Finished May 14 03:09:10 PM PDT 24
Peak memory 201524 kb
Host smart-6cb0f331-6832-4f03-8dbc-7a14a302e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678277362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3678277362
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3986514483
Short name T463
Test name
Test status
Simulation time 5872158604 ps
CPU time 13.84 seconds
Started May 14 03:08:58 PM PDT 24
Finished May 14 03:09:14 PM PDT 24
Peak memory 201760 kb
Host smart-6e42c4a3-24cc-428c-bfe4-ad82582dea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986514483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3986514483
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1123582987
Short name T231
Test name
Test status
Simulation time 345436183204 ps
CPU time 138.46 seconds
Started May 14 03:09:15 PM PDT 24
Finished May 14 03:11:35 PM PDT 24
Peak memory 201936 kb
Host smart-c08dd739-cc7c-4b12-8a08-5e49a65bc6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123582987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1123582987
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1498988853
Short name T290
Test name
Test status
Simulation time 170409767029 ps
CPU time 365.58 seconds
Started May 14 03:09:05 PM PDT 24
Finished May 14 03:15:12 PM PDT 24
Peak memory 210364 kb
Host smart-a594b227-7c9d-4066-b688-c0299a8b21b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498988853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1498988853
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4229282612
Short name T536
Test name
Test status
Simulation time 446225939 ps
CPU time 1.58 seconds
Started May 14 03:09:31 PM PDT 24
Finished May 14 03:09:34 PM PDT 24
Peak memory 201540 kb
Host smart-6cffbb5a-21d2-4a87-b70d-3cc83b2725fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229282612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4229282612
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2948035899
Short name T250
Test name
Test status
Simulation time 325914260876 ps
CPU time 467.17 seconds
Started May 14 03:09:23 PM PDT 24
Finished May 14 03:17:11 PM PDT 24
Peak memory 201796 kb
Host smart-72e1d43c-57a7-4af9-8f05-31ff2d6e21a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948035899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2948035899
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.769151086
Short name T249
Test name
Test status
Simulation time 490774607847 ps
CPU time 319.67 seconds
Started May 14 03:09:15 PM PDT 24
Finished May 14 03:14:36 PM PDT 24
Peak memory 201792 kb
Host smart-260b9f87-fac3-4b19-b394-de1eef5421aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769151086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.769151086
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1272483137
Short name T629
Test name
Test status
Simulation time 486931560237 ps
CPU time 1044.32 seconds
Started May 14 03:09:13 PM PDT 24
Finished May 14 03:26:39 PM PDT 24
Peak memory 201804 kb
Host smart-5fa4cba9-5c31-4347-bcef-a05fe191e337
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272483137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1272483137
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3166247100
Short name T149
Test name
Test status
Simulation time 329389910783 ps
CPU time 204.57 seconds
Started May 14 03:09:15 PM PDT 24
Finished May 14 03:12:41 PM PDT 24
Peak memory 201804 kb
Host smart-0c414aa0-7f5b-43fb-962e-529e0a2a32df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166247100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3166247100
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2292134649
Short name T552
Test name
Test status
Simulation time 328444202763 ps
CPU time 787.04 seconds
Started May 14 03:09:13 PM PDT 24
Finished May 14 03:22:22 PM PDT 24
Peak memory 201788 kb
Host smart-ca5cdbe5-4fb4-4018-8224-542a4d4becde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292134649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2292134649
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.99557948
Short name T84
Test name
Test status
Simulation time 379398472142 ps
CPU time 226.48 seconds
Started May 14 03:09:15 PM PDT 24
Finished May 14 03:13:03 PM PDT 24
Peak memory 201860 kb
Host smart-9c15bed8-2868-46e0-9731-492b194b82dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99557948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_w
akeup.99557948
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2350885384
Short name T521
Test name
Test status
Simulation time 392258401815 ps
CPU time 66.87 seconds
Started May 14 03:09:16 PM PDT 24
Finished May 14 03:10:24 PM PDT 24
Peak memory 201860 kb
Host smart-9ae56b00-02f5-45b9-99d1-0d265ef782ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350885384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2350885384
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3050742284
Short name T734
Test name
Test status
Simulation time 78761889794 ps
CPU time 259.59 seconds
Started May 14 03:09:22 PM PDT 24
Finished May 14 03:13:42 PM PDT 24
Peak memory 202100 kb
Host smart-9115601b-88d7-4361-91b3-07c453b994bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050742284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3050742284
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3973767316
Short name T400
Test name
Test status
Simulation time 22827144674 ps
CPU time 14.61 seconds
Started May 14 03:09:23 PM PDT 24
Finished May 14 03:09:39 PM PDT 24
Peak memory 201772 kb
Host smart-86794fdb-afee-4f6e-930f-6679b71876b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973767316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3973767316
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1789335071
Short name T780
Test name
Test status
Simulation time 5716981742 ps
CPU time 5.63 seconds
Started May 14 03:09:24 PM PDT 24
Finished May 14 03:09:30 PM PDT 24
Peak memory 201616 kb
Host smart-b4f846c3-8e32-41eb-9be7-2514e615a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789335071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1789335071
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1605537560
Short name T99
Test name
Test status
Simulation time 6089440306 ps
CPU time 4.6 seconds
Started May 14 03:09:15 PM PDT 24
Finished May 14 03:09:21 PM PDT 24
Peak memory 201624 kb
Host smart-11ad8382-10f4-447f-af47-9a83d3d5dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605537560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1605537560
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3190336855
Short name T566
Test name
Test status
Simulation time 200389403832 ps
CPU time 122.08 seconds
Started May 14 03:09:23 PM PDT 24
Finished May 14 03:11:26 PM PDT 24
Peak memory 201724 kb
Host smart-29e2f59c-cb2b-4a25-acf5-23f4e1c9e746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190336855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3190336855
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1696398840
Short name T501
Test name
Test status
Simulation time 22730130493 ps
CPU time 113.05 seconds
Started May 14 03:09:24 PM PDT 24
Finished May 14 03:11:18 PM PDT 24
Peak memory 210476 kb
Host smart-e8057a24-0162-4b69-a58a-09e752f4952e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696398840 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1696398840
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1288560029
Short name T510
Test name
Test status
Simulation time 338479315 ps
CPU time 0.8 seconds
Started May 14 03:09:42 PM PDT 24
Finished May 14 03:09:45 PM PDT 24
Peak memory 201512 kb
Host smart-e3e38c17-fac2-4ed0-a42c-7899537a369d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288560029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1288560029
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2071286650
Short name T747
Test name
Test status
Simulation time 384113724405 ps
CPU time 368.34 seconds
Started May 14 03:09:31 PM PDT 24
Finished May 14 03:15:41 PM PDT 24
Peak memory 201936 kb
Host smart-b05b1e71-dcba-4b1b-8892-3aabae556101
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071286650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2071286650
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2452102508
Short name T137
Test name
Test status
Simulation time 357043413169 ps
CPU time 884.26 seconds
Started May 14 03:09:42 PM PDT 24
Finished May 14 03:24:28 PM PDT 24
Peak memory 201804 kb
Host smart-6545b29d-43fb-4635-9f6a-ac3737121e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452102508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2452102508
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3132376344
Short name T784
Test name
Test status
Simulation time 161585322422 ps
CPU time 71.98 seconds
Started May 14 03:09:31 PM PDT 24
Finished May 14 03:10:44 PM PDT 24
Peak memory 201796 kb
Host smart-55d06127-612d-4ce9-b63a-5085d9b51e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132376344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3132376344
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2734854545
Short name T409
Test name
Test status
Simulation time 484797531803 ps
CPU time 434.44 seconds
Started May 14 03:09:30 PM PDT 24
Finished May 14 03:16:45 PM PDT 24
Peak memory 201792 kb
Host smart-c9c47864-4273-4f1d-834c-3fc99a657cef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734854545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2734854545
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1603369419
Short name T198
Test name
Test status
Simulation time 496753926900 ps
CPU time 277.16 seconds
Started May 14 03:09:33 PM PDT 24
Finished May 14 03:14:11 PM PDT 24
Peak memory 201708 kb
Host smart-95fa680a-03db-4254-b0bc-249794c08594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603369419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1603369419
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1848225486
Short name T667
Test name
Test status
Simulation time 335049597954 ps
CPU time 411.57 seconds
Started May 14 03:09:31 PM PDT 24
Finished May 14 03:16:24 PM PDT 24
Peak memory 201784 kb
Host smart-95ee3412-d61b-4885-9ab2-fb920df45d15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848225486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1848225486
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1272873265
Short name T431
Test name
Test status
Simulation time 186381113868 ps
CPU time 122.74 seconds
Started May 14 03:09:30 PM PDT 24
Finished May 14 03:11:33 PM PDT 24
Peak memory 201828 kb
Host smart-d0de0868-6349-4d3c-894b-cb0469a5cf1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272873265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1272873265
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3695258496
Short name T524
Test name
Test status
Simulation time 620204535649 ps
CPU time 1428.8 seconds
Started May 14 03:09:31 PM PDT 24
Finished May 14 03:33:22 PM PDT 24
Peak memory 201904 kb
Host smart-80241712-2874-4cb8-9486-3bd544d37fcb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695258496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3695258496
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4073650997
Short name T380
Test name
Test status
Simulation time 73224036016 ps
CPU time 431.8 seconds
Started May 14 03:09:42 PM PDT 24
Finished May 14 03:16:55 PM PDT 24
Peak memory 202156 kb
Host smart-9d107136-95b6-418b-8a6d-bde0cbefc8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073650997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4073650997
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2191872417
Short name T447
Test name
Test status
Simulation time 25306800706 ps
CPU time 59.91 seconds
Started May 14 03:09:42 PM PDT 24
Finished May 14 03:10:43 PM PDT 24
Peak memory 201692 kb
Host smart-56419b12-4321-4c88-bf76-7f4b3351c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191872417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2191872417
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1384578430
Short name T364
Test name
Test status
Simulation time 4305132827 ps
CPU time 11.39 seconds
Started May 14 03:09:42 PM PDT 24
Finished May 14 03:09:55 PM PDT 24
Peak memory 201608 kb
Host smart-43a0545c-0a53-4d7a-b836-d63c0439965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384578430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1384578430
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.697004677
Short name T353
Test name
Test status
Simulation time 5510898737 ps
CPU time 12.74 seconds
Started May 14 03:09:29 PM PDT 24
Finished May 14 03:09:43 PM PDT 24
Peak memory 201660 kb
Host smart-0cb11b3f-ea85-4138-a32c-4d054ba80c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697004677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.697004677
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.771720079
Short name T155
Test name
Test status
Simulation time 172644641108 ps
CPU time 592.44 seconds
Started May 14 03:09:42 PM PDT 24
Finished May 14 03:19:37 PM PDT 24
Peak memory 218044 kb
Host smart-d059d12b-1d37-4cc6-8c51-c3370c2c9cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771720079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
771720079
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2286576257
Short name T716
Test name
Test status
Simulation time 499161032 ps
CPU time 0.67 seconds
Started May 14 02:58:30 PM PDT 24
Finished May 14 02:58:32 PM PDT 24
Peak memory 201480 kb
Host smart-08d96fc1-7187-47dc-89ac-0caa07636a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286576257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2286576257
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2150547375
Short name T184
Test name
Test status
Simulation time 512160144964 ps
CPU time 168.34 seconds
Started May 14 02:58:31 PM PDT 24
Finished May 14 03:01:20 PM PDT 24
Peak memory 201704 kb
Host smart-6e4d6c18-0c61-447e-aa18-adbbc10ac911
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150547375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2150547375
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.773078845
Short name T181
Test name
Test status
Simulation time 512081358733 ps
CPU time 205.7 seconds
Started May 14 02:58:30 PM PDT 24
Finished May 14 03:01:57 PM PDT 24
Peak memory 201820 kb
Host smart-706c1e14-eb5c-4135-a734-ac9cbbb9d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773078845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.773078845
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2985716186
Short name T125
Test name
Test status
Simulation time 327387260800 ps
CPU time 382.03 seconds
Started May 14 02:58:26 PM PDT 24
Finished May 14 03:04:49 PM PDT 24
Peak memory 201840 kb
Host smart-af85dd8f-627d-47f9-bd7a-862b026211ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985716186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2985716186
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4212529667
Short name T396
Test name
Test status
Simulation time 497533613309 ps
CPU time 595.42 seconds
Started May 14 02:58:22 PM PDT 24
Finished May 14 03:08:18 PM PDT 24
Peak memory 201860 kb
Host smart-7081930c-badb-4d6b-9fc2-e2c3c44fe1a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212529667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4212529667
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2884927417
Short name T688
Test name
Test status
Simulation time 491789742212 ps
CPU time 534.27 seconds
Started May 14 02:58:26 PM PDT 24
Finished May 14 03:07:22 PM PDT 24
Peak memory 201900 kb
Host smart-f270b9ce-4e12-4600-8784-9e9dba830ebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884927417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2884927417
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.287022384
Short name T278
Test name
Test status
Simulation time 175239999102 ps
CPU time 206.93 seconds
Started May 14 02:58:24 PM PDT 24
Finished May 14 03:01:52 PM PDT 24
Peak memory 201816 kb
Host smart-e8cf5cc1-c8ea-4515-8fea-ef9c928724ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287022384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.287022384
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1104572661
Short name T776
Test name
Test status
Simulation time 613198016870 ps
CPU time 364.42 seconds
Started May 14 02:58:26 PM PDT 24
Finished May 14 03:04:31 PM PDT 24
Peak memory 201820 kb
Host smart-98d28fe6-926d-4fc2-89bd-8127954460a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104572661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1104572661
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3821705849
Short name T783
Test name
Test status
Simulation time 135295265568 ps
CPU time 434.77 seconds
Started May 14 02:58:30 PM PDT 24
Finished May 14 03:05:46 PM PDT 24
Peak memory 202148 kb
Host smart-54774871-c369-42a5-8677-085100e51d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821705849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3821705849
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.785135349
Short name T760
Test name
Test status
Simulation time 44017073281 ps
CPU time 24.76 seconds
Started May 14 02:58:31 PM PDT 24
Finished May 14 02:58:57 PM PDT 24
Peak memory 201624 kb
Host smart-8a2fe2ec-04c4-4813-a67a-893f12817987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785135349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.785135349
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.434189390
Short name T508
Test name
Test status
Simulation time 4828206472 ps
CPU time 12.8 seconds
Started May 14 02:58:31 PM PDT 24
Finished May 14 02:58:45 PM PDT 24
Peak memory 201628 kb
Host smart-8fc2c581-ad0d-405a-bd60-2c2c703739d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434189390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.434189390
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4183771183
Short name T535
Test name
Test status
Simulation time 5950786487 ps
CPU time 7.63 seconds
Started May 14 02:58:22 PM PDT 24
Finished May 14 02:58:30 PM PDT 24
Peak memory 201628 kb
Host smart-973e4d5c-e45a-40d7-9c95-52c888a0ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183771183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4183771183
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2748676163
Short name T295
Test name
Test status
Simulation time 579724206962 ps
CPU time 1252.26 seconds
Started May 14 02:58:31 PM PDT 24
Finished May 14 03:19:24 PM PDT 24
Peak memory 201756 kb
Host smart-b3d3fc44-30c2-4eda-ac91-4bb6177761cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748676163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2748676163
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4275313250
Short name T17
Test name
Test status
Simulation time 118418447233 ps
CPU time 122.95 seconds
Started May 14 02:58:29 PM PDT 24
Finished May 14 03:00:34 PM PDT 24
Peak memory 210444 kb
Host smart-01adc48c-0ba1-4556-92d2-aed6d0845c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275313250 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4275313250
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.744288242
Short name T405
Test name
Test status
Simulation time 343815493 ps
CPU time 0.83 seconds
Started May 14 02:58:57 PM PDT 24
Finished May 14 02:58:58 PM PDT 24
Peak memory 201488 kb
Host smart-3b32ec33-4f96-4ceb-b156-77a85e27d5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744288242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.744288242
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.832177154
Short name T186
Test name
Test status
Simulation time 165058798103 ps
CPU time 365.2 seconds
Started May 14 02:58:39 PM PDT 24
Finished May 14 03:04:46 PM PDT 24
Peak memory 201860 kb
Host smart-9813933a-1207-4acb-869d-43237a622c4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832177154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.832177154
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2732542626
Short name T251
Test name
Test status
Simulation time 326772813065 ps
CPU time 96.57 seconds
Started May 14 02:58:38 PM PDT 24
Finished May 14 03:00:16 PM PDT 24
Peak memory 201816 kb
Host smart-cd9cabbd-c3c8-4e92-9e6a-f47eed822068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732542626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2732542626
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3480025271
Short name T92
Test name
Test status
Simulation time 503561146071 ps
CPU time 305.92 seconds
Started May 14 02:58:41 PM PDT 24
Finished May 14 03:03:48 PM PDT 24
Peak memory 201904 kb
Host smart-2238825a-3c09-40d6-8ebd-43ed34972a55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480025271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3480025271
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2523658254
Short name T225
Test name
Test status
Simulation time 495023313220 ps
CPU time 1152.94 seconds
Started May 14 02:58:40 PM PDT 24
Finished May 14 03:17:55 PM PDT 24
Peak memory 201888 kb
Host smart-188f8dbf-b1c5-4ec4-a812-184f55a78b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523658254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2523658254
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2491295853
Short name T407
Test name
Test status
Simulation time 325940822649 ps
CPU time 743.96 seconds
Started May 14 02:58:41 PM PDT 24
Finished May 14 03:11:06 PM PDT 24
Peak memory 202120 kb
Host smart-de293802-0673-4eb7-9a9c-8f961e3b2ae5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491295853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2491295853
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1003645475
Short name T548
Test name
Test status
Simulation time 200872567709 ps
CPU time 114.48 seconds
Started May 14 02:58:40 PM PDT 24
Finished May 14 03:00:36 PM PDT 24
Peak memory 201776 kb
Host smart-e210b965-2a9c-4b5a-82f4-fd437ef7fe2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003645475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1003645475
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1512511507
Short name T706
Test name
Test status
Simulation time 121264963499 ps
CPU time 632.45 seconds
Started May 14 02:58:47 PM PDT 24
Finished May 14 03:09:21 PM PDT 24
Peak memory 202228 kb
Host smart-84c7cce4-f57b-48b8-9741-ff0cfe127e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512511507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1512511507
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3141570683
Short name T532
Test name
Test status
Simulation time 28107516864 ps
CPU time 65.2 seconds
Started May 14 02:58:47 PM PDT 24
Finished May 14 02:59:54 PM PDT 24
Peak memory 201580 kb
Host smart-202126d3-7c72-416b-b419-8c307c22590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141570683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3141570683
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.277283582
Short name T191
Test name
Test status
Simulation time 4031826723 ps
CPU time 9.25 seconds
Started May 14 02:58:49 PM PDT 24
Finished May 14 02:58:59 PM PDT 24
Peak memory 201572 kb
Host smart-77935f24-2d1e-4e95-a95f-a31213916167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277283582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.277283582
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.937494461
Short name T387
Test name
Test status
Simulation time 5881561326 ps
CPU time 4.86 seconds
Started May 14 02:58:31 PM PDT 24
Finished May 14 02:58:37 PM PDT 24
Peak memory 201612 kb
Host smart-e264cc96-4a9b-4559-83ce-e5c1aed9fd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937494461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.937494461
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3472591312
Short name T575
Test name
Test status
Simulation time 27421679986 ps
CPU time 33.61 seconds
Started May 14 02:58:57 PM PDT 24
Finished May 14 02:59:31 PM PDT 24
Peak memory 201560 kb
Host smart-d3ad8e8f-edbe-446e-b602-dc9dd1cd67bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472591312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3472591312
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.304213278
Short name T14
Test name
Test status
Simulation time 550453598355 ps
CPU time 81.19 seconds
Started May 14 02:58:50 PM PDT 24
Finished May 14 03:00:12 PM PDT 24
Peak memory 218276 kb
Host smart-68d5b3fe-df0e-4ed3-85d2-23fc833d478e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304213278 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.304213278
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.857951197
Short name T565
Test name
Test status
Simulation time 496587771 ps
CPU time 0.93 seconds
Started May 14 02:59:19 PM PDT 24
Finished May 14 02:59:21 PM PDT 24
Peak memory 201496 kb
Host smart-1a810bcb-e6c4-4a03-86cc-dc1c0694a7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857951197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.857951197
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.319437377
Short name T775
Test name
Test status
Simulation time 494713032051 ps
CPU time 1212.42 seconds
Started May 14 02:59:07 PM PDT 24
Finished May 14 03:19:20 PM PDT 24
Peak memory 201832 kb
Host smart-60973bee-3353-428c-9490-0c04d802bed4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319437377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.319437377
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3413376114
Short name T262
Test name
Test status
Simulation time 165270699391 ps
CPU time 404.47 seconds
Started May 14 02:59:05 PM PDT 24
Finished May 14 03:05:50 PM PDT 24
Peak memory 201876 kb
Host smart-ea5815fe-063c-4a26-9883-cdb058df57f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413376114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3413376114
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.206548590
Short name T570
Test name
Test status
Simulation time 324576952225 ps
CPU time 380.91 seconds
Started May 14 02:59:06 PM PDT 24
Finished May 14 03:05:28 PM PDT 24
Peak memory 201960 kb
Host smart-dde6ca8c-e54f-4b13-9745-f8037d547c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206548590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.206548590
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3037313143
Short name T592
Test name
Test status
Simulation time 163550451928 ps
CPU time 390.18 seconds
Started May 14 02:59:06 PM PDT 24
Finished May 14 03:05:37 PM PDT 24
Peak memory 201784 kb
Host smart-d1a50e56-92d8-400f-96b2-2ea23f49cc15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037313143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3037313143
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2924280142
Short name T271
Test name
Test status
Simulation time 497595561180 ps
CPU time 1210.83 seconds
Started May 14 02:59:06 PM PDT 24
Finished May 14 03:19:18 PM PDT 24
Peak memory 201788 kb
Host smart-fd5757c8-0fad-438b-b918-e47e0826664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924280142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2924280142
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2724976469
Short name T655
Test name
Test status
Simulation time 159740647870 ps
CPU time 94.87 seconds
Started May 14 02:59:05 PM PDT 24
Finished May 14 03:00:41 PM PDT 24
Peak memory 201848 kb
Host smart-4fb45da1-674c-49cc-aaf1-57c67401957f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724976469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2724976469
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.438946710
Short name T329
Test name
Test status
Simulation time 380565650315 ps
CPU time 253.89 seconds
Started May 14 02:59:07 PM PDT 24
Finished May 14 03:03:22 PM PDT 24
Peak memory 201852 kb
Host smart-aa6ac333-1890-45eb-a608-f3693525e592
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438946710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.438946710
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.72727290
Short name T98
Test name
Test status
Simulation time 389930635346 ps
CPU time 216.72 seconds
Started May 14 02:59:06 PM PDT 24
Finished May 14 03:02:44 PM PDT 24
Peak memory 201848 kb
Host smart-e3edd568-f322-4711-b584-b0d090e41158
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72727290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.ad
c_ctrl_filters_wakeup_fixed.72727290
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.620340122
Short name T419
Test name
Test status
Simulation time 116865485273 ps
CPU time 617.29 seconds
Started May 14 02:59:19 PM PDT 24
Finished May 14 03:09:37 PM PDT 24
Peak memory 202176 kb
Host smart-91183bbc-3f1c-4d83-a93a-acf056eab34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620340122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.620340122
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.920810538
Short name T722
Test name
Test status
Simulation time 32040136435 ps
CPU time 19.27 seconds
Started May 14 02:59:18 PM PDT 24
Finished May 14 02:59:39 PM PDT 24
Peak memory 201604 kb
Host smart-ac563514-6849-40e1-8c07-d67ed63c0e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920810538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.920810538
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.208871713
Short name T377
Test name
Test status
Simulation time 3595408321 ps
CPU time 2.9 seconds
Started May 14 02:59:18 PM PDT 24
Finished May 14 02:59:21 PM PDT 24
Peak memory 201460 kb
Host smart-326411af-6540-4b98-b64e-e506301d418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208871713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.208871713
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.525987664
Short name T455
Test name
Test status
Simulation time 5667267654 ps
CPU time 3.11 seconds
Started May 14 02:58:56 PM PDT 24
Finished May 14 02:59:00 PM PDT 24
Peak memory 201564 kb
Host smart-1ee42b1c-abec-45f2-9521-c63bb5a5a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525987664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.525987664
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.833616361
Short name T778
Test name
Test status
Simulation time 38292068041 ps
CPU time 24.61 seconds
Started May 14 02:59:18 PM PDT 24
Finished May 14 02:59:44 PM PDT 24
Peak memory 201572 kb
Host smart-cd90cae2-dac3-4c5c-bdd7-4bda04dcf82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833616361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.833616361
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2664894738
Short name T616
Test name
Test status
Simulation time 20437226980 ps
CPU time 48.45 seconds
Started May 14 02:59:20 PM PDT 24
Finished May 14 03:00:10 PM PDT 24
Peak memory 210156 kb
Host smart-c308c436-0bef-42b8-9a24-d3c61b8568bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664894738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2664894738
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1812807313
Short name T695
Test name
Test status
Simulation time 451212459 ps
CPU time 1.15 seconds
Started May 14 03:00:38 PM PDT 24
Finished May 14 03:00:40 PM PDT 24
Peak memory 201516 kb
Host smart-abab063c-97bc-4800-8b86-951cf6aa8a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812807313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1812807313
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1676968510
Short name T127
Test name
Test status
Simulation time 167500986308 ps
CPU time 379.07 seconds
Started May 14 02:59:34 PM PDT 24
Finished May 14 03:05:54 PM PDT 24
Peak memory 201824 kb
Host smart-9f70d820-9616-4e17-9298-cea2769addff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676968510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1676968510
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3080150461
Short name T236
Test name
Test status
Simulation time 168112647811 ps
CPU time 374.31 seconds
Started May 14 02:59:28 PM PDT 24
Finished May 14 03:05:43 PM PDT 24
Peak memory 201780 kb
Host smart-92b5fb66-cf16-44af-a327-9292eef383ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080150461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3080150461
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2713212119
Short name T226
Test name
Test status
Simulation time 164219571023 ps
CPU time 109.17 seconds
Started May 14 02:59:31 PM PDT 24
Finished May 14 03:01:22 PM PDT 24
Peak memory 202068 kb
Host smart-f6351bac-b02c-4fbc-8e27-dc69ee83f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713212119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2713212119
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3629169070
Short name T637
Test name
Test status
Simulation time 329030487539 ps
CPU time 213.33 seconds
Started May 14 02:59:33 PM PDT 24
Finished May 14 03:03:08 PM PDT 24
Peak memory 201824 kb
Host smart-bb9ce541-69c4-46cd-9bac-a534a188cbc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629169070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3629169070
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4269531511
Short name T513
Test name
Test status
Simulation time 159828010684 ps
CPU time 99.18 seconds
Started May 14 02:59:19 PM PDT 24
Finished May 14 03:01:00 PM PDT 24
Peak memory 201844 kb
Host smart-09f82144-0274-43c3-98ee-3570921409aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269531511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.4269531511
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3572298097
Short name T496
Test name
Test status
Simulation time 169655952814 ps
CPU time 71.67 seconds
Started May 14 02:59:30 PM PDT 24
Finished May 14 03:00:43 PM PDT 24
Peak memory 202140 kb
Host smart-9d581495-be69-4887-98ad-44cdc03c7851
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572298097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3572298097
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3772051179
Short name T411
Test name
Test status
Simulation time 206557686842 ps
CPU time 482.97 seconds
Started May 14 02:59:33 PM PDT 24
Finished May 14 03:07:38 PM PDT 24
Peak memory 201840 kb
Host smart-51a53745-3ca2-49d5-9705-b81663e251dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772051179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3772051179
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4003433661
Short name T643
Test name
Test status
Simulation time 100011725809 ps
CPU time 482.33 seconds
Started May 14 02:59:28 PM PDT 24
Finished May 14 03:07:31 PM PDT 24
Peak memory 202172 kb
Host smart-37b69fbe-7bb3-4944-a9e6-628bff48e1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003433661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4003433661
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3674250824
Short name T174
Test name
Test status
Simulation time 41026202536 ps
CPU time 96.98 seconds
Started May 14 02:59:28 PM PDT 24
Finished May 14 03:01:06 PM PDT 24
Peak memory 201556 kb
Host smart-61fa0b07-e57a-4e9a-9cb8-6c95cdbb0301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674250824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3674250824
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.213947863
Short name T593
Test name
Test status
Simulation time 3088678556 ps
CPU time 2.26 seconds
Started May 14 02:59:30 PM PDT 24
Finished May 14 02:59:34 PM PDT 24
Peak memory 201816 kb
Host smart-bc47dfa7-5568-41aa-9dd0-6799b85b8a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213947863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.213947863
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1252444465
Short name T121
Test name
Test status
Simulation time 6015726270 ps
CPU time 14.65 seconds
Started May 14 02:59:20 PM PDT 24
Finished May 14 02:59:35 PM PDT 24
Peak memory 201660 kb
Host smart-1dd6bc0b-1e36-4bea-a1f9-95ccc361e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252444465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1252444465
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1051015814
Short name T335
Test name
Test status
Simulation time 199626530200 ps
CPU time 339.9 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:06:21 PM PDT 24
Peak memory 201768 kb
Host smart-eeeddf4c-4f0b-46b4-b26d-ddd5f9991871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051015814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1051015814
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1273106888
Short name T554
Test name
Test status
Simulation time 415679593 ps
CPU time 1.59 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:00:43 PM PDT 24
Peak memory 201632 kb
Host smart-b64319e8-f8bc-4ea4-b4bd-e6e9e67097fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273106888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1273106888
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1030928336
Short name T624
Test name
Test status
Simulation time 185538744096 ps
CPU time 199.94 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:04:01 PM PDT 24
Peak memory 201876 kb
Host smart-cb44d9c6-de10-4d99-bf96-6bfa4730996b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030928336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1030928336
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2958373710
Short name T338
Test name
Test status
Simulation time 185706809446 ps
CPU time 444.65 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:08:07 PM PDT 24
Peak memory 201744 kb
Host smart-648a60f7-90fd-490f-a0f3-a1be529cc199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958373710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2958373710
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.826320150
Short name T700
Test name
Test status
Simulation time 323836885968 ps
CPU time 403.8 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:07:25 PM PDT 24
Peak memory 201880 kb
Host smart-a678cd04-2e4f-4cae-8732-28aa24e9b20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826320150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.826320150
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.470349186
Short name T598
Test name
Test status
Simulation time 480780270659 ps
CPU time 272.91 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:05:13 PM PDT 24
Peak memory 201692 kb
Host smart-0b9728b2-8a7e-4bf0-9c2c-b1c9a854af13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470349186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.470349186
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2559630279
Short name T248
Test name
Test status
Simulation time 332063872905 ps
CPU time 205.31 seconds
Started May 14 03:00:38 PM PDT 24
Finished May 14 03:04:05 PM PDT 24
Peak memory 201852 kb
Host smart-fa222dde-61ab-48cd-b694-5eaada4ab480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559630279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2559630279
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3531808662
Short name T618
Test name
Test status
Simulation time 494009788845 ps
CPU time 310.39 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:05:51 PM PDT 24
Peak memory 201804 kb
Host smart-79f47e03-a7dd-4dc7-a72f-de4d0c55a2c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531808662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3531808662
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2253680499
Short name T228
Test name
Test status
Simulation time 598567704752 ps
CPU time 1352.67 seconds
Started May 14 03:00:38 PM PDT 24
Finished May 14 03:23:13 PM PDT 24
Peak memory 201888 kb
Host smart-44995ce6-f8d3-4db0-a34c-bd0b5a894327
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253680499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2253680499
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1594718872
Short name T398
Test name
Test status
Simulation time 599264275329 ps
CPU time 350.34 seconds
Started May 14 03:00:38 PM PDT 24
Finished May 14 03:06:30 PM PDT 24
Peak memory 201764 kb
Host smart-5d90b88c-b9ea-4872-9dc3-d7c14c09f02d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594718872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1594718872
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.794959457
Short name T77
Test name
Test status
Simulation time 135248305002 ps
CPU time 388.32 seconds
Started May 14 03:00:40 PM PDT 24
Finished May 14 03:07:10 PM PDT 24
Peak memory 202368 kb
Host smart-1d6f0672-d7dc-4295-a70b-7be1c97a7480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794959457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.794959457
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1207817063
Short name T745
Test name
Test status
Simulation time 39663749634 ps
CPU time 66.01 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:01:46 PM PDT 24
Peak memory 201548 kb
Host smart-fb29ae4a-ce58-4e00-8932-8de5aaf32d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207817063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1207817063
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1991589506
Short name T375
Test name
Test status
Simulation time 5247428854 ps
CPU time 3.88 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:00:45 PM PDT 24
Peak memory 201620 kb
Host smart-0377e474-f278-4f71-b66d-5bf13b6362ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991589506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1991589506
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1892167426
Short name T370
Test name
Test status
Simulation time 5912031129 ps
CPU time 13.91 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:00:56 PM PDT 24
Peak memory 201720 kb
Host smart-743e9f22-aec2-4ff5-8bfc-19ac0dcbc719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892167426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1892167426
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.810345008
Short name T230
Test name
Test status
Simulation time 135416987676 ps
CPU time 86.62 seconds
Started May 14 03:00:39 PM PDT 24
Finished May 14 03:02:08 PM PDT 24
Peak memory 210452 kb
Host smart-8fb18132-1454-4efe-8d53-ae5591d85619
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810345008 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.810345008
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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