Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6903	1			T1	20		T5	5		T6	55
testmodes[AdcCtrlTestmodeNormal]	5281	1			T2	3		T4	1		T5	7
testmodes[AdcCtrlTestmodeLowpower]	5623	1			T3	3		T6	53		T7	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3834	1			T1	19		T5	3		T6	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1643	1			T5	2		T6	16		T8	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1315	1			T6	20		T45	17		T49	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1655	1			T5	2		T6	21		T8	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1931	1			T2	2		T5	4		T6	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1364	1			T6	12		T45	15		T46	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1307	1			T6	16		T45	11		T46	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1373	1			T6	17		T45	22		T46	29
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2686	1			T3	2		T6	20		T9	2