Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22157

1

T1

20

T2

10

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3801

1

T2

7

T4

17

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19889

1

T1

20

T2

17

T5

12

auto[1]

6069

1

T3

26

T4

17

T9

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	51	1			T194	13		T195	25		T196	12
values[1]	549	1			T27	7		T31	6		T34	10
values[2]	659	1			T2	10		T7	5		T15	11
values[3]	825	1			T2	3		T12	10		T13	1
values[4]	2842	1			T3	26		T9	24		T102	2
values[5]	770	1			T11	1		T13	2		T17	54
values[6]	748	1			T55	23		T38	3		T127	16
values[7]	907	1			T4	17		T11	1		T14	15
values[8]	641	1			T31	3		T158	20		T36	17
values[9]	1091	1			T2	4		T11	1		T17	21
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	736	1			T15	11		T27	7		T31	6
values[1]	640	1			T2	10		T7	5		T37	14
values[2]	806	1			T2	3		T12	10		T13	1
values[3]	2899	1			T3	26		T9	24		T13	2
values[4]	790	1			T11	1		T17	54		T31	9
values[5]	750	1			T101	14		T55	23		T38	3
values[6]	851	1			T4	17		T11	1		T14	15
values[7]	643	1			T11	1		T101	15		T37	50
values[8]	697	1			T2	4		T17	21		T30	6
values[9]	248	1			T197	29		T198	14		T82	9
minimum	16898	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	11		T31	6		T18	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T27	5		T34	10		T69	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	1		T37	6		T27	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	5		T38	2		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	1		T13	1		T27	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T35	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T3	26		T9	24		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T30	3		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T11	1		T137	13		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T17	26		T31	9		T200	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T101	1		T127	4		T144	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T55	14		T38	3		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	1		T44	15		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	1		T11	1		T125	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T101	1		T158	10		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T37	18		T201	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	6		T202	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T17	13		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T198	14		T82	1		T203	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T197	17		T204	14		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16772	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	9		T129	15		T146	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T27	2		T43	1		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	9		T37	8		T27	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	1		T206	2		T207	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	9		T27	13		T55	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	2		T35	11		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T33	30		T208	20		T209	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	2		T35	4		T69	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T21	2		T210	1		T211	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T17	28		T200	10		T212	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T101	13		T127	12		T171	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T55	9		T130	9		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	14		T129	2		T171	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	16		T125	14		T36	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T101	14		T158	10		T213	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	32		T201	10		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T159	11		T214	1		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	3		T17	8		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T82	8		T203	18		T216	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T197	12		T204	13		T178	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	5		T69	2		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T196	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T194	8		T195	14		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	6		T18	4		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	5		T34	10		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	1		T15	11		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	5		T36	1		T42	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T13	1		T27	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T35	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T3	26		T9	24		T102	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	3		T69	1		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T13	1		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T17	26		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T127	4		T144	7		T171	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T55	14		T38	3		T169	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	1		T101	2		T44	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	1		T11	1		T37	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T31	3		T158	10		T218	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	1		T160	1		T201	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T30	6		T202	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T2	1		T11	1		T17	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T194	5		T195	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	11		T151	9		T129	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T27	2		T219	9		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	9		T37	8		T55	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T42	2		T43	1		T205	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	9		T27	31		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	2		T35	11		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T33	30		T208	20		T209	36
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	2		T69	15		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	2		T210	1		T140	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	28		T35	4		T200	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T127	12		T171	5		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T55	9		T169	9		T85	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	14		T101	27		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	16		T37	32		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T158	10		T218	8		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	16		T201	10		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T159	11		T213	1		T82	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T2	3		T17	8		T138	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	1		T31	1		T18	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T27	3		T34	1		T69	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	10		T37	10		T27	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	1		T38	2		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T12	10		T13	1		T27	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	3		T35	12		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T3	3		T9	3		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T30	3		T35	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T137	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T17	31		T31	1		T200	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T101	14		T127	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T55	10		T38	3		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T14	15		T44	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	17		T11	1		T125	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T101	15		T158	11		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T37	35		T201	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	1		T202	1		T159	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	4		T17	10		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T198	1		T82	9		T203	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T197	13		T204	14		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16887	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	10		T31	5		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	4		T34	9		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T37	4		T27	13		T207	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	4		T38	1		T206	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	5		T55	11		T56	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	12		T36	5		T128	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T3	23		T9	21		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T30	2		T127	9		T197	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T137	12		T21	2		T210	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T17	23		T31	8		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T127	3		T144	6		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T55	13		T80	8		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T44	14		T31	2		T129	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T125	9		T169	7		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T158	9		T218	8		T223	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	15		T201	12		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T30	5		T198	14		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T17	11		T21	2		T141	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T198	13		T203	20		T216	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T197	16		T204	13		T224	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T135	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T196	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T194	9		T195	12		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	1		T18	3		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	3		T34	1		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	10		T15	1		T37	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T36	1		T42	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	10		T13	1		T27	33
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	3		T35	12		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T3	3		T9	3		T102	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	3		T69	16		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	1		T13	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	1		T17	31		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T127	13		T144	1		T171	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T55	10		T38	3		T169	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	15		T101	29		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T4	17		T11	1		T37	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T31	1		T158	11		T218	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	17		T160	1		T201	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T30	1		T202	1		T159	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T2	4		T11	1		T17	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T196	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T194	4		T195	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T31	5		T18	1		T135	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T27	4		T34	9		T219	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	10		T37	4		T55	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	4		T42	4		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	18		T56	2		T127	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	1		T128	12		T218	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1121	1			T3	23		T9	21		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T30	2		T136	12		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T137	12		T21	2		T210	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	23		T31	8		T200	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T127	3		T144	6		T171	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T55	13		T169	7		T80	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	14		T129	5		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	15		T125	9		T85	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T31	2		T158	9		T218	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T201	12		T222	12		T225	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	5		T198	27		T223	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T17	11		T197	16		T21	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22577

1

T1

20

T2

17

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3381

1

T7

5

T11

1

T12

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19945

1

T1

20

T2

10

T5

12

auto[1]

6013

1

T2

7

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T226	9		-	-		-	-
values[0]	90	1			T204	14		T166	11		T227	2
values[1]	660	1			T7	5		T13	1		T127	19
values[2]	864	1			T4	17		T37	50		T17	21
values[3]	737	1			T2	4		T31	3		T35	5
values[4]	661	1			T11	1		T37	14		T202	1
values[5]	638	1			T13	1		T14	15		T101	14
values[6]	577	1			T11	1		T17	54		T31	6
values[7]	743	1			T2	3		T15	11		T27	7
values[8]	3015	1			T2	10		T3	26		T9	24
values[9]	1089	1			T11	1		T12	10		T101	15
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1074	1			T7	5		T13	1		T37	50
values[1]	660	1			T4	17		T17	21		T27	51
values[2]	787	1			T2	4		T11	1		T37	14
values[3]	652	1			T14	15		T44	15		T202	1
values[4]	545	1			T13	1		T30	6		T126	1
values[5]	636	1			T2	3		T11	1		T101	14
values[6]	2941	1			T3	26		T9	24		T15	11
values[7]	778	1			T2	10		T101	15		T55	20
values[8]	860	1			T11	1		T12	10		T13	1
values[9]	150	1			T125	24		T38	3		T138	10
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	1		T37	18		T127	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	5		T38	2		T128	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T35	1		T158	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	13		T27	20		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	1		T11	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	3		T69	1		T144	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T202	1		T36	6		T171	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T44	15		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	6		T126	1		T129	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	1		T127	4		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T2	1		T56	3		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	1		T101	1		T17	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T3	26		T9	24		T15	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	4		T137	13		T20	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T101	1		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T69	1		T146	2		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T13	1		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	1		T35	1		T139	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T125	10		T38	3		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T42	7		T222	1		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T37	32		T127	19		T129	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T38	1		T128	9		T171	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	16		T35	4		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	8		T27	31		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	3		T37	8		T151	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T69	15		T218	11		T197	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T171	12		T213	1		T229	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	14		T130	9		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T129	2		T205	2		T22	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	12		T128	4		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	2		T56	4		T212	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T101	13		T17	28		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T30	2		T33	30		T55	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T20	13		T231	12		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	9		T101	14		T55	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T146	2		T140	10		T222	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	15		T212	1		T82	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	9		T35	11		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T125	14		T138	9		T85	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T42	2		T222	1		T228	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T226	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T204	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T166	11		T227	1		T232	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T127	10		T129	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	5		T171	8		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	1		T37	18		T158	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	13		T27	20		T136	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T35	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	3		T69	1		T218	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T37	6		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T144	18		T130	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	6		T126	1		T129	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T14	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	3		T39	2		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T17	26		T31	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	1		T15	11		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T27	5		T18	4		T20	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T2	1		T3	26		T9	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T137	13		T146	2		T222	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T11	1		T101	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T12	1		T35	1		T69	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T226	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T204	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T227	1		T234	10		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T127	9		T129	8		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T171	5		T148	11		T179	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	16		T37	32		T158	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	8		T27	31		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	3		T35	4		T159	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T69	15		T218	11		T197	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	8		T151	9		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T130	9		T201	27		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T129	2		T229	15		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	14		T101	13		T128	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T56	4		T212	1		T130	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T17	28		T127	12		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	2		T30	2		T200	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T27	2		T20	13		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T2	9		T33	30		T55	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	2		T222	11		T178	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T101	14		T125	14		T129	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	9		T35	11		T42	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1