Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22157

1

T1

20

T2

10

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3801

1

T2

7

T4

17

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19863

1

T1

20

T2

17

T5

12

auto[1]

6095

1

T3

26

T4

17

T9

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	143	1			T202	1		T138	12		T82	9
values[0]	25	1			T195	25		-	-		-	-
values[1]	541	1			T15	11		T27	7		T31	6
values[2]	729	1			T2	10		T7	5		T37	14
values[3]	740	1			T2	3		T12	10		T13	1
values[4]	2891	1			T3	26		T9	24		T102	2
values[5]	753	1			T11	1		T13	2		T17	54
values[6]	776	1			T101	14		T55	23		T38	3
values[7]	910	1			T4	17		T11	1		T14	15
values[8]	617	1			T31	3		T158	20		T36	17
values[9]	958	1			T2	4		T11	1		T17	21
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	569	1			T15	11		T31	6		T69	1
values[1]	699	1			T2	10		T7	5		T37	14
values[2]	760	1			T2	3		T12	10		T13	1
values[3]	2896	1			T3	26		T9	24		T13	2
values[4]	783	1			T11	1		T17	54		T31	9
values[5]	768	1			T101	14		T55	23		T38	3
values[6]	871	1			T4	17		T11	1		T14	15
values[7]	641	1			T11	1		T31	3		T158	20
values[8]	717	1			T2	4		T17	21		T30	6
values[9]	191	1			T82	9		T147	1		T178	9
minimum	17063	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	11		T31	6		T18	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T69	1		T138	1		T43	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T37	6		T27	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	5		T126	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T13	1		T27	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T35	1		T136	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T3	26		T9	24		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T30	3		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T11	1		T137	13		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T17	26		T31	9		T200	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T101	1		T127	4		T144	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T55	14		T38	3		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T14	1		T101	1		T44	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	1		T11	1		T37	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T31	3		T158	10		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T201	13		T147	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	6		T202	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T17	13		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T82	1		T203	21		T216	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T147	1		T178	1		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16802	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T27	5		T34	10		T309	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T146	15		T82	14		T205	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T43	1		T205	2		T219	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	9		T37	8		T27	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T206	2		T207	2		T254	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	9		T27	13		T56	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	2		T35	11		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T33	30		T208	20		T209	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T30	2		T35	4		T69	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	2		T210	1		T211	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T17	28		T200	10		T212	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T101	13		T127	12		T171	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T55	9		T130	9		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	14		T101	14		T129	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	16		T37	32		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T158	10		T213	1		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T201	10		T147	7		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T159	11		T214	1		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	3		T17	8		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T82	8		T203	18		T216	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T178	8		T179	3		T310	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T27	2		T195	11		T311	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T202	1		T82	1		T207	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T138	1		T147	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T195	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	11		T31	6		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	5		T34	10		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T37	6		T55	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	5		T36	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T13	1		T27	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T35	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T3	26		T9	24		T102	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	3		T69	1		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	1		T13	1		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T17	26		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T101	1		T127	4		T144	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T55	14		T38	3		T80	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T14	1		T101	1		T44	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T11	1		T37	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T31	3		T158	10		T218	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	1		T201	13		T140	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	6		T159	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	1		T11	1		T17	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T82	8		T216	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T138	11		T178	8		T179	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T195	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	11		T151	9		T129	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T27	2		T205	2		T219	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	9		T37	8		T55	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	1		T207	2		T254	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	9		T27	31		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	2		T35	11		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T33	30		T208	20		T209	36
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	2		T69	15		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	2		T210	1		T140	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	28		T35	4		T200	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T101	13		T127	12		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T55	9		T85	10		T86	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	14		T101	14		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	16		T37	32		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T158	10		T218	8		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	16		T201	10		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T159	11		T213	1		T214	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	3		T17	8		T197	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	1		T31	1		T18	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T69	1		T138	1		T43	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	10		T37	10		T27	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	1		T126	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	10		T13	1		T27	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	3		T35	12		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T3	3		T9	3		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T30	3		T35	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T137	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T17	31		T31	1		T200	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T101	14		T127	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T55	10		T38	3		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T14	15		T101	15		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	17		T11	1		T37	35
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T31	1		T158	11		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T201	11		T147	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	1		T202	1		T159	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	4		T17	10		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T82	9		T203	19		T216	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T147	1		T178	9		T179	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16944	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T27	3		T34	1		T309	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	10		T31	5		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T43	1		T219	10		T148	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	4		T27	13		T55	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	4		T206	9		T254	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T27	5		T56	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	12		T38	1		T36	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1151	1			T3	23		T9	21		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T30	2		T127	9		T197	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T137	12		T21	2		T210	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	23		T31	8		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T127	3		T144	6		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T55	13		T80	8		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T44	14		T129	5		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T37	15		T125	9		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	2		T158	9		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T201	12		T147	7		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T30	5		T198	27		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	11		T197	16		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T203	20		T216	5		T183	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T310	11		T196	17		T270	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T135	11		T129	12		T240	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T27	4		T34	9		T195	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T202	1		T82	9		T207	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T138	12		T147	1		T178	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T195	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	1		T31	1		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T27	3		T34	1		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	10		T37	10		T55	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	1		T36	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	10		T13	1		T27	33
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	3		T35	12		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T3	3		T9	3		T102	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T30	3		T69	16		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T13	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	1		T17	31		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T101	14		T127	13		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T55	10		T38	3		T80	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	15		T101	15		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T4	17		T11	1		T37	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	1		T158	11		T218	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T36	17		T201	11		T140	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T30	1		T159	12		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T2	4		T11	1		T17	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T216	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T310	11		T312	9		T196	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T195	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	10		T31	5		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T27	4		T34	9		T219	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	4		T55	11		T207	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	4		T43	1		T254	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T27	18		T56	2		T144	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	1		T128	12		T218	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T3	23		T9	21		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	2		T136	12		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T137	12		T21	2		T210	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	23		T31	8		T200	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T127	3		T144	6		T171	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T55	13		T80	8		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T44	14		T129	5		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T37	15		T125	9		T169	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T31	2		T158	9		T218	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T201	12		T140	7		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	5		T198	27		T223	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	11		T197	16		T21	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21