Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22662

1

T1

20

T2

13

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3296

1

T2

4

T4

17

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20096

1

T1

20

T2

4

T5

12

auto[1]

5862

1

T2

13

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	465	1			T6	1		T45	2		T46	4
values[0]	35	1			T134	1		T161	10		T301	1
values[1]	634	1			T7	5		T34	10		T202	1
values[2]	2993	1			T2	10		T3	26		T9	24
values[3]	712	1			T14	15		T15	11		T27	19
values[4]	716	1			T12	10		T13	2		T17	21
values[5]	853	1			T11	1		T17	54		T27	7
values[6]	585	1			T4	17		T38	3		T127	16
values[7]	726	1			T11	1		T101	15		T37	14
values[8]	542	1			T44	15		T55	20		T159	1
values[9]	1247	1			T2	7		T11	1		T37	50
minimum	16450	1			T1	20		T5	12		T6	153

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	875	1			T7	5		T34	10		T202	1
values[1]	2928	1			T2	10		T3	26		T9	24
values[2]	740	1			T14	15		T15	11		T69	1
values[3]	823	1			T12	10		T13	2		T17	75
values[4]	709	1			T11	1		T55	23		T144	18
values[5]	687	1			T4	17		T11	1		T30	6
values[6]	665	1			T44	15		T37	14		T35	12
values[7]	518	1			T2	3		T101	15		T55	20
values[8]	1012	1			T11	1		T101	14		T37	50
values[9]	118	1			T2	4		T148	2		T278	15
minimum	16883	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T34	10		T134	1		T135	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	5		T202	1		T125	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T2	1		T3	26		T9	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T27	6		T213	1		T139	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	1		T15	11		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T69	1		T136	13		T144	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T13	2		T17	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	26		T31	6		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	1		T55	14		T144	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	2		T86	12		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T30	6		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	1		T38	3		T127	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T159	1		T160	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T44	15		T37	6		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T55	12		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T101	1		T56	3		T198	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T11	1		T37	18		T27	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T101	1		T126	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T278	1		T180	17		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T2	1		T148	1		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T183	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T135	11		T127	9		T197	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T125	14		T158	10		T197	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T2	9		T33	30		T208	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	13		T213	1		T85	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	14		T145	12		T314	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	10		T171	5		T218	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	9		T17	8		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	28		T36	16		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	9		T42	2		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T86	9		T229	8		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T200	10		T212	1		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	16		T127	12		T129	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	2		T140	25		T211	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	8		T35	11		T128	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T2	2		T55	8		T212	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T101	14		T56	4		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T37	32		T27	18		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T101	13		T159	11		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T278	14		T276	11		T315	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T2	3		T148	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	436	1			T6	1		T45	2		T46	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T101	1		T316	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T134	1		T161	1		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T317	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	10		T135	12		T197	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	5		T202	1		T197	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T2	1		T3	26		T9	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T125	10		T158	10		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	1		T15	11		T18	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T27	6		T69	1		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T13	2		T17	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T128	13		T171	8		T218	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T11	1		T27	5		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	26		T31	6		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T160	1		T212	1		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	1		T38	3		T127	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T30	6		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T101	1		T37	6		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T55	12		T159	1		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T44	15		T212	16		T198	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T2	1		T11	1		T37	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	1		T126	1		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16335	1			T1	20		T5	12		T6	153
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T318	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T101	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T161	9		T256	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T317	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T135	11		T197	13		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T197	12		T204	7		T265	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T2	9		T33	30		T208	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T125	14		T158	10		T213	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	14		T179	3		T252	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	13		T136	10		T85	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	9		T17	8		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T128	9		T171	5		T218	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	2		T35	4		T55	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	28		T36	16		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T212	1		T140	10		T161	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	16		T127	12		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T200	10		T130	6		T146	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T101	14		T37	8		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T55	8		T212	1		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T212	17		T230	11		T206	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T2	2		T37	32		T27	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	3		T159	11		T56	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T34	1		T134	1		T135	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	1		T202	1		T125	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T2	10		T3	3		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T27	14		T213	2		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	15		T15	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T69	1		T136	11		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T12	10		T13	2		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	31		T31	1		T36	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T55	10		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	2		T86	10		T229	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	1		T30	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	17		T38	3		T127	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T159	1		T160	1		T146	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T44	1		T37	10		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	3		T55	9		T212	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T101	15		T56	5		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	1		T37	35		T27	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T101	14		T126	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T278	15		T180	1		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T2	4		T148	2		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T183	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	9		T135	11		T127	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	4		T125	9		T158	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T3	23		T9	21		T143	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	5		T139	5		T85	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	10		T18	1		T314	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T136	12		T144	1		T171	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T17	11		T27	4		T129	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	23		T31	5		T128	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	13		T144	17		T42	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T86	11		T147	12		T239	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	5		T144	6		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T127	3		T129	5		T20	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T140	9		T211	10		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T44	14		T37	4		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T55	11		T147	7		T319	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T56	2		T198	14		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T37	15		T27	13		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	1		T36	5		T127	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T180	16		T276	11		T280	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T320	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T183	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	436	1			T6	1		T45	2		T46	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T101	14		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T134	1		T161	10		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T317	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	1		T135	12		T197	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	1		T202	1		T197	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T2	10		T3	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T125	15		T158	11		T213	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	15		T15	1		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	14		T69	1		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	10		T13	2		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T128	10		T171	6		T218	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	1		T27	3		T35	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T17	31		T31	1		T36	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T160	1		T212	2		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	17		T38	3		T127	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T30	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T101	15		T37	10		T35	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T55	9		T159	1		T212	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T44	1		T212	18		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	376	1			T2	3		T11	1		T37	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T2	4		T126	1		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16450	1			T1	20		T5	12		T6	153
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T318	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T316	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T256	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	9		T135	11		T197	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	4		T197	16		T204	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T3	23		T9	21		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T125	9		T158	9		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	10		T18	1		T252	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	5		T136	12		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	11		T129	12		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T128	12		T171	7		T218	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T27	4		T55	13		T144	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	23		T31	5		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T140	13		T251	12		T275	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T127	3		T129	5		T86	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	5		T144	6		T200	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	4		T137	12		T129	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T55	11		T140	7		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T44	14		T212	15		T198	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T37	15		T27	13		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T56	2		T38	1		T36	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21