Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22410

1

T1

20

T2

17

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3548

1

T7

5

T12

10

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20020

1

T1

20

T2

4

T4

17

auto[1]

5938

1

T2

13

T3

26

T7

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	178	1			T101	14		T35	12		T18	4
values[0]	32	1			T36	6		T321	5		T322	7
values[1]	730	1			T15	11		T126	1		T171	36
values[2]	692	1			T2	4		T101	15		T37	50
values[3]	482	1			T4	17		T11	1		T13	1
values[4]	690	1			T2	3		T11	1		T13	1
values[5]	2929	1			T2	10		T3	26		T7	5
values[6]	740	1			T12	10		T17	21		T31	6
values[7]	736	1			T135	23		T36	1		T129	8
values[8]	838	1			T13	1		T14	15		T44	15
values[9]	1036	1			T11	1		T37	14		T17	54
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T15	11		T101	15		T69	16
values[1]	611	1			T2	4		T37	50		T158	20
values[2]	538	1			T4	17		T11	1		T13	1
values[3]	2997	1			T2	3		T3	26		T9	24
values[4]	675	1			T2	10		T7	5		T30	5
values[5]	701	1			T12	10		T17	21		T31	6
values[6]	723	1			T44	15		T27	32		T135	23
values[7]	881	1			T13	1		T17	54		T27	7
values[8]	800	1			T11	1		T14	15		T101	14
values[9]	197	1			T35	12		T136	23		T80	9
minimum	17075	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	11		T69	1		T171	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T101	1		T39	2		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	1		T37	18		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T158	10		T129	13		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T4	1		T11	1		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T137	13		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T2	1		T3	26		T9	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T27	6		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	1		T134	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	5		T30	3		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T17	13		T31	6		T34	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T35	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T135	12		T36	1		T129	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	15		T27	14		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	12		T69	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	1		T17	26		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	1		T101	1		T37	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T138	1		T218	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T35	1		T136	13		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T80	9		T233	1		T289	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16787	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T126	1		T36	6		T323	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T69	15		T171	17		T146	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T101	14		T212	1		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	3		T37	32		T127	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T158	10		T129	15		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	16		T213	1		T205	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T210	1		T224	4		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T2	2		T33	30		T208	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	13		T125	14		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T2	9		T224	10		T22	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T30	2		T36	16		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	8		T56	4		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	9		T35	4		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T135	11		T129	2		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T27	18		T82	8		T141	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T55	8		T128	4		T146	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	28		T27	2		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T101	13		T37	8		T55	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	14		T218	11		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T35	11		T136	10		T290	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T289	29		T292	2		T293	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T248	16		T164	11		T260	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T101	1		T35	1		T18	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T289	18		T292	4		T324	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T321	2		T295	1		T235	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T36	6		T322	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	11		T171	19		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T126	1		T39	2		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T37	18		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T101	1		T158	10		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T4	1		T11	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T199	1		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	1		T11	1		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	1		T125	10		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T2	1		T3	26		T9	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	5		T27	6		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T17	13		T31	6		T34	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	1		T151	1		T197	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T135	12		T36	1		T129	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T212	16		T146	1		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	12		T69	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T14	1		T44	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	1		T37	6		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T17	26		T132	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T101	13		T35	11		T136	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T289	15		T292	2		T294	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T321	3		T295	6		T235	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T171	17		T146	2		T179	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T212	1		T194	5		T222	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	3		T37	32		T69	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T101	14		T158	10		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	16		T213	1		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T210	1		T206	5		T224	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	2		T127	9		T205	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T125	14		T159	11		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T2	9		T33	30		T208	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T27	13		T30	2		T35	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	8		T56	4		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	9		T151	9		T197	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T135	11		T129	2		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T212	17		T82	8		T253	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T55	8		T128	4		T146	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	14		T27	20		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	8		T55	9		T127	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T17	28		T218	19		T140	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	1		T69	16		T171	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T101	15		T39	2		T212	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	4		T37	35		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T158	11		T129	16		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	17		T11	1		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	1		T137	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T2	3		T3	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T27	14		T125	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	10		T134	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	1		T30	3		T36	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T17	10		T31	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	10		T35	5		T151	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T135	12		T36	1		T129	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T44	1		T27	19		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T55	9		T69	1		T128	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	1		T17	31		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	1		T101	14		T37	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	15		T138	1		T218	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T35	12		T136	11		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T80	1		T233	1		T289	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16913	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T126	1		T36	1		T323	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	10		T171	17		T239	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T140	7		T194	4		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T37	15		T127	10		T169	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T158	9		T129	12		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T140	2		T325	12		T263	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T137	12		T210	1		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T3	23		T9	21		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T27	5		T125	9		T237	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T139	5		T22	2		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	4		T30	2		T197	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	11		T31	5		T34	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	10		T42	4		T212	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T135	11		T129	5		T144	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	14		T27	13		T141	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	11		T201	12		T147	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	23		T27	4		T30	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	4		T31	2		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T218	15		T140	13		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T136	12		T25	6		T290	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T80	8		T289	24		T292	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T225	4		T326	12		T235	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T36	5		T248	13		T97	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T101	14		T35	12		T18	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T289	16		T292	3		T324	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T321	5		T295	7		T235	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T36	1		T322	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	1		T171	19		T146	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T126	1		T39	2		T212	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	4		T37	35		T69	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T101	15		T158	11		T129	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	17		T11	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T199	1		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	3		T11	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T125	15		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T2	10		T3	3		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T27	14		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T17	10		T31	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	10		T151	10		T197	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T135	12		T36	1		T129	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T212	18		T146	1		T82	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T55	9		T69	1		T128	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	1		T14	15		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	1		T37	10		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T17	31		T132	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T18	1		T136	12		T38	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T289	17		T292	3		T294	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T235	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T36	5		T322	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	10		T171	17		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T194	4		T222	12		T273	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	15		T127	10		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T158	9		T129	12		T250	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T204	13		T254	2		T325	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T210	1		T206	5		T224	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T31	8		T127	9		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T125	9		T137	12		T237	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T3	23		T9	21		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	4		T27	5		T30	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	11		T31	5		T34	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T197	16		T139	10		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T135	11		T129	5		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T212	15		T142	9		T304	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T55	11		T201	12		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	14		T27	17		T30	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T37	4		T31	2		T55	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	23		T218	23		T80	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21