Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22192

1

T1

20

T2

14

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3766

1

T2

3

T11

1

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20106

1

T1

20

T2

14

T5

12

auto[1]

5852

1

T2

3

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T202	1		T55	23		T145	10
values[0]	54	1			T265	13		T327	24		T271	16
values[1]	716	1			T7	5		T11	2		T15	11
values[2]	721	1			T13	1		T101	15		T35	5
values[3]	568	1			T4	17		T37	14		T138	1
values[4]	755	1			T2	4		T11	1		T17	21
values[5]	793	1			T2	3		T13	1		T37	50
values[6]	727	1			T14	15		T44	15		T17	54
values[7]	928	1			T13	1		T27	19		T30	6
values[8]	517	1			T2	10		T12	10		T31	3
values[9]	3043	1			T3	26		T9	24		T102	2
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	606	1			T7	5		T11	2		T34	10
values[1]	673	1			T13	1		T101	15		T35	5
values[2]	578	1			T2	4		T4	17		T37	14
values[3]	808	1			T2	3		T11	1		T17	21
values[4]	784	1			T13	1		T44	15		T37	50
values[5]	715	1			T14	15		T17	54		T31	6
values[6]	3071	1			T3	26		T9	24		T13	1
values[7]	569	1			T2	10		T12	10		T31	3
values[8]	826	1			T35	12		T202	1		T136	23
values[9]	104	1			T55	23		T328	1		T310	10
minimum	17224	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	5		T11	2		T34	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	1		T159	1		T36	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	1		T69	1		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	1		T101	1		T128	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	1		T4	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T212	1		T211	11		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	13		T27	5		T56	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T2	1		T11	1		T27	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	1		T44	15		T200	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T37	18		T30	3		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	1		T17	26		T31	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T158	10		T38	3		T169	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T3	26		T9	24		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	6		T31	9		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T12	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T213	1		T197	17		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T151	1		T139	11		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	1		T202	1		T136	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T310	5		T267	1		T270	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T55	14		T328	1		T269	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16845	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T212	1		T130	1		T204	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T127	19		T86	9		T201	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T197	13		T145	12		T82	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T35	4		T38	1		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T101	14		T128	9		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	3		T4	16		T37	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T212	1		T211	10		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T17	8		T27	2		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	2		T27	18		T214	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T200	10		T229	10		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T37	32		T30	2		T69	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	14		T17	28		T55	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T158	10		T169	9		T201	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T27	13		T33	30		T208	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T127	12		T20	13		T194	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	9		T12	9		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T213	1		T197	12		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T151	9		T145	9		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T35	11		T136	10		T205	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T310	5		T270	14		T311	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T55	9		T269	9		T274	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T101	13		T37	5		T69	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T212	1		T130	6		T204	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T145	1		T237	15		T21	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T202	1		T55	14		T142	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T271	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T265	1		T327	13		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	5		T11	2		T15	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T134	1		T159	1		T36	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	1		T69	1		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T101	1		T128	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T4	1		T37	6		T139	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T138	1		T218	9		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	1		T17	13		T27	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	1		T27	14		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	1		T200	12		T250	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T2	1		T37	18		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	1		T44	15		T17	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T30	3		T158	10		T169	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	1		T27	6		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T30	6		T31	9		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T12	1		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T197	17		T239	9		T323	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T3	26		T9	24		T102	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	1		T136	13		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T145	9		T21	2		T229	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T55	9		T178	13		T276	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T265	12		T327	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T101	13		T127	10		T201	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T197	13		T212	1		T130	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	4		T38	1		T127	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T101	14		T128	9		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T4	16		T37	8		T141	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T218	8		T212	1		T211	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	3		T17	8		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T27	18		T231	12		T214	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T200	10		T250	14		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	2		T37	32		T69	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	14		T17	28		T55	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	2		T158	10		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T27	13		T128	4		T129	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T127	12		T20	13		T194	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	9		T12	9		T135	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T197	12		T272	8		T329	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T33	30		T208	20		T209	36
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	11		T136	10		T213	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	1		T11	2		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T134	1		T159	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T35	5		T69	1		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	1		T101	15		T128	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	4		T4	17		T37	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T212	2		T211	11		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	10		T27	3		T56	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	3		T11	1		T27	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T44	1		T200	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T37	35		T30	3		T69	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	15		T17	31		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T158	11		T38	3		T169	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T3	3		T9	3		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T30	1		T31	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	10		T12	10		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T213	2		T197	13		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T151	10		T139	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	12		T202	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T310	6		T267	1		T270	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T55	10		T328	1		T269	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16973	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T212	2		T130	7		T204	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	4		T34	9		T127	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	5		T197	10		T140	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T18	1		T38	1		T218	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T128	12		T171	10		T218	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T37	4		T125	9		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T211	10		T239	7		T273	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	11		T27	4		T56	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T27	13		T198	14		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T44	14		T200	11		T304	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T37	15		T30	2		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	23		T31	5		T55	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T158	9		T169	7		T144	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T3	23		T9	21		T27	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	5		T31	8		T127	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	2		T135	11		T129	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T197	16		T42	4		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T139	10		T237	14		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T136	12		T142	4		T22	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T310	4		T270	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T55	13		T269	14		T274	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T15	10		T144	17		T194	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T204	13		T206	5		T327	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T145	10		T237	1		T21	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T202	1		T55	10		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T265	13		T327	12		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	1		T11	2		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T134	1		T159	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	5		T69	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	1		T101	15		T128	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	17		T37	10		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T138	1		T218	9		T212	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	4		T17	10		T27	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	1		T27	19		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T200	11		T250	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	3		T37	35		T69	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	15		T44	1		T17	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T30	3		T158	11		T169	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	1		T27	14		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T30	1		T31	1		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	10		T12	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T197	13		T239	1		T323	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T3	3		T9	3		T102	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T35	12		T136	11		T213	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T237	14		T21	2		T147	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T55	13		T142	4		T276	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T327	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	4		T15	10		T34	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T36	5		T197	10		T204	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	1		T38	1		T127	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T128	12		T171	10		T204	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T37	4		T139	5		T141	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T218	8		T211	25		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	11		T27	4		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T27	13		T231	12		T236	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T200	11		T250	14		T304	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T37	15		T198	14		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	14		T17	23		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	2		T158	9		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T27	5		T129	12		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T30	5		T31	8		T127	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T31	2		T135	11		T129	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T197	16		T239	8		T275	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T3	23		T9	21		T143	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T136	12		T42	4		T147	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21