Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22497

1

T1

20

T2

17

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3461

1

T7

5

T11

1

T12

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20094

1

T1

20

T2

10

T5

12

auto[1]

5864

1

T2

7

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	236	1			T31	9		T129	28		T160	1
values[0]	38	1			T204	14		T166	11		T227	2
values[1]	759	1			T7	5		T13	1		T127	40
values[2]	776	1			T4	17		T37	50		T17	21
values[3]	781	1			T2	4		T31	3		T35	5
values[4]	635	1			T11	1		T37	14		T36	6
values[5]	656	1			T13	1		T14	15		T101	14
values[6]	509	1			T11	1		T17	54		T31	6
values[7]	717	1			T2	13		T15	11		T27	7
values[8]	3096	1			T3	26		T9	24		T13	1
values[9]	880	1			T11	1		T12	10		T101	15
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	904	1			T13	1		T38	3		T127	40
values[1]	695	1			T4	17		T37	50		T17	21
values[2]	779	1			T2	4		T11	1		T37	14
values[3]	664	1			T14	15		T44	15		T30	6
values[4]	564	1			T13	1		T101	14		T126	1
values[5]	657	1			T2	3		T11	1		T17	54
values[6]	2979	1			T2	10		T3	26		T9	24
values[7]	758	1			T13	1		T101	15		T55	20
values[8]	935	1			T11	1		T12	10		T31	9
values[9]	33	1			T224	19		T244	1		T330	1
minimum	16990	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T127	21		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T38	2		T128	13		T171	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T37	18		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	13		T27	20		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T11	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T31	3		T69	1		T144	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T202	1		T36	6		T171	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	1		T44	15		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T126	1		T129	6		T198	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T101	1		T127	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T56	3		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T17	26		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T2	1		T3	26		T9	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T18	4		T137	13		T20	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T101	1		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T69	1		T146	2		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T31	9		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	1		T35	1		T139	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T224	11		T244	1		T330	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T238	10		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16798	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T7	5		T227	1		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T127	19		T138	11		T145	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T38	1		T128	9		T171	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	16		T37	32		T36	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	8		T27	31		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	3		T37	8		T35	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T69	15		T218	11		T197	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T171	12		T213	1		T229	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	14		T130	9		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T129	2		T206	5		T331	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T101	13		T127	12		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	2		T56	4		T212	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	28		T27	2		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T2	9		T30	2		T33	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T20	13		T231	12		T278	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T101	14		T55	8		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	2		T140	10		T222	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T125	14		T129	15		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	9		T35	11		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T224	8		T238	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T227	1		T241	7		T235	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T31	9		T129	13		T145	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T160	1		T147	13		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T204	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T166	11		T227	1		T232	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T127	21		T129	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	5		T171	8		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	1		T37	18		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	13		T27	20		T136	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T35	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T31	3		T69	1		T218	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T37	6		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T144	18		T130	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T202	1		T126	1		T129	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	1		T14	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T56	3		T199	1		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T17	26		T31	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	2		T15	11		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T27	5		T18	4		T20	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T3	26		T9	24		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T69	1		T137	13		T146	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	1		T101	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	1		T35	1		T139	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T129	15		T145	9		T246	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T147	11		T265	12		T293	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T204	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T227	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T127	19		T129	8		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T171	5		T148	11		T297	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	16		T37	32		T36	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	8		T27	31		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	3		T35	4		T218	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T69	15		T218	11		T197	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	8		T151	9		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T130	9		T201	10		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T129	2		T229	7		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	14		T101	13		T128	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T56	4		T212	1		T146	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T17	28		T127	12		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	11		T30	2		T200	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T27	2		T20	13		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T33	30		T55	17		T208	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T146	2		T231	12		T222	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T101	14		T125	14		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	9		T35	11		T42	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	1		T127	21		T138	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T38	2		T128	10		T171	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	17		T37	35		T36	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	10		T27	33		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T2	4		T11	1		T37	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T31	1		T69	16		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T202	1		T36	1		T171	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	15		T44	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T126	1		T129	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T101	14		T127	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	3		T56	5		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T17	31		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T2	10		T3	3		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	3		T137	1		T20	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	1		T101	15		T55	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T69	1		T146	4		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	1		T31	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T12	10		T35	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T224	9		T244	1		T330	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T238	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16914	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T7	1		T227	2		T241	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T127	19		T204	6		T142	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	1		T128	12		T171	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	15		T140	2		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	11		T27	18		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	4		T218	8		T197	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T31	2		T144	17		T218	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T36	5		T171	10		T147	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T44	14		T30	5		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T129	5		T198	13		T206	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T127	3		T43	1		T147	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T56	2		T21	2		T239	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	23		T27	4		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T3	23		T9	21		T15	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	1		T137	12		T20	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T55	11		T135	11		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	13		T222	12		T236	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	8		T125	9		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T139	10		T42	4		T237	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T224	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T238	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T129	7		T275	2		T97	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T7	4		T232	10		T235	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T31	1		T129	16		T145	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T160	1		T147	12		T265	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T204	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T166	1		T227	2		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T127	21		T129	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	1		T171	6		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	17		T37	35		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T17	10		T27	33		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T2	4		T35	5		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	1		T69	16		T218	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	1		T37	10		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	1		T130	10		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T202	1		T126	1		T129	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	1		T14	15		T101	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T56	5		T199	1		T212	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	1		T17	31		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	13		T15	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T27	3		T18	3		T20	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T3	3		T9	3		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T69	1		T137	1		T146	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	1		T101	15		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	10		T35	12		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T31	8		T129	12		T246	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T147	12		T26	1		T332	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T204	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T166	10		T232	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T127	19		T129	7		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	4		T171	7		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	15		T207	5		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	11		T27	18		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T218	8		T197	10		T80	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	2		T218	15		T197	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	4		T36	5		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T144	17		T201	12		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T129	5		T198	13		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	14		T30	5		T144	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T56	2		T21	2		T22	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	23		T31	5		T127	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	10		T30	2		T34	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T27	4		T18	1		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T3	23		T9	21		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T137	12		T231	12		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T125	9		T139	21		T85	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T139	10		T42	4		T237	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21