Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22284

1

T1

20

T2

4

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3674

1

T2

13

T11

3

T101

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19979

1

T1

20

T2

14

T5

12

auto[1]

5979

1

T2

3

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	184	1			T2	4		T202	1		T151	10
values[0]	88	1			T101	14		T140	24		T242	13
values[1]	656	1			T2	10		T11	1		T31	9
values[2]	3019	1			T3	26		T9	24		T14	15
values[3]	731	1			T17	54		T31	6		T126	1
values[4]	565	1			T2	3		T11	2		T101	15
values[5]	816	1			T7	5		T37	50		T55	23
values[6]	681	1			T12	10		T15	11		T27	7
values[7]	675	1			T13	1		T27	32		T34	10
values[8]	610	1			T13	2		T37	14		T27	19
values[9]	1058	1			T4	17		T31	3		T55	20
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	582	1			T2	10		T11	1		T14	15
values[1]	3155	1			T3	26		T9	24		T44	15
values[2]	636	1			T126	1		T159	1		T127	16
values[3]	760	1			T2	3		T11	2		T101	15
values[4]	762	1			T7	5		T15	11		T37	50
values[5]	664	1			T12	10		T27	7		T30	6
values[6]	588	1			T13	1		T27	32		T34	10
values[7]	652	1			T13	2		T37	14		T27	19
values[8]	934	1			T2	4		T4	17		T31	3
values[9]	160	1			T151	10		T224	19		T248	30
minimum	17065	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	1		T139	11		T210	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T11	1		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T3	26		T9	24		T102	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T44	15		T128	13		T169	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	2		T218	9		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T126	1		T159	1		T127	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	3		T144	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T11	2		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	5		T15	11		T127	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T37	18		T55	14		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T27	5		T171	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	6		T35	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T160	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T27	14		T34	10		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	2		T37	6		T27	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	1		T129	8		T144	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T2	1		T4	1		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T171	11		T145	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T151	1		T333	1		T334	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T224	11		T248	14		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16800	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T56	3		T80	9		T140	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	14		T210	1		T201	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	9		T135	11		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T17	28		T33	30		T208	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T128	9		T169	9		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T218	8		T212	1		T86	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T127	12		T42	2		T222	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	2		T145	12		T201	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	2		T101	14		T17	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T127	10		T213	1		T197	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T37	32		T55	9		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	9		T27	2		T171	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T35	4		T36	16		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T130	6		T231	12		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	18		T35	11		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	8		T27	13		T69	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T129	8		T85	2		T204	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	3		T4	16		T55	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T171	12		T145	9		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T151	9		T247	11		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T224	8		T248	16		T336	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T101	13		T37	5		T69	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T56	4		T140	10		T337	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T2	1		T202	1		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T206	6		T328	1		T252	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T101	1		T235	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T140	14		T242	13		T186	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T139	11		T210	3		T201	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T11	1		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T3	26		T9	24		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T44	15		T128	13		T169	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T17	26		T31	6		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T126	1		T159	1		T127	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T30	3		T144	2		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T11	2		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	5		T127	11		T144	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T37	18		T55	14		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T15	11		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T30	6		T35	1		T158	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	1		T146	1		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T27	14		T34	10		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T37	6		T27	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	1		T129	8		T144	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T4	1		T31	3		T55	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T171	11		T145	1		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T2	3		T151	9		T254	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T206	5		T252	6		T248	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T101	13		T235	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T140	10		T186	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T210	1		T201	10		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	9		T56	4		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T14	14		T33	30		T208	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T128	9		T169	9		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	28		T218	8		T86	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	12		T42	2		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T30	2		T213	1		T212	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	2		T101	14		T17	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T127	10		T197	12		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	32		T55	9		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	9		T27	2		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	4		T158	10		T36	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T231	12		T194	5		T272	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	18		T35	11		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	8		T27	13		T69	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T129	8		T85	2		T204	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	16		T55	8		T147	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T171	12		T145	9		T130	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	15		T139	1		T210	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	10		T11	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T3	3		T9	3		T102	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T44	1		T128	10		T169	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	2		T218	9		T212	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T126	1		T159	1		T127	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	3		T144	1		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	3		T11	2		T101	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	1		T15	1		T127	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T37	35		T55	10		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	10		T27	3		T171	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	1		T35	5		T36	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T160	1		T130	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	19		T34	1		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	2		T37	10		T27	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T36	1		T129	9		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	4		T4	17		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T171	13		T145	10		T130	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T151	10		T333	1		T334	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T224	9		T248	17		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16914	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T56	5		T80	1		T140	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T139	10		T210	1		T201	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T31	8		T135	11		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T3	23		T9	21		T17	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T44	14		T128	12		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T218	8		T86	11		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	3		T139	26		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	2		T144	1		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	11		T129	5		T200	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	4		T15	10		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	15		T55	13		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T27	4		T171	7		T142	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T30	5		T127	9		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T231	12		T194	4		T273	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T27	13		T34	9		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	4		T27	5		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T129	7		T144	6		T85	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T31	2		T55	11		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T171	10		T206	5		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T247	2		T234	9		T338	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T224	10		T248	13		T255	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T206	9		T298	6		T235	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T56	2		T80	8		T140	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T2	4		T202	1		T151	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T206	6		T328	1		T252	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T101	14		T235	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T140	11		T242	1		T186	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T139	1		T210	3		T201	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	10		T11	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1475	1			T3	3		T9	3		T14	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T44	1		T128	10		T169	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T17	31		T31	1		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T126	1		T159	1		T127	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T30	3		T144	1		T213	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	3		T11	2		T101	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	1		T127	11		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T37	35		T55	10		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	10		T15	1		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T30	1		T35	5		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	1		T146	1		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T27	19		T34	1		T35	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	2		T37	10		T27	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T36	1		T129	9		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	17		T31	1		T55	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T171	13		T145	10		T130	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T254	13		T324	4		T322	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T206	5		T252	6		T248	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T235	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T140	13		T242	12		T186	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T139	10		T210	1		T201	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T31	8		T56	2		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T3	23		T9	21		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T44	14		T128	12		T169	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	23		T31	5		T218	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T127	3		T139	26		T42	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T30	2		T144	1		T327	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	11		T136	12		T129	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	4		T127	10		T144	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	15		T55	13		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T15	10		T27	4		T171	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	5		T158	9		T21	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T231	12		T142	4		T194	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	13		T34	9		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T37	4		T27	5		T198	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T129	7		T144	6		T85	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T31	2		T55	11		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T171	10		T246	10		T207	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21