Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T13	1		T37	35		T127	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T7	1		T38	2		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	17		T35	5		T158	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	10		T27	33		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	4		T11	1		T37	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T31	1		T69	16		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T202	1		T36	1		T171	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	15		T44	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T30	1		T126	1		T129	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T127	13		T128	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	3		T56	5		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T101	14		T17	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T3	3		T9	3		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T18	3		T137	1		T20	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T2	10		T101	15		T55	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T69	1		T146	4		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	1		T13	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	10		T35	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T125	15		T38	3		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T42	5		T222	2		T228	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T37	15		T127	19		T129	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	4		T38	1		T128	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T158	9		T140	2		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T17	11		T27	18		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	4		T218	8		T197	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T31	2		T144	17		T218	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T36	5		T171	10		T147	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T44	14		T144	1		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T30	5		T129	5		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T127	3		T43	1		T147	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T56	2		T21	2		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	23		T27	4		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T3	23		T9	21		T15	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T18	1		T137	12		T20	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T55	11		T135	11		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	13		T222	12		T236	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T31	8		T129	12		T139	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T139	10		T237	14		T86	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T125	9		T85	11		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T42	4		T234	13		T238	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T226	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T204	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T166	1		T227	2		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T127	10		T129	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T171	6		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T4	17		T37	35		T158	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T17	10		T27	33		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T2	4		T35	5		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T31	1		T69	16		T218	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T37	10		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T144	1		T130	10		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	1		T126	1		T129	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T14	15		T101	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T56	5		T39	2		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T17	31		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	3		T15	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T27	3		T18	3		T20	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T2	10		T3	3		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T137	1		T146	4		T222	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T11	1		T101	15		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	10		T35	12		T69	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T204	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T166	10		T232	10		T234	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T127	9		T129	7		T142	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	4		T171	7		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	15		T158	9		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	11		T27	18		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T218	8		T197	10		T80	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T31	2		T218	15		T197	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	4		T36	5		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	17		T201	12		T239	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T30	5		T129	5		T198	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	14		T144	1		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T56	2		T21	2		T194	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	23		T31	5		T127	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	10		T30	2		T34	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T27	4		T18	1		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T3	23		T9	21		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	12		T222	12		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	8		T125	9		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	10		T42	4		T237	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21