Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22195

1

T1

20

T2

4

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3763

1

T2

13

T11

3

T101

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20037

1

T1

20

T2

14

T5

12

auto[1]

5921

1

T2

3

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T241	8		-	-		-	-
values[0]	54	1			T140	24		T206	12		T242	13
values[1]	633	1			T11	1		T14	15		T101	14
values[2]	3049	1			T2	10		T3	26		T9	24
values[3]	680	1			T17	75		T31	6		T18	4
values[4]	670	1			T2	3		T11	2		T101	15
values[5]	711	1			T7	5		T37	50		T55	23
values[6]	803	1			T12	10		T15	11		T27	39
values[7]	628	1			T13	1		T34	10		T35	12
values[8]	702	1			T13	1		T37	14		T27	19
values[9]	1145	1			T2	4		T4	17		T13	1
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	749	1			T2	10		T11	1		T14	15
values[1]	3122	1			T3	26		T9	24		T44	15
values[2]	702	1			T126	1		T159	1		T127	16
values[3]	727	1			T2	3		T11	2		T17	21
values[4]	780	1			T7	5		T15	11		T101	15
values[5]	652	1			T12	10		T27	7		T35	5
values[6]	597	1			T13	1		T27	51		T34	10
values[7]	644	1			T13	2		T37	14		T69	17
values[8]	826	1			T4	17		T31	3		T202	1
values[9]	283	1			T2	4		T151	10		T41	1
minimum	16876	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T101	1		T139	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T11	1		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T3	26		T9	24		T102	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T44	15		T134	1		T128	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T39	2		T218	9		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T126	1		T159	1		T127	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	3		T144	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T11	2		T17	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	5		T15	11		T127	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T101	1		T37	18		T30	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	1		T27	5		T171	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	1		T36	1		T127	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T27	6		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	14		T34	10		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	2		T37	6		T69	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	1		T129	8		T144	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T4	1		T31	3		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T171	11		T145	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T2	1		T151	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T207	6		T224	11		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16761	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	14		T101	13		T229	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	9		T56	4		T135	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T17	28		T33	30		T208	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T128	9		T169	9		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T218	8		T212	1		T86	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T127	12		T42	2		T222	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	2		T145	12		T201	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	2		T17	8		T129	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T127	10		T213	1		T212	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T101	14		T37	32		T55	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	9		T27	2		T171	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	4		T36	16		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T27	13		T130	6		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T27	18		T35	11		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	8		T69	15		T128	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T129	8		T85	2		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	16		T55	8		T147	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T171	12		T145	9		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T2	3		T151	9		T244	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T207	16		T224	8		T243	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T241	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T206	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T140	14		T242	13		T245	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	1		T101	1		T139	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T134	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T3	26		T9	24		T102	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	1		T44	15		T31	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T17	26		T31	6		T18	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	13		T126	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	3		T144	2		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	1		T11	2		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	5		T127	11		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T37	18		T55	14		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T15	11		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T27	14		T30	6		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T128	1		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	10		T35	1		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T37	6		T27	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	1		T129	8		T144	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T2	1		T4	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T171	11		T145	1		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T241	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T140	10		T245	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	14		T101	13		T210	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T56	4		T135	11		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T33	30		T208	20		T209	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	9		T128	9		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	28		T218	8		T86	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	8		T127	12		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	2		T213	1		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	2		T101	14		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T127	10		T201	17		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T37	32		T55	9		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	9		T27	2		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T27	18		T35	4		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T128	4		T231	12		T194	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T35	11		T125	14		T159	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T37	8		T27	13		T69	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	8		T43	1		T204	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	3		T4	16		T55	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T171	12		T145	9		T130	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	15		T101	14		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	10		T11	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T3	3		T9	3		T102	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T44	1		T134	1		T128	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T39	2		T218	9		T212	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T126	1		T159	1		T127	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	3		T144	1		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	3		T11	2		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	1		T15	1		T127	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T101	15		T37	35		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	10		T27	3		T171	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T35	5		T36	17		T127	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T27	14		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	19		T34	1		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	2		T37	10		T69	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	1		T129	9		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	17		T31	1		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T171	13		T145	10		T130	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T2	4		T151	10		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T207	17		T224	9		T243	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16876	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T139	10		T210	1		T201	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	8		T56	2		T135	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T3	23		T9	21		T17	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T44	14		T128	12		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T218	8		T86	11		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	3		T139	26		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	2		T144	1		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	11		T129	5		T200	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	4		T15	10		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T37	15		T30	5		T55	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T27	4		T171	7		T142	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T127	9		T21	4		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T27	5		T231	12		T194	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T27	13		T34	9		T125	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	4		T36	5		T237	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T129	7		T144	6		T85	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T31	2		T55	11		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T171	10		T206	5		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T244	7		T247	2		T167	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T207	5		T224	10		T248	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T241	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T206	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T140	11		T242	1		T245	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	15		T101	14		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T134	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T3	3		T9	3		T102	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	10		T44	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	31		T31	1		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	10		T126	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T30	3		T144	1		T213	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	3		T11	2		T101	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T127	11		T201	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T37	35		T55	10		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	10		T15	1		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T27	19		T30	1		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T128	5		T231	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	1		T35	12		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T13	1		T37	10		T27	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	1		T129	9		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T2	4		T4	17		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T171	13		T145	10		T130	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T206	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T140	13		T242	12		T245	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T139	10		T210	1		T201	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T56	2		T135	11		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T3	23		T9	21		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	14		T31	8		T128	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T17	23		T31	5		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	11		T127	3		T139	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	2		T144	1		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T136	12		T129	5		T200	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T7	4		T127	10		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	15		T55	13		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	10		T27	4		T144	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T27	13		T30	5		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T231	12		T142	4		T194	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T34	9		T125	9		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	4		T27	5		T222	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T129	7		T144	6		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T31	2		T55	11		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T171	10		T85	2		T206	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21