Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20069

1

T1

20

T2

17

T5

12

auto[ADC_CTRL_FILTER_COND_OUT]

5889

1

T3

26

T4

17

T9

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20210

1

T1

20

T2

14

T5

12

auto[1]

5748

1

T2

3

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T249	14		-	-		-	-
values[0]	50	1			T128	5		T222	2		T214	2
values[1]	897	1			T12	10		T13	1		T27	26
values[2]	828	1			T13	1		T17	54		T31	3
values[3]	611	1			T11	1		T37	50		T69	1
values[4]	592	1			T2	4		T11	1		T15	11
values[5]	640	1			T14	15		T37	14		T56	7
values[6]	646	1			T2	10		T4	17		T7	5
values[7]	738	1			T11	1		T101	14		T44	15
values[8]	622	1			T2	3		T35	5		T69	16
values[9]	3445	1			T3	26		T9	24		T13	1
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1077	1			T12	10		T13	1		T27	26
values[1]	3134	1			T3	26		T9	24		T102	2
values[2]	484	1			T11	2		T13	1		T17	21
values[3]	647	1			T2	4		T15	11		T30	6
values[4]	714	1			T4	17		T7	5		T14	15
values[5]	663	1			T2	10		T101	14		T44	15
values[6]	653	1			T11	1		T18	4		T135	23
values[7]	692	1			T2	3		T27	32		T35	5
values[8]	829	1			T101	15		T55	23		T159	12
values[9]	178	1			T13	1		T31	9		T158	20
minimum	16887	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T12	1		T27	11		T30	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T13	1		T136	13		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T37	18		T31	3		T127	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1552	1			T3	26		T9	24		T102	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T69	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	1		T13	1		T17	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T15	11		T30	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	6		T34	10		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	5		T134	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T14	1		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	1		T126	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T101	1		T44	15		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T18	4		T36	1		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T135	12		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T35	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	14		T55	12		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T129	13		T218	16		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T101	1		T55	14		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T13	1		T169	8		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T31	9		T158	10		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16768	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	9		T27	15		T30	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T136	10		T38	1		T127	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T37	32		T127	12		T213	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1161	1			T17	28		T33	30		T208	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T36	16		T200	10		T205	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T17	8		T42	2		T250	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	3		T145	12		T146	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T128	9		T251	11		T252	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T138	9		T206	2		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	16		T14	14		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	9		T214	11		T254	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T101	13		T37	8		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T212	17		T21	2		T221	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	11		T82	8		T246	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	2		T35	4		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	18		T55	8		T69	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T129	15		T218	11		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T101	14		T55	9		T159	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T169	9		T255	4		T256	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T158	10		T148	1		T141	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T37	5		T69	2		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T249	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T128	1		T257	13		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T222	1		T214	1		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T12	1		T27	11		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T136	13		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	3		T127	4		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	1		T17	26		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	18		T69	1		T200	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T137	13		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	1		T11	1		T15	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	13		T31	6		T34	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T233	1		T229	1		T253	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T37	6		T56	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	1		T7	5		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T125	10		T129	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T18	4		T126	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	1		T101	1		T44	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	1		T35	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T69	1		T129	8		T144	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	1		T126	1		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1711	1			T3	26		T9	24		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T128	4		T257	7		T258	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T222	1		T214	1		T260	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	9		T27	15		T30	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T136	10		T38	1		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T127	12		T213	1		T210	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	28		T127	9		T197	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	32		T200	10		T205	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	9		T42	2		T82	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	3		T36	16		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T17	8		T128	9		T250	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T229	8		T253	4		T261	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	14		T37	8		T56	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	9		T138	9		T214	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	16		T125	14		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T212	17		T21	2		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T101	13		T35	11		T135	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	2		T35	4		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T69	15		T129	8		T22	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T129	15		T169	9		T218	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1310	1			T101	14		T27	18		T33	30
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T12	10		T27	17		T30	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T13	1		T136	11		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T37	35		T31	1		T127	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1510	1			T3	3		T9	3		T102	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T69	1		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T13	1		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	4		T15	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T31	1		T34	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T134	1		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	17		T14	15		T56	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	10		T126	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T101	14		T44	1		T37	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	3		T36	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	1		T135	12		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	3		T35	5		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	19		T55	9		T69	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T129	16		T218	12		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T101	15		T55	10		T159	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T13	1		T169	10		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T31	1		T158	11		T148	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	9		T30	2		T171	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T136	12		T38	1		T127	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	15		T31	2		T127	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1203	1			T3	23		T9	21		T17	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T200	11		T80	8		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T17	11		T144	1		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T15	10		T30	5		T36	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T31	5		T34	9		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	4		T206	9		T262	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T56	2		T218	8		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T214	11		T254	9		T236	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	14		T37	4		T125	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	1		T139	10		T212	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T135	11		T144	6		T198	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T197	10		T85	2		T204	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T27	13		T55	11		T129	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T129	12		T218	15		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T55	13		T237	14		T85	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T169	7		T255	18		T256	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T31	8		T158	9		T141	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T244	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T249	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T128	5		T257	8		T258	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T222	2		T214	2		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	10		T27	17		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	1		T136	11		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T31	1		T127	13		T213	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T13	1		T17	31		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	35		T69	1		T200	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T137	1		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	4		T11	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T17	10		T31	1		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T233	1		T229	9		T253	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	15		T37	10		T56	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	10		T7	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	17		T125	15		T129	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	3		T126	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	1		T101	14		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	3		T35	5		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T69	16		T129	9		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	1		T126	1		T129	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1688	1			T3	3		T9	3		T101	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T249	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T257	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T27	9		T30	2		T171	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T136	12		T38	1		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T31	2		T127	3		T210	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	23		T127	9		T197	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	15		T200	11		T142	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T137	12		T144	1		T42	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	10		T30	5		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T17	11		T31	5		T34	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T262	1		T162	13		T263	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	4		T56	2		T218	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	4		T214	11		T236	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T125	9		T129	5		T230	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	1		T139	10		T212	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	14		T135	11		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T197	10		T140	7		T142	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T129	7		T144	6		T198	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T129	12		T169	7		T218	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1333	1			T3	23		T9	21		T27	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21