Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22322

1

T1

20

T2

17

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3636

1

T11

1

T13

1

T101

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19970

1

T1

20

T2

10

T5

12

auto[1]

5988

1

T2

7

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T264	1		-	-		-	-
values[0]	35	1			T212	2		T265	13		T266	4
values[1]	800	1			T7	5		T11	2		T15	11
values[2]	654	1			T13	1		T101	15		T35	5
values[3]	599	1			T4	17		T37	14		T69	1
values[4]	701	1			T2	4		T11	1		T17	21
values[5]	801	1			T2	3		T13	1		T37	50
values[6]	767	1			T14	15		T44	15		T17	54
values[7]	881	1			T13	1		T27	19		T30	6
values[8]	531	1			T2	10		T12	10		T31	3
values[9]	3313	1			T3	26		T9	24		T102	2
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T7	5		T11	2		T15	11
values[1]	668	1			T13	1		T101	15		T35	5
values[2]	587	1			T2	4		T4	17		T37	14
values[3]	800	1			T2	3		T11	1		T17	21
values[4]	807	1			T13	1		T44	15		T37	50
values[5]	733	1			T14	15		T17	54		T55	20
values[6]	3007	1			T3	26		T9	24		T13	1
values[7]	566	1			T2	10		T12	10		T31	3
values[8]	802	1			T35	12		T202	1		T136	23
values[9]	128	1			T55	23		T199	1		T205	14
minimum	16927	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	5		T11	2		T15	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T134	1		T159	1		T36	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T35	1		T69	1		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T101	1		T128	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T4	1		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T141	10		T207	1		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T17	13		T27	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	1		T27	14		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T44	15		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T37	18		T30	3		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	1		T17	26		T55	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T158	10		T38	3		T144	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T3	26		T9	24		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T30	6		T31	9		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T12	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T213	1		T197	17		T42	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T151	1		T160	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	1		T202	1		T136	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T199	1		T147	8		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T55	14		T205	1		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16777	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T130	1		T268	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T101	13		T127	19		T82	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T197	13		T145	12		T212	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T35	4		T38	1		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T101	14		T128	9		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	3		T4	16		T37	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T141	8		T253	4		T174	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	2		T17	8		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T27	18		T146	2		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T200	10		T229	10		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T37	32		T30	2		T69	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	14		T17	28		T55	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	10		T85	2		T20	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1098	1			T27	13		T33	30		T208	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	12		T129	15		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	9		T12	9		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T213	1		T197	12		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T151	9		T145	9		T21	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	11		T136	10		T178	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T147	3		T269	9		T270	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T55	9		T205	13		T164	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T130	6		T268	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T266	4		T271	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T212	1		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	5		T11	2		T15	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T134	1		T159	1		T36	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	1		T38	2		T127	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T101	1		T128	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	1		T37	6		T69	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T138	1		T218	9		T204	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T17	13		T27	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	1		T27	14		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T13	1		T200	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T37	18		T69	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T44	15		T17	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	3		T158	10		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	1		T27	6		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T30	6		T31	9		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T12	1		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T138	1		T197	17		T239	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T3	26		T9	24		T102	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	1		T202	1		T55	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	1		T265	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T101	13		T127	10		T201	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T171	12		T197	13		T130	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T35	4		T38	1		T127	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T101	14		T128	9		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T4	16		T37	8		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T218	8		T204	7		T211	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T2	3		T17	8		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T27	18		T146	2		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	2		T200	10		T250	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T37	32		T69	15		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	14		T17	28		T55	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	2		T158	10		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T27	13		T128	4		T85	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	12		T129	15		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	9		T12	9		T135	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T138	9		T197	12		T272	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T33	30		T208	20		T209	36
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T35	11		T55	9		T136	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	1		T11	2		T15	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T134	1		T159	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	5		T69	1		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	1		T101	15		T128	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T4	17		T37	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T141	9		T207	1		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	3		T17	10		T27	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	1		T27	19		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T44	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T37	35		T30	3		T69	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	15		T17	31		T55	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T158	11		T38	3		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T3	3		T9	3		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T30	1		T31	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	10		T12	10		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T213	2		T197	13		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T151	10		T160	1		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T35	12		T202	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T199	1		T147	4		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T55	10		T205	14		T164	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16888	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T130	7		T268	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	4		T15	10		T34	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	5		T197	10		T204	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T18	1		T38	1		T218	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T128	12		T171	10		T218	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T37	4		T125	9		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T141	9		T239	7		T273	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T17	11		T27	4		T56	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T27	13		T231	12		T236	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	14		T137	12		T200	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T37	15		T30	2		T169	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T17	23		T55	11		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T158	9		T144	1		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T3	23		T9	21		T27	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	5		T31	8		T127	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	2		T135	11		T129	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T197	16		T42	4		T147	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T237	14		T21	2		T142	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T136	12		T139	10		T142	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T147	7		T269	14		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T55	13		T274	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T268	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T266	1		T271	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T212	2		T265	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	1		T11	2		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	1		T159	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T35	5		T38	2		T127	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T101	15		T128	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	17		T37	10		T69	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T138	1		T218	9		T204	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	4		T17	10		T27	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	1		T27	19		T146	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	3		T13	1		T200	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T37	35		T69	16		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T14	15		T44	1		T17	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T30	3		T158	11		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	1		T27	14		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T30	1		T31	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	10		T12	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T138	10		T197	13		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T3	3		T9	3		T102	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T35	12		T202	1		T55	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T266	3		T271	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	4		T15	10		T34	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	5		T171	10		T197	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	1		T127	9		T218	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T128	12		T140	9		T254	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T37	4		T18	1		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T218	8		T204	6		T211	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T17	11		T27	4		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T27	13		T231	12		T236	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T200	11		T250	14		T198	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T37	15		T230	11		T140	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T44	14		T17	23		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	2		T158	9		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	5		T80	8		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T30	5		T31	8		T127	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T31	2		T135	11		T129	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T197	16		T239	8		T275	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T3	23		T9	21		T143	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	13		T136	12		T139	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21