Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22630

1

T1

20

T2

13

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T2

4

T4

17

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19887

1

T1

20

T2

4

T4

17

auto[1]

6071

1

T2

13

T3

26

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	702	1			T2	4		T6	1		T45	2
values[0]	11	1			T134	1		T161	10		-	-
values[1]	625	1			T7	5		T34	10		T202	1
values[2]	3037	1			T2	10		T3	26		T9	24
values[3]	699	1			T14	15		T15	11		T27	19
values[4]	718	1			T12	10		T13	2		T17	21
values[5]	815	1			T11	1		T17	54		T27	7
values[6]	707	1			T4	17		T30	6		T55	23
values[7]	582	1			T11	1		T35	12		T126	1
values[8]	638	1			T101	15		T44	15		T37	14
values[9]	974	1			T2	3		T11	1		T27	32
minimum	16450	1			T1	20		T5	12		T6	153

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	693	1			T7	5		T134	1		T158	20
values[1]	2919	1			T2	10		T3	26		T9	24
values[2]	778	1			T14	15		T15	11		T69	1
values[3]	798	1			T12	10		T13	2		T17	75
values[4]	754	1			T11	1		T35	5		T144	18
values[5]	596	1			T4	17		T11	1		T30	6
values[6]	683	1			T37	14		T35	12		T137	13
values[7]	551	1			T2	3		T101	15		T44	15
values[8]	985	1			T11	1		T101	14		T37	50
values[9]	135	1			T2	4		T148	2		T180	17
minimum	17066	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T134	1		T135	12		T127	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	5		T158	10		T197	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T2	1		T3	26		T9	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T27	6		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T15	11		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T136	13		T144	2		T171	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	2		T17	26		T27	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T17	13		T31	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	1		T144	18		T42	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T39	2		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T30	6		T55	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	1		T129	6		T20	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	1		T159	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T37	6		T137	13		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T55	12		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T101	1		T44	15		T56	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	1		T101	1		T37	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T31	12		T159	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T180	17		T261	1		T276	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T2	1		T148	1		T248	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16800	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T202	1		T197	17		T83	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T135	11		T127	9		T145	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T158	10		T197	13		T85	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T2	9		T33	30		T208	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	13		T125	14		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	14		T277	6		T272	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	10		T171	5		T218	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T17	28		T27	2		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	9		T17	8		T36	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	2		T147	11		T265	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	4		T86	9		T229	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T55	9		T127	12		T212	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	16		T129	2		T20	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	11		T128	4		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	8		T138	11		T200	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	2		T55	8		T212	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T101	14		T56	4		T212	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T101	13		T37	32		T27	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T159	11		T38	1		T171	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T276	11		T255	4		T258	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T2	3		T148	1		T248	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T197	12		T161	8		T278	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	526	1			T6	1		T45	2		T46	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T2	1		T149	1		T228	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T134	1		T161	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	10		T135	12		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	5		T202	1		T197	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T2	1		T3	26		T9	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	1		T125	10		T158	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	1		T15	11		T69	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T27	6		T136	13		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	2		T128	13		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T17	13		T218	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	1		T17	26		T27	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	6		T35	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T30	6		T55	14		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	1		T129	6		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T35	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T137	13		T138	1		T200	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T55	12		T159	1		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T101	1		T44	15		T37	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	1		T11	1		T27	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T31	12		T159	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16335	1			T1	20		T5	12		T6	153
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T101	13		T37	32		T127	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T2	3		T228	2		T182	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T161	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	11		T82	8		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T197	25		T221	6		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T2	9		T33	30		T208	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T125	14		T158	10		T85	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	14		T194	5		T179	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	13		T136	10		T171	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T128	9		T151	9		T129	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	9		T17	8		T218	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T17	28		T27	2		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T35	4		T36	16		T130	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T55	9		T127	12		T212	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	16		T129	2		T86	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T35	11		T128	4		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	11		T200	10		T146	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	8		T212	1		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T101	14		T37	8		T56	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	2		T27	18		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T159	11		T38	1		T171	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T134	1		T135	12		T127	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T158	11		T197	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T2	10		T3	3		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	1		T27	14		T125	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	15		T15	1		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T136	11		T144	1		T171	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	2		T17	31		T27	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	10		T17	10		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T144	1		T42	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	5		T39	2		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T30	1		T55	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	17		T129	3		T20	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T35	12		T159	1		T128	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	10		T137	1		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	3		T55	9		T212	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T101	15		T44	1		T56	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T11	1		T101	14		T37	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T31	2		T159	12		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T180	1		T261	1		T276	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T2	4		T148	2		T248	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16937	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T202	1		T197	13		T83	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T135	11		T127	9		T142	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	4		T158	9		T197	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T3	23		T9	21		T143	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	5		T125	9		T139	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	10		T18	1		T162	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T136	12		T144	1		T171	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T17	23		T27	4		T128	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T17	11		T31	5		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T144	17		T42	4		T237	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T86	11		T239	7		T279	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	5		T55	13		T127	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T129	5		T20	13		T214	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T129	7		T21	2		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	4		T137	12		T200	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	11		T21	2		T147	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T44	14		T56	2		T212	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	15		T27	13		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T31	10		T38	1		T36	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T180	16		T276	11		T280	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T248	13		T182	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T34	9		T281	4		T282	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T197	16		T283	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	537	1			T6	1		T45	2		T46	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T2	4		T149	1		T228	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T134	1		T161	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T34	1		T135	12		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T202	1		T197	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T2	10		T3	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	1		T125	15		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	15		T15	1		T69	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T27	14		T136	11		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	2		T128	10		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	10		T17	10		T218	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	1		T17	31		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	1		T35	5		T36	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T30	1		T55	10		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	17		T129	3		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T35	12		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	1		T138	12		T200	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	9		T159	1		T212	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T101	15		T44	1		T37	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	3		T11	1		T27	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T31	2		T159	12		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16450	1			T1	20		T5	12		T6	153
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T37	15		T127	10		T139	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T228	4		T182	12		T196	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	9		T135	11		T142	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T7	4		T197	26		T284	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T3	23		T9	21		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T125	9		T158	9		T139	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	10		T18	1		T194	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T27	5		T136	12		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T128	12		T129	12		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T17	11		T218	23		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	23		T27	4		T144	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T31	5		T239	7		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	5		T55	13		T127	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T129	5		T86	11		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T129	7		T144	6		T21	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T137	12		T200	11		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T55	11		T211	10		T141	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T44	14		T37	4		T56	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T27	13		T30	2		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T31	10		T38	1		T36	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21