Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22466

1

T1

20

T2

17

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3492

1

T11

2

T12

10

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20024

1

T1

20

T2

4

T4

17

auto[1]

5934

1

T2

13

T3

26

T9

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T35	12		T285	15		T183	2
values[0]	72	1			T286	14		T287	10		T255	7
values[1]	690	1			T15	11		T126	1		T36	6
values[2]	737	1			T2	4		T101	15		T37	50
values[3]	443	1			T13	1		T202	1		T213	2
values[4]	661	1			T2	3		T4	17		T11	2
values[5]	2961	1			T2	10		T3	26		T7	5
values[6]	743	1			T17	21		T34	10		T56	7
values[7]	657	1			T12	10		T135	23		T36	1
values[8]	833	1			T13	1		T14	15		T44	15
values[9]	1243	1			T11	1		T101	14		T37	14
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	925	1			T15	11		T101	15		T69	16
values[1]	640	1			T2	4		T37	50		T158	20
values[2]	501	1			T4	17		T11	1		T13	1
values[3]	3045	1			T2	3		T3	26		T9	24
values[4]	714	1			T2	10		T7	5		T30	5
values[5]	658	1			T12	10		T17	21		T31	6
values[6]	753	1			T44	15		T27	32		T55	20
values[7]	847	1			T13	1		T17	54		T27	7
values[8]	796	1			T11	1		T14	15		T101	14
values[9]	192	1			T136	23		T159	1		T80	9
minimum	16887	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	11		T69	1		T171	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T101	1		T126	1		T36	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T37	18		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T158	10		T129	13		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T4	1		T213	1		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T13	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T2	1		T3	26		T9	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T125	10		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T7	5		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	3		T134	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T17	13		T31	6		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T34	10		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T55	12		T129	6		T144	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T44	15		T27	14		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T27	5		T69	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	1		T17	26		T30	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T101	1		T37	6		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T14	1		T18	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T136	13		T159	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T80	9		T233	1		T289	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16761	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T69	15		T171	17		T146	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T101	14		T212	1		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	3		T37	32		T127	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T158	10		T129	15		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	16		T213	1		T205	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T210	1		T254	3		T278	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1108	1			T2	2		T27	13		T33	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T125	14		T159	11		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	9		T21	3		T224	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T30	2		T36	16		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	8		T56	4		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	9		T35	4		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	8		T129	2		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	18		T135	11		T82	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	2		T128	4		T229	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	28		T128	9		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T101	13		T37	8		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	14		T38	1		T218	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T136	10		T290	13		T291	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T289	29		T292	2		T293	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	5		T69	2		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T35	1		T285	15		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T183	1		T294	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T287	4		T235	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T286	1		T255	7		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	11		T171	19		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T126	1		T36	6		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T37	18		T69	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T101	1		T158	10		T250	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T213	1		T145	1		T204	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T202	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	1		T4	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T13	1		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T2	1		T3	26		T7	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	3		T35	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T17	13		T56	3		T129	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	10		T36	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T129	6		T138	1		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T135	12		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T27	5		T55	12		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T14	1		T44	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T101	1		T37	6		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T11	1		T17	26		T30	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T35	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T183	1		T294	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T287	6		T235	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T286	13		T295	6		T296	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T171	17		T146	2		T179	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T129	15		T212	1		T194	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	3		T37	32		T69	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T101	14		T158	10		T250	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T213	1		T145	9		T204	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T210	1		T254	5		T278	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	2		T4	16		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T125	14		T159	11		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T2	9		T27	13		T33	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	2		T35	4		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T17	8		T56	4		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T36	16		T151	9		T197	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	2		T138	9		T197	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	9		T135	11		T212	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T27	2		T55	8		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	14		T27	18		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T101	13		T37	8		T55	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T17	28		T38	1		T138	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	1		T69	16		T171	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T101	15		T126	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	4		T37	35		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T158	11		T129	16		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	17		T213	2		T205	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T13	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T2	3		T3	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T125	15		T159	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	10		T7	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T30	3		T134	1		T36	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	10		T31	1		T56	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	10		T34	1		T35	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T55	9		T129	3		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	1		T27	19		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T27	3		T69	1		T128	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	1		T17	31		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T101	14		T37	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	1		T14	15		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T136	11		T159	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T80	1		T233	1		T289	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16887	1			T1	20		T5	12		T6	154
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	10		T171	17		T225	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T36	5		T140	7		T194	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	15		T127	10		T169	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T158	9		T129	12		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T140	2		T224	4		T225	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	12		T210	1		T254	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T3	23		T9	21		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	9		T237	14		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	4		T139	5		T21	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	2		T197	16		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	11		T31	5		T56	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	9		T139	10		T42	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T55	11		T129	5		T144	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	14		T27	13		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T27	4		T144	17		T201	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	23		T30	5		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	4		T31	2		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T18	1		T38	1		T218	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T136	12		T25	6		T290	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T80	8		T289	24		T292	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T35	12		T285	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T183	2		T294	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T287	7		T235	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T286	14		T255	1		T295	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	1		T171	19		T146	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T126	1		T36	1		T129	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	4		T37	35		T69	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T101	15		T158	11		T250	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T213	2		T145	10		T204	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T202	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	3		T4	17		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	1		T13	1		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T2	10		T3	3		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	3		T35	5		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T17	10		T56	5		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	1		T36	17		T151	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	3		T138	10		T197	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	10		T135	12		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T27	3		T55	9		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	1		T14	15		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T101	14		T37	10		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T11	1		T17	31		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T285	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T294	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T287	3		T235	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T255	6		T296	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	10		T171	17		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	5		T129	12		T194	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	15		T127	10		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T158	9		T250	14		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T204	13		T206	5		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T210	1		T254	2		T252	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T127	9		T198	13		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T125	9		T137	12		T237	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T3	23		T7	4		T9	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	2		T147	12		T297	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T17	11		T56	2		T129	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T34	9		T197	16		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T129	5		T197	10		T200	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T135	11		T212	15		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T27	4		T55	11		T144	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T44	14		T27	13		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T37	4		T31	2		T55	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T17	23		T30	5		T18	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21