Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22129

1

T1

20

T2

7

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3829

1

T2

10

T4

17

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19931

1

T1

20

T2

3

T5

12

auto[1]

6027

1

T2

14

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T298	11		-	-		-	-
values[0]	50	1			T248	10		T299	1		T300	2
values[1]	680	1			T15	11		T30	11		T35	12
values[2]	536	1			T2	10		T17	54		T126	1
values[3]	603	1			T12	10		T37	14		T55	20
values[4]	804	1			T2	4		T11	1		T101	14
values[5]	2794	1			T3	26		T9	24		T102	2
values[6]	793	1			T4	17		T27	39		T69	17
values[7]	709	1			T7	5		T11	1		T13	2
values[8]	745	1			T11	1		T37	50		T31	6
values[9]	1358	1			T2	3		T13	1		T14	15
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T17	54		T30	11		T35	12
values[1]	666	1			T2	10		T12	10		T15	11
values[2]	518	1			T11	1		T27	19		T136	23
values[3]	2974	1			T2	4		T3	26		T9	24
values[4]	612	1			T27	7		T69	1		T18	4
values[5]	742	1			T4	17		T27	32		T69	16
values[6]	731	1			T11	1		T13	2		T44	15
values[7]	698	1			T7	5		T34	10		T135	23
values[8]	949	1			T2	3		T11	1		T13	1
values[9]	317	1			T158	20		T229	9		T211	33
minimum	16913	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T30	6		T35	1		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	26		T30	3		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T15	11		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T37	6		T222	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T27	6		T136	13		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T11	1		T171	11		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T2	1		T3	26		T9	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T101	1		T31	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T27	5		T69	1		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	3		T39	2		T230	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T69	1		T126	1		T169	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	1		T27	14		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	2		T128	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	1		T44	15		T31	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	10		T151	1		T139	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	5		T135	12		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T101	1		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T11	1		T13	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T229	1		T288	1		T240	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T158	10		T211	16		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T223	14		T301	1		T269	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T35	11		T212	1		T204	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	28		T30	2		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	9		T130	9		T206	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	9		T37	8		T222	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T27	13		T136	10		T194	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T171	12		T138	11		T146	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T2	3		T33	30		T208	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T101	13		T55	8		T125	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T27	2		T127	10		T128	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T230	11		T161	9		T302	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T69	15		T169	9		T86	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	16		T27	18		T218	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T128	4		T145	9		T204	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T55	9		T85	10		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T151	9		T212	1		T82	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T135	11		T38	1		T129	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	2		T101	14		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T14	14		T37	32		T17	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T229	8		T240	12		T290	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T158	10		T211	17		T161	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T223	11		T269	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T298	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T300	1		T283	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T248	5		T299	1		T303	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T15	11		T30	6		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T30	3		T202	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T126	1		T36	1		T144	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	1		T17	26		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T136	13		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	6		T55	12		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	1		T27	6		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T101	1		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T3	26		T9	24		T102	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	3		T134	1		T230	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T27	5		T69	2		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T4	1		T27	14		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	2		T145	1		T86	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	5		T11	1		T44	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	10		T151	1		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	1		T37	18		T31	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	1		T101	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T13	1		T14	1		T17	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T298	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T300	1		T283	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	5		T303	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T35	11		T204	13		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T30	2		T159	11		T56	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T212	1		T130	9		T206	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	9		T17	28		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	9		T136	10		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T37	8		T55	8		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	3		T27	13		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T101	13		T125	14		T127	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T33	30		T208	20		T209	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T230	11		T205	13		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	2		T69	15		T128	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T4	16		T27	18		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T145	9		T86	9		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T55	9		T82	8		T85	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T151	9		T212	1		T204	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T37	32		T38	1		T129	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	2		T101	14		T35	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T14	14		T17	8		T158	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T30	1		T35	12		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	31		T30	3		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	10		T15	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	10		T37	10		T222	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	14		T136	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	1		T171	13		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T2	4		T3	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T101	14		T31	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	3		T69	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T38	3		T39	2		T230	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T69	16		T126	1		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T4	17		T27	19		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	2		T128	5		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	1		T44	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T34	1		T151	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	1		T135	12		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	3		T101	15		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T11	1		T13	1		T14	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T229	9		T288	1		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T158	11		T211	18		T161	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T223	12		T301	1		T269	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T30	5		T139	21		T204	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	23		T30	2		T56	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	10		T144	6		T206	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T37	4		T222	12		T273	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T27	5		T136	12		T194	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T171	10		T43	1		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T3	23		T9	21		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	2		T55	11		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T27	4		T18	1		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T230	11		T142	12		T239	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T169	7		T86	11		T304	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	13		T137	12		T218	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T204	6		T219	10		T182	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T44	14		T31	5		T55	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	9		T139	5		T147	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	4		T135	11		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	8		T144	1		T201	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T37	15		T17	11		T36	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T240	13		T290	22		T305	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T158	9		T211	15		T254	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T223	13		T269	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T298	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T300	2		T283	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T248	6		T299	1		T303	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	1		T30	1		T35	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	3		T202	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T126	1		T36	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	10		T17	31		T229	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	10		T136	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	10		T55	9		T171	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	4		T27	14		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T101	14		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T3	3		T9	3		T102	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T31	1		T134	1		T230	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	3		T69	17		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T4	17		T27	19		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	2		T145	10		T86	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T11	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	1		T151	10		T212	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T11	1		T37	35		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T2	3		T101	15		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	498	1			T13	1		T14	15		T17	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T298	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T283	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T248	4		T303	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	10		T30	5		T139	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T30	2		T56	2		T129	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T144	6		T206	5		T297	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T17	23		T273	11		T275	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	12		T206	9		T194	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T37	4		T55	11		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T27	5		T198	13		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T125	9		T127	9		T22	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T3	23		T9	21		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T31	2		T230	11		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T27	4		T128	12		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T27	13		T218	8		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T86	11		T219	10		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	4		T44	14		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T34	9		T204	6		T201	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T37	15		T31	5		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T31	8		T144	1		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T17	11		T158	9		T135	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21