Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25958

1

T1

20

T2

17

T3

26

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22130

1

T1

20

T2

7

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3828

1

T2

10

T4

17

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19923

1

T1

20

T2

3

T5

12

auto[1]

6035

1

T2

14

T3

26

T4

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21685

1

T1

20

T2

3

T3

26

auto[1]

4273

1

T2

14

T4

16

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	301	1			T101	15		T41	1		T197	29
values[0]	12	1			T303	12		-	-		-	-
values[1]	709	1			T17	54		T30	11		T35	12
values[2]	527	1			T2	10		T15	11		T126	1
values[3]	577	1			T12	10		T37	14		T55	20
values[4]	787	1			T2	4		T11	1		T101	14
values[5]	2870	1			T3	26		T9	24		T102	2
values[6]	801	1			T4	17		T27	39		T69	17
values[7]	600	1			T7	5		T11	1		T13	2
values[8]	781	1			T31	6		T34	10		T38	3
values[9]	1118	1			T2	3		T11	1		T13	1
minimum	16875	1			T1	20		T5	12		T6	154

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	564	1			T17	54		T30	6		T35	12
values[1]	584	1			T2	10		T12	10		T15	11
values[2]	585	1			T11	1		T27	19		T55	20
values[3]	2933	1			T2	4		T3	26		T9	24
values[4]	634	1			T27	7		T69	17		T18	4
values[5]	792	1			T4	17		T27	32		T126	1
values[6]	679	1			T7	5		T11	1		T13	2
values[7]	748	1			T34	10		T135	23		T38	3
values[8]	993	1			T2	3		T11	1		T14	15
values[9]	235	1			T13	1		T101	15		T158	20
minimum	17211	1			T1	20		T5	12		T6	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

3878

1

T3

23

T7

4

T9

21

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	6		T35	1		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T17	26		T202	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T15	11		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	1		T37	6		T306	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T27	6		T136	13		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	1		T55	12		T171	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T2	1		T3	26		T9	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T101	1		T31	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	5		T69	2		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	3		T39	2		T230	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T126	1		T128	1		T169	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	1		T27	14		T218	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	2		T204	7		T219	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	5		T11	1		T44	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	10		T151	1		T139	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	12		T38	2		T129	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T31	9		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T11	1		T14	1		T37	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T101	1		T229	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	1		T158	10		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16846	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T30	3		T132	1		T129	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T35	11		T140	9		T297	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	28		T159	11		T56	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	9		T212	1		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T2	9		T37	8		T222	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	13		T136	10		T206	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T55	8		T171	12		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T2	3		T33	30		T208	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T101	13		T125	14		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T27	2		T69	15		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T230	11		T161	9		T302	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T128	4		T169	9		T86	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T4	16		T27	18		T218	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T204	7		T219	9		T278	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	9		T85	10		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T151	9		T145	9		T212	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T135	11		T38	1		T129	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	2		T35	4		T36	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T14	14		T37	32		T17	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T101	14		T229	8		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T158	10		T197	12		T211	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	5		T69	2		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T30	2		T129	8		T286	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T101	1		T229	1		T236	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T41	1		T197	17		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T303	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T30	6		T35	1		T139	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	26		T30	3		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	11		T126	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T2	1		T229	1		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T136	13		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	6		T55	12		T171	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	1		T27	6		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T101	1		T125	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T3	26		T9	24		T102	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T31	3		T134	1		T230	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	5		T69	2		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	1		T27	14		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	2		T86	12		T204	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	5		T11	1		T44	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	10		T151	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T31	6		T38	2		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T31	9		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T11	1		T13	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T101	14		T229	8		T215	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T197	12		T145	12		T211	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T303	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	11		T140	9		T211	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T17	28		T30	2		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T212	1		T130	9		T204	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	9		T229	10		T179	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	9		T136	10		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	8		T55	8		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	3		T27	13		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T101	13		T125	14		T127	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T33	30		T208	20		T209	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T230	11		T205	13		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T27	2		T69	15		T128	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T4	16		T27	18		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T86	9		T204	7		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T55	9		T85	10		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T151	9		T145	9		T212	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T38	1		T129	15		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	2		T35	4		T36	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T14	14		T37	32		T17	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	5		T69	2		T18	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	1		T35	12		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	31		T202	1		T159	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	10		T15	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	10		T37	10		T306	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T27	14		T136	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T55	9		T171	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T2	4		T3	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T101	14		T31	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	3		T69	17		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T38	3		T39	2		T230	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T126	1		T128	5		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T4	17		T27	19		T218	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	2		T204	8		T219	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	1		T11	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	1		T151	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T135	12		T38	2		T129	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	3		T31	1		T35	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T11	1		T14	15		T37	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T101	15		T229	9		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T13	1		T158	11		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16987	1			T1	20		T5	12		T6	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T30	3		T132	1		T129	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T30	5		T139	21		T140	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T17	23		T56	2		T273	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	10		T144	6		T204	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T37	4		T222	12		T162	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T27	5		T136	12		T206	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T55	11		T171	10		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T3	23		T9	21		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T31	2		T125	9		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T27	4		T18	1		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T230	11		T142	12		T239	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T169	7		T86	11		T304	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T27	13		T218	8		T139	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T204	6		T219	10		T182	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	4		T44	14		T31	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	9		T139	5		T147	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T135	11		T38	1		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T31	8		T144	1		T201	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T37	15		T17	11		T36	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T240	13		T285	14		T183	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T158	9		T197	16		T211	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T211	10		T273	12		T307	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T30	2		T129	7		T251	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T101	15		T229	9		T236	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	1		T197	13		T145	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T303	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	1		T35	12		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	31		T30	3		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	1		T126	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	10		T229	11		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	10		T136	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	10		T55	9		T171	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	4		T27	14		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	1		T101	14		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T3	3		T9	3		T102	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	1		T134	1		T230	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T27	3		T69	17		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T4	17		T27	19		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	2		T86	10		T204	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	1		T11	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	1		T151	10		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T31	1		T38	2		T129	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	3		T31	1		T35	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T11	1		T13	1		T14	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16875	1			T1	20		T5	12		T6	154
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T236	5		T215	9		T240	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T197	16		T211	15		T308	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T303	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	5		T139	21		T140	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T17	23		T30	2		T56	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	10		T144	6		T204	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T273	11		T162	14		T290	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	12		T206	9		T194	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T37	4		T55	11		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T27	5		T198	13		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T125	9		T127	9		T210	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T3	23		T9	21		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	2		T230	11		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T27	4		T128	12		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	13		T218	8		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T86	11		T204	6		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	4		T44	14		T55	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T34	9		T147	7		T214	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T31	5		T38	1		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T31	8		T144	1		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T37	15		T17	11		T158	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22080

1

T1

20

T2

17

T3

3

auto[1]

auto[0]

3878

1

T3

23

T7

4

T9

21