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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.83 98.33 90.99


Total test records in report: 919
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T797 /workspace/coverage/default/46.adc_ctrl_poweron_counter.4132347530 May 16 02:13:40 PM PDT 24 May 16 02:13:49 PM PDT 24 5179621899 ps
T798 /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3845642333 May 16 02:13:47 PM PDT 24 May 16 02:15:37 PM PDT 24 330968480259 ps
T799 /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3441932756 May 16 02:07:56 PM PDT 24 May 16 02:08:41 PM PDT 24 211277405477 ps
T800 /workspace/coverage/default/4.adc_ctrl_poweron_counter.2843075763 May 16 02:05:46 PM PDT 24 May 16 02:05:53 PM PDT 24 3062593634 ps
T801 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3190711349 May 16 02:39:54 PM PDT 24 May 16 02:39:59 PM PDT 24 478762234 ps
T802 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4124125757 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 565220716 ps
T803 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.614751616 May 16 02:39:37 PM PDT 24 May 16 02:39:42 PM PDT 24 313340417 ps
T61 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2587112538 May 16 02:39:37 PM PDT 24 May 16 02:39:43 PM PDT 24 524981342 ps
T804 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3261186284 May 16 02:39:18 PM PDT 24 May 16 02:39:20 PM PDT 24 422386713 ps
T103 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.883750193 May 16 02:39:20 PM PDT 24 May 16 02:39:29 PM PDT 24 850530339 ps
T52 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3088661956 May 16 02:39:20 PM PDT 24 May 16 02:39:38 PM PDT 24 4383712180 ps
T805 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2370321776 May 16 02:39:45 PM PDT 24 May 16 02:39:52 PM PDT 24 474269321 ps
T62 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2294661465 May 16 02:39:18 PM PDT 24 May 16 02:39:22 PM PDT 24 532034435 ps
T806 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2379725038 May 16 02:39:57 PM PDT 24 May 16 02:40:05 PM PDT 24 443063260 ps
T57 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3897238604 May 16 02:39:20 PM PDT 24 May 16 02:39:35 PM PDT 24 4024503497 ps
T67 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2896122605 May 16 02:39:30 PM PDT 24 May 16 02:39:38 PM PDT 24 488944123 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.771769075 May 16 02:39:23 PM PDT 24 May 16 02:39:28 PM PDT 24 418426003 ps
T53 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2221352016 May 16 02:39:08 PM PDT 24 May 16 02:39:17 PM PDT 24 2388151917 ps
T54 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1898256310 May 16 02:39:29 PM PDT 24 May 16 02:39:44 PM PDT 24 3811945611 ps
T807 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2403641656 May 16 02:39:53 PM PDT 24 May 16 02:39:57 PM PDT 24 534014638 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2292783578 May 16 02:39:18 PM PDT 24 May 16 02:39:27 PM PDT 24 2179525923 ps
T808 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.219967768 May 16 02:39:19 PM PDT 24 May 16 02:39:24 PM PDT 24 339886859 ps
T809 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3974720785 May 16 02:39:12 PM PDT 24 May 16 02:39:16 PM PDT 24 285236879 ps
T58 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.925783143 May 16 02:39:10 PM PDT 24 May 16 02:39:26 PM PDT 24 4398534539 ps
T119 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1347238624 May 16 02:39:38 PM PDT 24 May 16 02:39:45 PM PDT 24 2517710115 ps
T120 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3799070712 May 16 02:39:37 PM PDT 24 May 16 02:39:42 PM PDT 24 540723334 ps
T810 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1728679544 May 16 02:39:46 PM PDT 24 May 16 02:39:52 PM PDT 24 419447735 ps
T811 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3595822874 May 16 02:39:44 PM PDT 24 May 16 02:39:50 PM PDT 24 496618707 ps
T812 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3918905665 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 501854413 ps
T121 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3684321209 May 16 02:39:12 PM PDT 24 May 16 02:39:29 PM PDT 24 3841095405 ps
T124 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2256659323 May 16 02:39:09 PM PDT 24 May 16 02:39:14 PM PDT 24 789150432 ps
T63 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1408660888 May 16 02:39:22 PM PDT 24 May 16 02:39:33 PM PDT 24 4392931769 ps
T122 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.959060971 May 16 02:39:37 PM PDT 24 May 16 02:39:49 PM PDT 24 2112833999 ps
T813 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3319177002 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 300489374 ps
T814 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2908788398 May 16 02:39:44 PM PDT 24 May 16 02:39:48 PM PDT 24 337711370 ps
T104 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2716371177 May 16 02:39:28 PM PDT 24 May 16 02:39:34 PM PDT 24 430071705 ps
T815 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1751295688 May 16 02:39:46 PM PDT 24 May 16 02:39:52 PM PDT 24 486263018 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1538889100 May 16 02:39:20 PM PDT 24 May 16 02:39:25 PM PDT 24 443070926 ps
T816 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2636967849 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 282164140 ps
T817 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1164280734 May 16 02:39:19 PM PDT 24 May 16 02:39:24 PM PDT 24 483153540 ps
T818 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3359890969 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 2368729766 ps
T105 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1341260980 May 16 02:39:10 PM PDT 24 May 16 02:39:15 PM PDT 24 532067386 ps
T819 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3611039942 May 16 02:39:44 PM PDT 24 May 16 02:39:49 PM PDT 24 424539090 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3604847269 May 16 02:39:37 PM PDT 24 May 16 02:39:42 PM PDT 24 367941938 ps
T821 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.278093433 May 16 02:39:55 PM PDT 24 May 16 02:40:01 PM PDT 24 399429357 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1448840631 May 16 02:39:20 PM PDT 24 May 16 02:39:38 PM PDT 24 4014201968 ps
T68 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.713194184 May 16 02:39:12 PM PDT 24 May 16 02:39:17 PM PDT 24 590851429 ps
T823 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3520385919 May 16 02:39:44 PM PDT 24 May 16 02:39:49 PM PDT 24 393117868 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1933122100 May 16 02:39:20 PM PDT 24 May 16 02:39:39 PM PDT 24 4313179456 ps
T89 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.641657597 May 16 02:39:09 PM PDT 24 May 16 02:39:15 PM PDT 24 577728167 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1844026584 May 16 02:39:11 PM PDT 24 May 16 02:39:16 PM PDT 24 439669394 ps
T59 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.432817840 May 16 02:39:12 PM PDT 24 May 16 02:39:19 PM PDT 24 4296739970 ps
T75 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1107105626 May 16 02:39:31 PM PDT 24 May 16 02:39:40 PM PDT 24 3991763161 ps
T826 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1221793436 May 16 02:39:23 PM PDT 24 May 16 02:39:34 PM PDT 24 4657116300 ps
T827 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3637397777 May 16 02:39:23 PM PDT 24 May 16 02:39:33 PM PDT 24 2273996104 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3904148308 May 16 02:39:30 PM PDT 24 May 16 02:39:36 PM PDT 24 452151577 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1536548206 May 16 02:39:11 PM PDT 24 May 16 02:41:12 PM PDT 24 27397975917 ps
T829 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1146246396 May 16 02:39:24 PM PDT 24 May 16 02:39:30 PM PDT 24 375015330 ps
T830 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2967166155 May 16 02:39:58 PM PDT 24 May 16 02:40:05 PM PDT 24 316569248 ps
T99 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.882077152 May 16 02:39:22 PM PDT 24 May 16 02:39:28 PM PDT 24 354444052 ps
T831 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.324106787 May 16 02:39:27 PM PDT 24 May 16 02:39:33 PM PDT 24 337127718 ps
T73 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.888393074 May 16 02:39:29 PM PDT 24 May 16 02:39:38 PM PDT 24 717492401 ps
T832 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1074308716 May 16 02:39:25 PM PDT 24 May 16 02:39:30 PM PDT 24 413412747 ps
T72 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.99873188 May 16 02:39:23 PM PDT 24 May 16 02:39:39 PM PDT 24 4225992882 ps
T100 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2210690239 May 16 02:39:19 PM PDT 24 May 16 02:39:31 PM PDT 24 4791824910 ps
T833 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4164965040 May 16 02:39:44 PM PDT 24 May 16 02:39:49 PM PDT 24 729413375 ps
T74 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.799266274 May 16 02:39:09 PM PDT 24 May 16 02:39:16 PM PDT 24 908884351 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.778013737 May 16 02:39:20 PM PDT 24 May 16 02:39:26 PM PDT 24 541282794 ps
T835 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1096220102 May 16 02:39:47 PM PDT 24 May 16 02:39:53 PM PDT 24 338978068 ps
T836 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2897192218 May 16 02:39:20 PM PDT 24 May 16 02:39:27 PM PDT 24 576512247 ps
T107 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4066256395 May 16 02:39:19 PM PDT 24 May 16 02:39:28 PM PDT 24 1441477453 ps
T108 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3131073552 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 449825996 ps
T837 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2367892630 May 16 02:39:31 PM PDT 24 May 16 02:39:37 PM PDT 24 392091143 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2123688276 May 16 02:39:24 PM PDT 24 May 16 02:39:30 PM PDT 24 380039165 ps
T109 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2819114536 May 16 02:39:22 PM PDT 24 May 16 02:39:55 PM PDT 24 28086408906 ps
T839 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1776599095 May 16 02:39:47 PM PDT 24 May 16 02:39:53 PM PDT 24 338837832 ps
T840 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1056913723 May 16 02:39:20 PM PDT 24 May 16 02:39:26 PM PDT 24 437431068 ps
T342 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2811146256 May 16 02:39:46 PM PDT 24 May 16 02:39:57 PM PDT 24 7891693137 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2581514607 May 16 02:39:35 PM PDT 24 May 16 02:39:41 PM PDT 24 4607285964 ps
T110 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3900704429 May 16 02:39:27 PM PDT 24 May 16 02:39:34 PM PDT 24 467652251 ps
T842 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2988050929 May 16 02:39:44 PM PDT 24 May 16 02:39:50 PM PDT 24 600791553 ps
T843 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.960332934 May 16 02:39:56 PM PDT 24 May 16 02:40:04 PM PDT 24 513347493 ps
T111 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1626379047 May 16 02:39:36 PM PDT 24 May 16 02:39:41 PM PDT 24 375449308 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1279706166 May 16 02:39:26 PM PDT 24 May 16 02:39:33 PM PDT 24 470734194 ps
T112 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1899560491 May 16 02:39:19 PM PDT 24 May 16 02:39:24 PM PDT 24 450590949 ps
T845 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1297109471 May 16 02:39:19 PM PDT 24 May 16 02:39:23 PM PDT 24 382935261 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1742724916 May 16 02:39:09 PM PDT 24 May 16 02:39:49 PM PDT 24 26226785947 ps
T847 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.909971476 May 16 02:39:25 PM PDT 24 May 16 02:39:30 PM PDT 24 807183287 ps
T848 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.709095782 May 16 02:39:18 PM PDT 24 May 16 02:39:21 PM PDT 24 454276420 ps
T849 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1256427322 May 16 02:39:45 PM PDT 24 May 16 02:40:01 PM PDT 24 4488465708 ps
T343 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2548111162 May 16 02:39:45 PM PDT 24 May 16 02:39:57 PM PDT 24 4471563196 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.24875816 May 16 02:39:11 PM PDT 24 May 16 02:39:16 PM PDT 24 487118498 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.148407109 May 16 02:39:20 PM PDT 24 May 16 02:39:27 PM PDT 24 827809207 ps
T851 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1799570157 May 16 02:39:18 PM PDT 24 May 16 02:39:22 PM PDT 24 513631027 ps
T852 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1369362556 May 16 02:39:22 PM PDT 24 May 16 02:39:26 PM PDT 24 653216709 ps
T344 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3693048138 May 16 02:39:21 PM PDT 24 May 16 02:39:32 PM PDT 24 8733411503 ps
T853 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3019961567 May 16 02:39:46 PM PDT 24 May 16 02:39:51 PM PDT 24 523834036 ps
T854 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.953335379 May 16 02:39:30 PM PDT 24 May 16 02:39:39 PM PDT 24 8844265111 ps
T855 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1883465504 May 16 02:39:28 PM PDT 24 May 16 02:39:35 PM PDT 24 436484315 ps
T856 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.116332628 May 16 02:39:47 PM PDT 24 May 16 02:39:54 PM PDT 24 1102669969 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1468780294 May 16 02:39:21 PM PDT 24 May 16 02:39:28 PM PDT 24 4685846305 ps
T858 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1982239342 May 16 02:39:43 PM PDT 24 May 16 02:39:48 PM PDT 24 419789605 ps
T345 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3333170991 May 16 02:39:39 PM PDT 24 May 16 02:39:55 PM PDT 24 4472415096 ps
T859 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3358849673 May 16 02:39:43 PM PDT 24 May 16 02:39:48 PM PDT 24 478508457 ps
T860 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1019392993 May 16 02:39:20 PM PDT 24 May 16 02:39:26 PM PDT 24 459577478 ps
T861 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3757545499 May 16 02:39:37 PM PDT 24 May 16 02:39:42 PM PDT 24 605090304 ps
T862 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.444292318 May 16 02:39:20 PM PDT 24 May 16 02:39:29 PM PDT 24 4984332098 ps
T863 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1123458189 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 442273617 ps
T864 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3637781807 May 16 02:39:45 PM PDT 24 May 16 02:39:49 PM PDT 24 527013380 ps
T865 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2058976765 May 16 02:39:44 PM PDT 24 May 16 02:40:03 PM PDT 24 4223394685 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2496669469 May 16 02:39:22 PM PDT 24 May 16 02:39:42 PM PDT 24 27263662706 ps
T867 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.279901361 May 16 02:39:46 PM PDT 24 May 16 02:39:52 PM PDT 24 492149685 ps
T868 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.970593014 May 16 02:39:46 PM PDT 24 May 16 02:39:57 PM PDT 24 3847914275 ps
T869 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1634357707 May 16 02:39:38 PM PDT 24 May 16 02:39:44 PM PDT 24 570569698 ps
T870 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3462833392 May 16 02:39:21 PM PDT 24 May 16 02:39:32 PM PDT 24 8257493498 ps
T871 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3862704401 May 16 02:39:19 PM PDT 24 May 16 02:39:25 PM PDT 24 502302234 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.563333645 May 16 02:39:21 PM PDT 24 May 16 02:39:25 PM PDT 24 360017710 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4209948185 May 16 02:39:43 PM PDT 24 May 16 02:39:50 PM PDT 24 764823350 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.359635217 May 16 02:39:20 PM PDT 24 May 16 02:39:30 PM PDT 24 1054819054 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.829802294 May 16 02:39:30 PM PDT 24 May 16 02:39:37 PM PDT 24 2263919277 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1521084443 May 16 02:39:43 PM PDT 24 May 16 02:39:48 PM PDT 24 484908054 ps
T876 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1558145205 May 16 02:39:30 PM PDT 24 May 16 02:39:36 PM PDT 24 443958385 ps
T877 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.791933415 May 16 02:39:44 PM PDT 24 May 16 02:39:54 PM PDT 24 2599319505 ps
T878 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1434848971 May 16 02:39:55 PM PDT 24 May 16 02:40:01 PM PDT 24 322059690 ps
T879 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.30920521 May 16 02:39:19 PM PDT 24 May 16 02:39:34 PM PDT 24 4684677285 ps
T880 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1986103182 May 16 02:39:22 PM PDT 24 May 16 02:39:28 PM PDT 24 406651447 ps
T76 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1605003565 May 16 02:39:44 PM PDT 24 May 16 02:39:52 PM PDT 24 4586481624 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2501285645 May 16 02:39:10 PM PDT 24 May 16 02:39:17 PM PDT 24 1104399534 ps
T115 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4172319285 May 16 02:39:19 PM PDT 24 May 16 02:39:25 PM PDT 24 433459426 ps
T882 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4184709341 May 16 02:39:20 PM PDT 24 May 16 02:39:24 PM PDT 24 401132863 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1243986817 May 16 02:39:12 PM PDT 24 May 16 02:39:17 PM PDT 24 460541774 ps
T77 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4076170136 May 16 02:39:36 PM PDT 24 May 16 02:40:02 PM PDT 24 8505906003 ps
T883 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.336384592 May 16 02:39:37 PM PDT 24 May 16 02:39:43 PM PDT 24 445803655 ps
T884 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4294629881 May 16 02:39:22 PM PDT 24 May 16 02:39:28 PM PDT 24 509308432 ps
T885 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3534914827 May 16 02:39:47 PM PDT 24 May 16 02:39:53 PM PDT 24 507992115 ps
T886 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1683586579 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 457184286 ps
T887 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2985464968 May 16 02:39:46 PM PDT 24 May 16 02:39:54 PM PDT 24 1024520077 ps
T888 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1128595452 May 16 02:39:54 PM PDT 24 May 16 02:40:00 PM PDT 24 391726134 ps
T889 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3115185705 May 16 02:39:23 PM PDT 24 May 16 02:39:27 PM PDT 24 466834013 ps
T890 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2631278013 May 16 02:39:48 PM PDT 24 May 16 02:39:53 PM PDT 24 452898036 ps
T891 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3619648285 May 16 02:39:28 PM PDT 24 May 16 02:39:34 PM PDT 24 2736743176 ps
T892 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2525834567 May 16 02:39:47 PM PDT 24 May 16 02:39:53 PM PDT 24 319484964 ps
T893 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2787086093 May 16 02:39:45 PM PDT 24 May 16 02:39:50 PM PDT 24 339089073 ps
T894 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2073173432 May 16 02:39:20 PM PDT 24 May 16 02:39:40 PM PDT 24 4640465114 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1410080657 May 16 02:39:11 PM PDT 24 May 16 02:39:19 PM PDT 24 4820688554 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2043777965 May 16 02:39:19 PM PDT 24 May 16 02:39:23 PM PDT 24 525836070 ps
T897 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3364687342 May 16 02:39:40 PM PDT 24 May 16 02:39:44 PM PDT 24 412298801 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.856840251 May 16 02:39:22 PM PDT 24 May 16 02:39:27 PM PDT 24 455683319 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2107518843 May 16 02:39:09 PM PDT 24 May 16 02:39:15 PM PDT 24 785221343 ps
T900 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3189509866 May 16 02:39:45 PM PDT 24 May 16 02:39:51 PM PDT 24 400688195 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2173811809 May 16 02:39:22 PM PDT 24 May 16 02:39:28 PM PDT 24 495739997 ps
T902 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1824444644 May 16 02:39:28 PM PDT 24 May 16 02:39:35 PM PDT 24 411519851 ps
T903 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1764601711 May 16 02:39:57 PM PDT 24 May 16 02:40:04 PM PDT 24 347858348 ps
T904 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4123294218 May 16 02:39:10 PM PDT 24 May 16 02:39:15 PM PDT 24 334366496 ps
T905 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2022700523 May 16 02:39:19 PM PDT 24 May 16 02:39:25 PM PDT 24 788115882 ps
T906 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1697129113 May 16 02:39:38 PM PDT 24 May 16 02:39:43 PM PDT 24 476561070 ps
T907 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4199978745 May 16 02:39:44 PM PDT 24 May 16 02:39:49 PM PDT 24 503737889 ps
T908 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3224610195 May 16 02:39:45 PM PDT 24 May 16 02:39:52 PM PDT 24 445846790 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3629679260 May 16 02:39:35 PM PDT 24 May 16 02:39:39 PM PDT 24 407145859 ps
T910 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.813196639 May 16 02:39:54 PM PDT 24 May 16 02:40:00 PM PDT 24 491664682 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.811302880 May 16 02:39:29 PM PDT 24 May 16 02:39:46 PM PDT 24 4294796497 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.891535666 May 16 02:39:24 PM PDT 24 May 16 02:39:31 PM PDT 24 422848180 ps
T913 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3574613915 May 16 02:39:30 PM PDT 24 May 16 02:39:37 PM PDT 24 646354674 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.870023361 May 16 02:39:10 PM PDT 24 May 16 02:39:15 PM PDT 24 601237704 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1917014065 May 16 02:39:10 PM PDT 24 May 16 02:39:16 PM PDT 24 788998732 ps
T916 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3499638315 May 16 02:39:53 PM PDT 24 May 16 02:39:59 PM PDT 24 334066219 ps
T917 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2922690694 May 16 02:39:24 PM PDT 24 May 16 02:39:30 PM PDT 24 613011523 ps
T918 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2386228947 May 16 02:39:47 PM PDT 24 May 16 02:39:52 PM PDT 24 487234673 ps
T919 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2304601272 May 16 02:39:11 PM PDT 24 May 16 02:39:16 PM PDT 24 409183371 ps

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.310745082
Short name T3
Test name
Test status
Simulation time 598627615866 ps
CPU time 755.65 seconds
Started May 16 02:08:10 PM PDT 24
Finished May 16 02:20:46 PM PDT 24
Peak memory 201796 kb
Host smart-cd57f241-6771-49b2-ba18-c323a480f0f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310745082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.310745082
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2770427858
Short name T37
Test name
Test status
Simulation time 862254438432 ps
CPU time 760.39 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:21:11 PM PDT 24
Peak memory 210428 kb
Host smart-3611592f-d25f-41f4-a72a-d65901a09b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770427858 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2770427858
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3004818912
Short name T2
Test name
Test status
Simulation time 486292584256 ps
CPU time 1079.58 seconds
Started May 16 02:11:44 PM PDT 24
Finished May 16 02:29:45 PM PDT 24
Peak memory 201900 kb
Host smart-bea1072e-5436-4f9d-a1c1-46321517af8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004818912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3004818912
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.599024575
Short name T17
Test name
Test status
Simulation time 1376806072809 ps
CPU time 504.31 seconds
Started May 16 02:11:36 PM PDT 24
Finished May 16 02:20:02 PM PDT 24
Peak memory 210516 kb
Host smart-7f44608b-e738-4239-b2a9-e1dde625bc16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599024575 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.599024575
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3574208661
Short name T129
Test name
Test status
Simulation time 534932263463 ps
CPU time 271.68 seconds
Started May 16 02:11:29 PM PDT 24
Finished May 16 02:16:01 PM PDT 24
Peak memory 201892 kb
Host smart-b2fe19a3-8629-4db8-8fc2-f4e8686e48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574208661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3574208661
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.565563787
Short name T51
Test name
Test status
Simulation time 367313573478 ps
CPU time 562.57 seconds
Started May 16 02:11:28 PM PDT 24
Finished May 16 02:20:51 PM PDT 24
Peak memory 210400 kb
Host smart-ad100b3c-cf47-4ec0-b91c-8abbe4b369f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565563787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
565563787
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3740654954
Short name T147
Test name
Test status
Simulation time 648505650942 ps
CPU time 311.97 seconds
Started May 16 02:10:04 PM PDT 24
Finished May 16 02:15:17 PM PDT 24
Peak memory 201908 kb
Host smart-80cd3744-ef91-48ad-8af6-eb99a2fce1ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740654954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3740654954
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4158693706
Short name T212
Test name
Test status
Simulation time 496714763294 ps
CPU time 227.71 seconds
Started May 16 02:12:19 PM PDT 24
Finished May 16 02:16:09 PM PDT 24
Peak memory 201792 kb
Host smart-2d2df05f-f00b-4587-ac59-657e2b9e94f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158693706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4158693706
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.815933976
Short name T27
Test name
Test status
Simulation time 490428306535 ps
CPU time 308.35 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:19:01 PM PDT 24
Peak memory 201776 kb
Host smart-3a1716cd-bf78-4124-8a9b-3ec7ec1b03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815933976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.815933976
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1298291294
Short name T211
Test name
Test status
Simulation time 502150626723 ps
CPU time 1125.83 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:25:21 PM PDT 24
Peak memory 201652 kb
Host smart-2aaf771d-16e8-4c7a-8250-4c29a41864ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298291294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1298291294
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2896122605
Short name T67
Test name
Test status
Simulation time 488944123 ps
CPU time 3.23 seconds
Started May 16 02:39:30 PM PDT 24
Finished May 16 02:39:38 PM PDT 24
Peak memory 201916 kb
Host smart-c236f5d1-f232-4f59-90f6-a061cc0f7810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896122605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2896122605
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3472523726
Short name T127
Test name
Test status
Simulation time 490910603323 ps
CPU time 1191.12 seconds
Started May 16 02:13:47 PM PDT 24
Finished May 16 02:33:40 PM PDT 24
Peak memory 201820 kb
Host smart-e4054a04-3d0b-40a6-8ad7-ace70920044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472523726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3472523726
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.4268799558
Short name T64
Test name
Test status
Simulation time 4331507173 ps
CPU time 11.26 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:05:47 PM PDT 24
Peak memory 217360 kb
Host smart-6537696e-c01e-488e-87dc-a25941eb78b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268799558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4268799558
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3369569615
Short name T224
Test name
Test status
Simulation time 570181735607 ps
CPU time 659.42 seconds
Started May 16 02:08:07 PM PDT 24
Finished May 16 02:19:07 PM PDT 24
Peak memory 201736 kb
Host smart-cd1bde9f-b19b-457d-8cd0-fad50b8f55d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369569615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3369569615
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4218750767
Short name T201
Test name
Test status
Simulation time 522284623921 ps
CPU time 1109.56 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:25:05 PM PDT 24
Peak memory 201832 kb
Host smart-7ea703dc-297a-49bf-ae5a-f1e558e12bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218750767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4218750767
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3996131314
Short name T11
Test name
Test status
Simulation time 495311494253 ps
CPU time 1150.58 seconds
Started May 16 02:12:44 PM PDT 24
Finished May 16 02:31:57 PM PDT 24
Peak memory 201808 kb
Host smart-8138ac7f-eb40-4cd5-8d04-f2b4d5703a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996131314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3996131314
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1583738899
Short name T197
Test name
Test status
Simulation time 350428019809 ps
CPU time 774.42 seconds
Started May 16 02:09:11 PM PDT 24
Finished May 16 02:22:08 PM PDT 24
Peak memory 201852 kb
Host smart-995c8165-3581-4aa0-b4bd-236b176a2415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583738899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1583738899
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3063055005
Short name T162
Test name
Test status
Simulation time 515940002914 ps
CPU time 331.3 seconds
Started May 16 02:12:56 PM PDT 24
Finished May 16 02:18:30 PM PDT 24
Peak memory 201784 kb
Host smart-89e7b442-4c07-4bb2-bd1d-7d9cb22f2a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063055005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3063055005
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.883750193
Short name T103
Test name
Test status
Simulation time 850530339 ps
CPU time 4.61 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:29 PM PDT 24
Peak memory 201852 kb
Host smart-b505391a-047a-4799-b3de-3dc6b3b04840
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883750193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.883750193
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4039414903
Short name T206
Test name
Test status
Simulation time 320696269204 ps
CPU time 197 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:15:39 PM PDT 24
Peak memory 201804 kb
Host smart-61798cda-4b80-4c8a-afc8-5b2396fedcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039414903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4039414903
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.469603268
Short name T158
Test name
Test status
Simulation time 163121646394 ps
CPU time 43.47 seconds
Started May 16 02:09:42 PM PDT 24
Finished May 16 02:10:26 PM PDT 24
Peak memory 201800 kb
Host smart-447292d9-5f65-49ef-977d-19777da1b8a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469603268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.469603268
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3071872651
Short name T171
Test name
Test status
Simulation time 341042461443 ps
CPU time 181.5 seconds
Started May 16 02:08:32 PM PDT 24
Finished May 16 02:11:35 PM PDT 24
Peak memory 201788 kb
Host smart-332f9629-349b-41b0-9149-4c83cfa478ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071872651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3071872651
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3859063335
Short name T140
Test name
Test status
Simulation time 552871182807 ps
CPU time 1357.26 seconds
Started May 16 02:07:08 PM PDT 24
Finished May 16 02:29:48 PM PDT 24
Peak memory 201836 kb
Host smart-f4fc7589-1fad-4be4-bb4d-c1081aa1df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859063335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3859063335
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3564869901
Short name T194
Test name
Test status
Simulation time 224275307574 ps
CPU time 107.2 seconds
Started May 16 02:13:18 PM PDT 24
Finished May 16 02:15:06 PM PDT 24
Peak memory 210140 kb
Host smart-772b76c9-b9e6-4621-9281-4281ffb85827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564869901 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3564869901
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3795012010
Short name T35
Test name
Test status
Simulation time 327964057538 ps
CPU time 424.28 seconds
Started May 16 02:12:08 PM PDT 24
Finished May 16 02:19:14 PM PDT 24
Peak memory 201844 kb
Host smart-3034bf03-b7cd-40c6-bfaf-0a21fc54207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795012010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3795012010
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1902214001
Short name T310
Test name
Test status
Simulation time 498098178997 ps
CPU time 542.52 seconds
Started May 16 02:13:53 PM PDT 24
Finished May 16 02:22:57 PM PDT 24
Peak memory 201736 kb
Host smart-37704488-692f-4620-b70a-142fe7b01378
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902214001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1902214001
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1952937774
Short name T216
Test name
Test status
Simulation time 447967367722 ps
CPU time 88.4 seconds
Started May 16 02:07:39 PM PDT 24
Finished May 16 02:09:08 PM PDT 24
Peak memory 218644 kb
Host smart-2389f90a-8f55-48b9-a4b2-059fe0a46358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952937774 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1952937774
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3601364972
Short name T255
Test name
Test status
Simulation time 368354725333 ps
CPU time 809.42 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:27:17 PM PDT 24
Peak memory 201920 kb
Host smart-9f858d56-6910-4b47-91b0-8a823e4ebbe8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601364972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3601364972
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2221352016
Short name T53
Test name
Test status
Simulation time 2388151917 ps
CPU time 5.99 seconds
Started May 16 02:39:08 PM PDT 24
Finished May 16 02:39:17 PM PDT 24
Peak memory 201740 kb
Host smart-d062aeee-238b-485c-965c-67f0eef778de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221352016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2221352016
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1414003872
Short name T235
Test name
Test status
Simulation time 484518360454 ps
CPU time 269.36 seconds
Started May 16 02:09:51 PM PDT 24
Finished May 16 02:14:23 PM PDT 24
Peak memory 201788 kb
Host smart-48cc7864-4de0-4eb6-bd43-5b6edd7f437b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414003872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1414003872
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2322896943
Short name T254
Test name
Test status
Simulation time 505285922028 ps
CPU time 481.57 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:13:53 PM PDT 24
Peak memory 201844 kb
Host smart-143137a4-863e-4372-ab76-3f84a7a70c8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322896943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2322896943
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3049311083
Short name T382
Test name
Test status
Simulation time 545994486 ps
CPU time 1.03 seconds
Started May 16 02:07:57 PM PDT 24
Finished May 16 02:08:00 PM PDT 24
Peak memory 201504 kb
Host smart-23bc04fe-8f74-4db9-973b-d04ee7b59a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049311083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3049311083
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3693048138
Short name T344
Test name
Test status
Simulation time 8733411503 ps
CPU time 7.82 seconds
Started May 16 02:39:21 PM PDT 24
Finished May 16 02:39:32 PM PDT 24
Peak memory 201984 kb
Host smart-fc8fdf1b-261c-41c5-a1bf-929282ae5931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693048138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3693048138
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1191837738
Short name T161
Test name
Test status
Simulation time 493971102331 ps
CPU time 88.86 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:12:13 PM PDT 24
Peak memory 201928 kb
Host smart-192e3edc-8c65-4393-907f-338f02229c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191837738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1191837738
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.773264817
Short name T183
Test name
Test status
Simulation time 462396009104 ps
CPU time 201.5 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:09:56 PM PDT 24
Peak memory 210156 kb
Host smart-ded46682-b6f9-4a57-82c3-3bc04d98d3fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773264817 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.773264817
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4156712894
Short name T273
Test name
Test status
Simulation time 513470312477 ps
CPU time 1038.95 seconds
Started May 16 02:12:44 PM PDT 24
Finished May 16 02:30:05 PM PDT 24
Peak memory 201920 kb
Host smart-a36ba91f-eec9-4c81-89dc-df9407cc6c4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156712894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4156712894
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.152814212
Short name T324
Test name
Test status
Simulation time 425070267751 ps
CPU time 1050.03 seconds
Started May 16 02:05:54 PM PDT 24
Finished May 16 02:23:26 PM PDT 24
Peak memory 201840 kb
Host smart-972ada83-de31-47f0-a07a-0e2307f7ee19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152814212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.152814212
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.269322122
Short name T248
Test name
Test status
Simulation time 559959004138 ps
CPU time 343.34 seconds
Started May 16 02:12:55 PM PDT 24
Finished May 16 02:18:42 PM PDT 24
Peak memory 201816 kb
Host smart-384a1c4d-cce9-4bb0-ae29-86f508036953
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269322122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.269322122
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.751997136
Short name T215
Test name
Test status
Simulation time 369448543353 ps
CPU time 898.55 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:28:08 PM PDT 24
Peak memory 201792 kb
Host smart-b093c5d5-8787-4189-a73b-02ce333b60c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751997136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.751997136
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3450121606
Short name T55
Test name
Test status
Simulation time 366321984124 ps
CPU time 762.41 seconds
Started May 16 02:06:42 PM PDT 24
Finished May 16 02:19:25 PM PDT 24
Peak memory 201832 kb
Host smart-5c665a36-2fca-4eab-98e1-5c042a16a7c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450121606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3450121606
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1265568074
Short name T204
Test name
Test status
Simulation time 327398836224 ps
CPU time 791.44 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:21:44 PM PDT 24
Peak memory 201836 kb
Host smart-4fb418b5-06c1-4bc2-a4d9-4e3d0401bbf8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265568074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1265568074
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1798797226
Short name T234
Test name
Test status
Simulation time 548059949442 ps
CPU time 350.17 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:19:43 PM PDT 24
Peak memory 201816 kb
Host smart-c95030ab-27b5-42d0-ae57-eb04e94f9e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798797226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1798797226
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3657515959
Short name T135
Test name
Test status
Simulation time 169177914037 ps
CPU time 204.89 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:17:19 PM PDT 24
Peak memory 201828 kb
Host smart-edb0289f-f001-47c5-85b8-13875ba4083f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657515959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3657515959
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3513798413
Short name T128
Test name
Test status
Simulation time 482522184696 ps
CPU time 194.98 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:09:14 PM PDT 24
Peak memory 201792 kb
Host smart-83c1d734-3788-475a-bf2d-58f03b74d3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513798413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3513798413
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2567269639
Short name T271
Test name
Test status
Simulation time 168650674379 ps
CPU time 69.79 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:12:17 PM PDT 24
Peak memory 201852 kb
Host smart-39046cff-a056-4122-a760-061b58e6102e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567269639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2567269639
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1543516794
Short name T289
Test name
Test status
Simulation time 570157839951 ps
CPU time 317.29 seconds
Started May 16 02:06:50 PM PDT 24
Finished May 16 02:12:10 PM PDT 24
Peak memory 201824 kb
Host smart-b93aad7b-21b7-4707-baa2-774852b5911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543516794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1543516794
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3017841031
Short name T101
Test name
Test status
Simulation time 329984067376 ps
CPU time 719.77 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:18:01 PM PDT 24
Peak memory 201840 kb
Host smart-fec587bf-6fbb-4a07-82ee-fd574ba1ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017841031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3017841031
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3608986910
Short name T290
Test name
Test status
Simulation time 569407492652 ps
CPU time 1330.59 seconds
Started May 16 02:12:09 PM PDT 24
Finished May 16 02:34:21 PM PDT 24
Peak memory 201900 kb
Host smart-569de8bb-8599-4e8d-9ea5-86bc8c846f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608986910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3608986910
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1978493407
Short name T298
Test name
Test status
Simulation time 353697676944 ps
CPU time 786.44 seconds
Started May 16 02:06:57 PM PDT 24
Finished May 16 02:20:06 PM PDT 24
Peak memory 201872 kb
Host smart-8357817b-3d02-4c9b-8de3-f37787e9388d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978493407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1978493407
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1689166071
Short name T346
Test name
Test status
Simulation time 79621509660 ps
CPU time 373.18 seconds
Started May 16 02:07:20 PM PDT 24
Finished May 16 02:13:34 PM PDT 24
Peak memory 202160 kb
Host smart-04a19644-929c-4007-ab36-4b216d01f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689166071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1689166071
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.513834904
Short name T303
Test name
Test status
Simulation time 379897305187 ps
CPU time 436.47 seconds
Started May 16 02:09:42 PM PDT 24
Finished May 16 02:17:00 PM PDT 24
Peak memory 201788 kb
Host smart-5b93c604-b84b-4a7a-a281-58ac938643ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513834904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.513834904
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2481079636
Short name T214
Test name
Test status
Simulation time 382977491243 ps
CPU time 123.54 seconds
Started May 16 02:11:05 PM PDT 24
Finished May 16 02:13:09 PM PDT 24
Peak memory 201824 kb
Host smart-7c48c122-717f-45fe-a1db-c4425838ba1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481079636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2481079636
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1119588401
Short name T195
Test name
Test status
Simulation time 161771547720 ps
CPU time 374.77 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:12:24 PM PDT 24
Peak memory 201840 kb
Host smart-43643080-3536-4d5f-af8a-385f905be7bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119588401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1119588401
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2637620919
Short name T269
Test name
Test status
Simulation time 516639232780 ps
CPU time 319.75 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:11:30 PM PDT 24
Peak memory 201808 kb
Host smart-b9db1fb5-fd5d-4412-a1fe-8ffe86e985a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637620919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2637620919
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.888393074
Short name T73
Test name
Test status
Simulation time 717492401 ps
CPU time 3.2 seconds
Started May 16 02:39:29 PM PDT 24
Finished May 16 02:39:38 PM PDT 24
Peak memory 217852 kb
Host smart-f862bb53-4f55-4ac0-9f48-ce871ddf75c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888393074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.888393074
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3072052048
Short name T208
Test name
Test status
Simulation time 489733802271 ps
CPU time 539.61 seconds
Started May 16 02:05:37 PM PDT 24
Finished May 16 02:14:38 PM PDT 24
Peak memory 201804 kb
Host smart-3afa0e54-aa86-4e31-b17a-d0692c3cdfec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072052048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3072052048
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.687171816
Short name T249
Test name
Test status
Simulation time 201592075720 ps
CPU time 477.86 seconds
Started May 16 02:05:42 PM PDT 24
Finished May 16 02:13:41 PM PDT 24
Peak memory 201800 kb
Host smart-f372b31b-cebf-42c4-b875-1eeb2e448861
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687171816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.687171816
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.4245508861
Short name T268
Test name
Test status
Simulation time 531473380296 ps
CPU time 1236.07 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:26:51 PM PDT 24
Peak memory 201912 kb
Host smart-f784ccf8-a2c0-48d8-a261-e5c8f09b78ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245508861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.4245508861
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1091782681
Short name T196
Test name
Test status
Simulation time 354091919864 ps
CPU time 222.8 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:10:17 PM PDT 24
Peak memory 201832 kb
Host smart-396e7690-224c-4d1e-b6b8-4aae9b32633a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091782681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1091782681
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.544909791
Short name T18
Test name
Test status
Simulation time 121316582651 ps
CPU time 91.33 seconds
Started May 16 02:09:31 PM PDT 24
Finished May 16 02:11:03 PM PDT 24
Peak memory 210040 kb
Host smart-c8e04240-3da1-416b-a54b-560044a2e20c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544909791 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.544909791
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4211810810
Short name T283
Test name
Test status
Simulation time 351507818337 ps
CPU time 220.19 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:09:30 PM PDT 24
Peak memory 201780 kb
Host smart-9a8d42e6-23ab-4a66-9662-d710f5b622dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211810810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4211810810
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1115771626
Short name T241
Test name
Test status
Simulation time 495521385345 ps
CPU time 372.34 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:18:34 PM PDT 24
Peak memory 201916 kb
Host smart-366444db-85b6-4f7b-9abb-4b84f7e17d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115771626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1115771626
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4171776729
Short name T226
Test name
Test status
Simulation time 164843318658 ps
CPU time 105 seconds
Started May 16 02:12:46 PM PDT 24
Finished May 16 02:14:32 PM PDT 24
Peak memory 201904 kb
Host smart-3e2a6fe6-296d-40c6-b159-9fd715cd3234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171776729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4171776729
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4032976911
Short name T185
Test name
Test status
Simulation time 376293599195 ps
CPU time 791.51 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:26:59 PM PDT 24
Peak memory 212376 kb
Host smart-ba45abbf-d718-4871-bd3f-47bd76b99f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032976911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4032976911
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2170086367
Short name T327
Test name
Test status
Simulation time 403896194463 ps
CPU time 104.97 seconds
Started May 16 02:05:55 PM PDT 24
Finished May 16 02:07:42 PM PDT 24
Peak memory 201780 kb
Host smart-19be2baa-1426-4c4c-9d2f-896adc552b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170086367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2170086367
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.668491332
Short name T238
Test name
Test status
Simulation time 519432894557 ps
CPU time 118.27 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:08:08 PM PDT 24
Peak memory 201828 kb
Host smart-429d035b-cc95-4d06-9c87-949556e08711
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668491332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.668491332
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3380618546
Short name T36
Test name
Test status
Simulation time 496743663399 ps
CPU time 644.69 seconds
Started May 16 02:07:37 PM PDT 24
Finished May 16 02:18:22 PM PDT 24
Peak memory 201840 kb
Host smart-f0a321d0-8db0-4390-9708-cbe7c5caf78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380618546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3380618546
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1671539426
Short name T227
Test name
Test status
Simulation time 579177191220 ps
CPU time 250.81 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:09:59 PM PDT 24
Peak memory 201720 kb
Host smart-96b9205e-46b0-4fea-922f-39b5e65f60c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671539426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1671539426
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.675967553
Short name T317
Test name
Test status
Simulation time 163477593013 ps
CPU time 120.91 seconds
Started May 16 02:13:11 PM PDT 24
Finished May 16 02:15:13 PM PDT 24
Peak memory 201892 kb
Host smart-d3fae5b3-6514-402c-907d-38cf9fd95909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675967553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.675967553
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.755748705
Short name T264
Test name
Test status
Simulation time 162910213170 ps
CPU time 379.16 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:12:10 PM PDT 24
Peak memory 201712 kb
Host smart-2e251b98-673a-448e-ac5a-d9a539d9119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755748705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.755748705
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1394491202
Short name T239
Test name
Test status
Simulation time 347787746715 ps
CPU time 383.12 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:12:38 PM PDT 24
Peak memory 201800 kb
Host smart-9c01971b-3138-4b68-90bd-4ebfc60d2da8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394491202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1394491202
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1389941657
Short name T45
Test name
Test status
Simulation time 106735466614 ps
CPU time 415.71 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:13:30 PM PDT 24
Peak memory 202132 kb
Host smart-4a501f2f-2630-492d-a464-d6d1d7beffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389941657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1389941657
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2285788389
Short name T189
Test name
Test status
Simulation time 78606325486 ps
CPU time 409.44 seconds
Started May 16 02:08:39 PM PDT 24
Finished May 16 02:15:30 PM PDT 24
Peak memory 202172 kb
Host smart-c725f824-dd8d-400c-8ec9-e517b943f4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285788389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2285788389
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1657834153
Short name T318
Test name
Test status
Simulation time 322111656523 ps
CPU time 49.66 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:06:36 PM PDT 24
Peak memory 201828 kb
Host smart-f395e14c-f609-423f-9e66-c183538c2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657834153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1657834153
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4076170136
Short name T77
Test name
Test status
Simulation time 8505906003 ps
CPU time 22.36 seconds
Started May 16 02:39:36 PM PDT 24
Finished May 16 02:40:02 PM PDT 24
Peak memory 201840 kb
Host smart-da7dcc3d-9f82-41a8-a068-2903f266f286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076170136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4076170136
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.725955870
Short name T296
Test name
Test status
Simulation time 166019683848 ps
CPU time 370.03 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:11:46 PM PDT 24
Peak memory 201780 kb
Host smart-ec69abbc-bdb5-414d-b2a7-f5234351ffda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725955870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.725955870
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2960649118
Short name T258
Test name
Test status
Simulation time 325464579503 ps
CPU time 159.98 seconds
Started May 16 02:06:12 PM PDT 24
Finished May 16 02:08:55 PM PDT 24
Peak memory 201788 kb
Host smart-81cc378b-6485-4610-a7ff-efd46b493f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960649118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2960649118
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1771731690
Short name T256
Test name
Test status
Simulation time 508140719370 ps
CPU time 1292.42 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:27:55 PM PDT 24
Peak memory 201800 kb
Host smart-bb6d72e5-62db-4392-a205-6214665a7bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771731690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1771731690
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2433399782
Short name T193
Test name
Test status
Simulation time 104862281055 ps
CPU time 341.05 seconds
Started May 16 02:06:43 PM PDT 24
Finished May 16 02:12:25 PM PDT 24
Peak memory 202128 kb
Host smart-d9b46dff-a92b-477b-9fae-4e46b30eda7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433399782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2433399782
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3150362045
Short name T294
Test name
Test status
Simulation time 511023690310 ps
CPU time 153.89 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:08:08 PM PDT 24
Peak memory 201820 kb
Host smart-114e6469-5f62-4701-9044-15acacbb1736
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150362045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3150362045
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2703100495
Short name T316
Test name
Test status
Simulation time 190541969779 ps
CPU time 234.41 seconds
Started May 16 02:05:36 PM PDT 24
Finished May 16 02:09:32 PM PDT 24
Peak memory 201920 kb
Host smart-1676d08b-dc07-40cf-821a-8a9b4ade2aac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703100495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2703100495
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3934663122
Short name T187
Test name
Test status
Simulation time 68722426441 ps
CPU time 359.13 seconds
Started May 16 02:09:12 PM PDT 24
Finished May 16 02:15:13 PM PDT 24
Peak memory 202024 kb
Host smart-02b7ab23-8507-4b63-ba4b-5d8c41f72450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934663122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3934663122
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3878096653
Short name T285
Test name
Test status
Simulation time 198715258347 ps
CPU time 109.07 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:07:40 PM PDT 24
Peak memory 201840 kb
Host smart-e8eec7cb-3b72-40e9-bd6e-35899e0b182e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878096653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3878096653
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2846908712
Short name T257
Test name
Test status
Simulation time 224096396206 ps
CPU time 499.82 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:14:08 PM PDT 24
Peak memory 201848 kb
Host smart-c236ba5b-f9c2-4983-98e2-8ffb6d298fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846908712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2846908712
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1110267518
Short name T88
Test name
Test status
Simulation time 301139379854 ps
CPU time 278.45 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:15:46 PM PDT 24
Peak memory 210400 kb
Host smart-acf0a97a-3388-4616-a5c4-52353d461d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110267518 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1110267518
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1997449150
Short name T166
Test name
Test status
Simulation time 672008485496 ps
CPU time 413.17 seconds
Started May 16 02:11:48 PM PDT 24
Finished May 16 02:18:43 PM PDT 24
Peak memory 201872 kb
Host smart-dd3d9c3e-e3aa-4882-afa0-9e267b7b0174
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997449150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1997449150
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.148904206
Short name T347
Test name
Test status
Simulation time 120326975142 ps
CPU time 640.12 seconds
Started May 16 02:11:58 PM PDT 24
Finished May 16 02:22:40 PM PDT 24
Peak memory 202140 kb
Host smart-1c1e42d1-628d-4293-be47-c4882ae23bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148904206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.148904206
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.572384445
Short name T22
Test name
Test status
Simulation time 183159900033 ps
CPU time 308.24 seconds
Started May 16 02:11:58 PM PDT 24
Finished May 16 02:17:07 PM PDT 24
Peak memory 210480 kb
Host smart-5f302ff1-e314-4e70-a714-0e533b589293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572384445 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.572384445
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3329308302
Short name T320
Test name
Test status
Simulation time 347192628777 ps
CPU time 183.9 seconds
Started May 16 02:12:22 PM PDT 24
Finished May 16 02:15:27 PM PDT 24
Peak memory 201912 kb
Host smart-ccc887ab-3dd7-475b-a679-ba89e7a01979
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329308302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3329308302
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2245972736
Short name T305
Test name
Test status
Simulation time 596780925091 ps
CPU time 1339.18 seconds
Started May 16 02:12:54 PM PDT 24
Finished May 16 02:35:16 PM PDT 24
Peak memory 201884 kb
Host smart-a8448aa9-aed2-4238-bb13-d01ef37b0a8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245972736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2245972736
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1852554845
Short name T244
Test name
Test status
Simulation time 667347005970 ps
CPU time 151.09 seconds
Started May 16 02:13:10 PM PDT 24
Finished May 16 02:15:43 PM PDT 24
Peak memory 201832 kb
Host smart-d878b0fa-e1a0-4e50-b318-fabdfeac1844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852554845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1852554845
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2202030706
Short name T349
Test name
Test status
Simulation time 70489591542 ps
CPU time 376.88 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:12:19 PM PDT 24
Peak memory 202160 kb
Host smart-9432c5b3-af60-40c7-be2b-28b95bf442d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202030706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2202030706
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1341260980
Short name T105
Test name
Test status
Simulation time 532067386 ps
CPU time 1.76 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 201864 kb
Host smart-59352368-caf7-4b77-8743-7ce800227cbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341260980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1341260980
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1742724916
Short name T846
Test name
Test status
Simulation time 26226785947 ps
CPU time 35.91 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201916 kb
Host smart-2daf9e10-c8bc-460d-9eee-56072dfe6c14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742724916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1742724916
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2256659323
Short name T124
Test name
Test status
Simulation time 789150432 ps
CPU time 1.18 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:14 PM PDT 24
Peak memory 201676 kb
Host smart-e93cdca6-3c14-4ff9-9c50-8e762bd44ce6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256659323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2256659323
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.641657597
Short name T89
Test name
Test status
Simulation time 577728167 ps
CPU time 2.23 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 201696 kb
Host smart-3a06c4eb-f451-486f-9d12-7c1eb72f36b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641657597 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.641657597
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1243986817
Short name T116
Test name
Test status
Simulation time 460541774 ps
CPU time 1.8 seconds
Started May 16 02:39:12 PM PDT 24
Finished May 16 02:39:17 PM PDT 24
Peak memory 201664 kb
Host smart-9b3ac137-03fa-4b07-9fc3-2b3dec6d819d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243986817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1243986817
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4123294218
Short name T904
Test name
Test status
Simulation time 334366496 ps
CPU time 1.43 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 201652 kb
Host smart-5006c154-94ec-4dca-8059-e29f61d79a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123294218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4123294218
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.870023361
Short name T914
Test name
Test status
Simulation time 601237704 ps
CPU time 1.54 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 201972 kb
Host smart-9a673992-0b05-4798-bb40-739c072ed8b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870023361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.870023361
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1410080657
Short name T895
Test name
Test status
Simulation time 4820688554 ps
CPU time 4.1 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:19 PM PDT 24
Peak memory 201904 kb
Host smart-be714450-d61a-4fe3-9de2-583b60d6748c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410080657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1410080657
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1917014065
Short name T915
Test name
Test status
Simulation time 788998732 ps
CPU time 1.81 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 201900 kb
Host smart-ab5d7b1d-1a6b-4fa1-b0c8-30be77aab74f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917014065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1917014065
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1536548206
Short name T106
Test name
Test status
Simulation time 27397975917 ps
CPU time 117.59 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:41:12 PM PDT 24
Peak memory 201944 kb
Host smart-89ba55af-2769-451d-883a-882105c1cc8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536548206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1536548206
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2107518843
Short name T899
Test name
Test status
Simulation time 785221343 ps
CPU time 2.54 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:15 PM PDT 24
Peak memory 201692 kb
Host smart-aa1c39e8-8b16-4864-acad-2f693a91edf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107518843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2107518843
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.24875816
Short name T850
Test name
Test status
Simulation time 487118498 ps
CPU time 1.17 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 201764 kb
Host smart-65660b9e-f5ca-4827-939b-29dec2261aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875816 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.24875816
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1844026584
Short name T825
Test name
Test status
Simulation time 439669394 ps
CPU time 1.24 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 201720 kb
Host smart-bf66e3e6-aeec-4d80-b5a7-e763e55195da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844026584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1844026584
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3974720785
Short name T809
Test name
Test status
Simulation time 285236879 ps
CPU time 1.26 seconds
Started May 16 02:39:12 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 201708 kb
Host smart-541a5db5-fcf4-4905-82e8-00a805ae3e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974720785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3974720785
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3684321209
Short name T121
Test name
Test status
Simulation time 3841095405 ps
CPU time 14.08 seconds
Started May 16 02:39:12 PM PDT 24
Finished May 16 02:39:29 PM PDT 24
Peak memory 202016 kb
Host smart-1dcabf76-e3ce-4bd0-900c-e203ba36fd4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684321209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3684321209
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.799266274
Short name T74
Test name
Test status
Simulation time 908884351 ps
CPU time 3.17 seconds
Started May 16 02:39:09 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 210100 kb
Host smart-613057f6-95cc-4279-aace-627771b06687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799266274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.799266274
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.925783143
Short name T58
Test name
Test status
Simulation time 4398534539 ps
CPU time 11.97 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:26 PM PDT 24
Peak memory 201928 kb
Host smart-cad3ae19-0426-4f12-a40d-d6099be12ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925783143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.925783143
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3574613915
Short name T913
Test name
Test status
Simulation time 646354674 ps
CPU time 1.73 seconds
Started May 16 02:39:30 PM PDT 24
Finished May 16 02:39:37 PM PDT 24
Peak memory 201764 kb
Host smart-3330e11f-a337-419f-8d63-422c678167c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574613915 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3574613915
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1824444644
Short name T902
Test name
Test status
Simulation time 411519851 ps
CPU time 1.94 seconds
Started May 16 02:39:28 PM PDT 24
Finished May 16 02:39:35 PM PDT 24
Peak memory 201668 kb
Host smart-12ca7127-7e7b-48c7-91c3-8c20b975a46e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824444644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1824444644
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1558145205
Short name T876
Test name
Test status
Simulation time 443958385 ps
CPU time 1.13 seconds
Started May 16 02:39:30 PM PDT 24
Finished May 16 02:39:36 PM PDT 24
Peak memory 201656 kb
Host smart-6a2dec0e-afb0-4e78-995f-ab64d8333a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558145205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1558145205
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1898256310
Short name T54
Test name
Test status
Simulation time 3811945611 ps
CPU time 10.24 seconds
Started May 16 02:39:29 PM PDT 24
Finished May 16 02:39:44 PM PDT 24
Peak memory 201984 kb
Host smart-aa41fbb3-bd54-4103-b2dc-693911f215d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898256310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1898256310
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.891535666
Short name T912
Test name
Test status
Simulation time 422848180 ps
CPU time 2.59 seconds
Started May 16 02:39:24 PM PDT 24
Finished May 16 02:39:31 PM PDT 24
Peak memory 218272 kb
Host smart-eb3fada1-3df5-40d7-b37c-43a003e12f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891535666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.891535666
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.99873188
Short name T72
Test name
Test status
Simulation time 4225992882 ps
CPU time 11.91 seconds
Started May 16 02:39:23 PM PDT 24
Finished May 16 02:39:39 PM PDT 24
Peak memory 201872 kb
Host smart-9cc2dcfd-48a2-45da-bace-08c4faeb10ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99873188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_int
g_err.99873188
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2367892630
Short name T837
Test name
Test status
Simulation time 392091143 ps
CPU time 1.2 seconds
Started May 16 02:39:31 PM PDT 24
Finished May 16 02:39:37 PM PDT 24
Peak memory 201720 kb
Host smart-9bb65012-0f69-4c88-8d84-10b1c3f0cdf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367892630 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2367892630
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2716371177
Short name T104
Test name
Test status
Simulation time 430071705 ps
CPU time 1.34 seconds
Started May 16 02:39:28 PM PDT 24
Finished May 16 02:39:34 PM PDT 24
Peak memory 201696 kb
Host smart-26ee4c36-422d-487b-9ad3-40c215ff1c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716371177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2716371177
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.324106787
Short name T831
Test name
Test status
Simulation time 337127718 ps
CPU time 1.43 seconds
Started May 16 02:39:27 PM PDT 24
Finished May 16 02:39:33 PM PDT 24
Peak memory 201704 kb
Host smart-9f4dc9ba-bf4f-475e-abd2-e27978f75ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324106787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.324106787
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3619648285
Short name T891
Test name
Test status
Simulation time 2736743176 ps
CPU time 1.38 seconds
Started May 16 02:39:28 PM PDT 24
Finished May 16 02:39:34 PM PDT 24
Peak memory 201696 kb
Host smart-d085cca1-e3f1-4fc8-aa9f-ccaf7d4dc10d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619648285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3619648285
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1107105626
Short name T75
Test name
Test status
Simulation time 3991763161 ps
CPU time 4.06 seconds
Started May 16 02:39:31 PM PDT 24
Finished May 16 02:39:40 PM PDT 24
Peak memory 201952 kb
Host smart-57255bbd-ac0e-4104-8f65-356cfaaa0d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107105626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1107105626
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1883465504
Short name T855
Test name
Test status
Simulation time 436484315 ps
CPU time 1.4 seconds
Started May 16 02:39:28 PM PDT 24
Finished May 16 02:39:35 PM PDT 24
Peak memory 201760 kb
Host smart-47a51452-a0a0-4baf-80a0-17d6c07f8899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883465504 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1883465504
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3900704429
Short name T110
Test name
Test status
Simulation time 467652251 ps
CPU time 1.45 seconds
Started May 16 02:39:27 PM PDT 24
Finished May 16 02:39:34 PM PDT 24
Peak memory 201724 kb
Host smart-f028c088-0345-40ad-bccd-2da514032205
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900704429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3900704429
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3904148308
Short name T828
Test name
Test status
Simulation time 452151577 ps
CPU time 0.96 seconds
Started May 16 02:39:30 PM PDT 24
Finished May 16 02:39:36 PM PDT 24
Peak memory 201672 kb
Host smart-14b76319-b3d2-45ce-bcc6-7aed9945c4e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904148308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3904148308
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.829802294
Short name T874
Test name
Test status
Simulation time 2263919277 ps
CPU time 2.06 seconds
Started May 16 02:39:30 PM PDT 24
Finished May 16 02:39:37 PM PDT 24
Peak memory 201788 kb
Host smart-ed75ab78-468c-43d8-9c88-0667c8b37cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829802294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.829802294
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1279706166
Short name T844
Test name
Test status
Simulation time 470734194 ps
CPU time 2.49 seconds
Started May 16 02:39:26 PM PDT 24
Finished May 16 02:39:33 PM PDT 24
Peak memory 201940 kb
Host smart-5cdb8c3a-c9ae-4f2b-a3fd-b1a0fb7cf645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279706166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1279706166
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.811302880
Short name T911
Test name
Test status
Simulation time 4294796497 ps
CPU time 11.69 seconds
Started May 16 02:39:29 PM PDT 24
Finished May 16 02:39:46 PM PDT 24
Peak memory 202004 kb
Host smart-0cac52b6-977e-4922-8845-44f4243a029d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811302880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.811302880
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.336384592
Short name T883
Test name
Test status
Simulation time 445803655 ps
CPU time 2.23 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:43 PM PDT 24
Peak memory 201728 kb
Host smart-39541e33-9565-4afd-9b70-2491c27cd77b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336384592 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.336384592
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3799070712
Short name T120
Test name
Test status
Simulation time 540723334 ps
CPU time 1.06 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:42 PM PDT 24
Peak memory 201696 kb
Host smart-a857a2dc-55c6-48ea-ac99-f4d04698228a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799070712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3799070712
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.614751616
Short name T803
Test name
Test status
Simulation time 313340417 ps
CPU time 1.02 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:42 PM PDT 24
Peak memory 201648 kb
Host smart-89d59af6-d364-4d0e-88e5-c1e86739b9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614751616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.614751616
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2581514607
Short name T841
Test name
Test status
Simulation time 4607285964 ps
CPU time 2.79 seconds
Started May 16 02:39:35 PM PDT 24
Finished May 16 02:39:41 PM PDT 24
Peak memory 201988 kb
Host smart-67b0993b-8cc3-4b59-bd36-49afbda72216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581514607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2581514607
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.953335379
Short name T854
Test name
Test status
Simulation time 8844265111 ps
CPU time 4.07 seconds
Started May 16 02:39:30 PM PDT 24
Finished May 16 02:39:39 PM PDT 24
Peak memory 201956 kb
Host smart-4618dbfe-7f5c-4722-b839-0f65560ada91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953335379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.953335379
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3629679260
Short name T909
Test name
Test status
Simulation time 407145859 ps
CPU time 1.32 seconds
Started May 16 02:39:35 PM PDT 24
Finished May 16 02:39:39 PM PDT 24
Peak memory 201680 kb
Host smart-a584c53a-ec0b-4a79-95a0-f8ee1bd8144e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629679260 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3629679260
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1626379047
Short name T111
Test name
Test status
Simulation time 375449308 ps
CPU time 1.69 seconds
Started May 16 02:39:36 PM PDT 24
Finished May 16 02:39:41 PM PDT 24
Peak memory 201696 kb
Host smart-7006900a-c55d-41ca-abe3-3bec62e82ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626379047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1626379047
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3604847269
Short name T820
Test name
Test status
Simulation time 367941938 ps
CPU time 1.51 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:42 PM PDT 24
Peak memory 201660 kb
Host smart-09591663-0b7a-4b0c-825c-fad403a63863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604847269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3604847269
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1347238624
Short name T119
Test name
Test status
Simulation time 2517710115 ps
CPU time 3.94 seconds
Started May 16 02:39:38 PM PDT 24
Finished May 16 02:39:45 PM PDT 24
Peak memory 201752 kb
Host smart-81c95ab0-a796-4903-9558-47f8e15cd741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347238624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1347238624
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2587112538
Short name T61
Test name
Test status
Simulation time 524981342 ps
CPU time 1.96 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:43 PM PDT 24
Peak memory 201940 kb
Host smart-9184deaa-1f7d-4c13-9b2d-ea0ca35e2118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587112538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2587112538
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3333170991
Short name T345
Test name
Test status
Simulation time 4472415096 ps
CPU time 12.25 seconds
Started May 16 02:39:39 PM PDT 24
Finished May 16 02:39:55 PM PDT 24
Peak memory 201896 kb
Host smart-e0005a2f-a7ff-45e4-8245-a0ee78827ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333170991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3333170991
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3757545499
Short name T861
Test name
Test status
Simulation time 605090304 ps
CPU time 1.58 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:42 PM PDT 24
Peak memory 201708 kb
Host smart-81406fb5-aaae-4dc3-a8d4-357b6d742aff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757545499 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3757545499
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3364687342
Short name T897
Test name
Test status
Simulation time 412298801 ps
CPU time 1.34 seconds
Started May 16 02:39:40 PM PDT 24
Finished May 16 02:39:44 PM PDT 24
Peak memory 201660 kb
Host smart-b5499bac-4fa1-4006-999d-d00eda51bfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364687342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3364687342
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1697129113
Short name T906
Test name
Test status
Simulation time 476561070 ps
CPU time 1.79 seconds
Started May 16 02:39:38 PM PDT 24
Finished May 16 02:39:43 PM PDT 24
Peak memory 201664 kb
Host smart-30734af8-fdf8-4dcd-b041-89c2996177a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697129113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1697129113
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.959060971
Short name T122
Test name
Test status
Simulation time 2112833999 ps
CPU time 7.9 seconds
Started May 16 02:39:37 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201692 kb
Host smart-5b14b0c1-35be-44fa-94cb-5ea7232e8019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959060971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.959060971
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1634357707
Short name T869
Test name
Test status
Simulation time 570569698 ps
CPU time 2.06 seconds
Started May 16 02:39:38 PM PDT 24
Finished May 16 02:39:44 PM PDT 24
Peak memory 201984 kb
Host smart-dcaa4c6b-3bf8-4d56-aced-ea05078b5c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634357707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1634357707
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4164965040
Short name T833
Test name
Test status
Simulation time 729413375 ps
CPU time 1.26 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201896 kb
Host smart-cd6877d6-1a0f-49f9-9dad-d6aae6044422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164965040 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.4164965040
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3019961567
Short name T853
Test name
Test status
Simulation time 523834036 ps
CPU time 0.99 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201700 kb
Host smart-17129e96-1f78-483a-a63c-090cc564d07e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019961567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3019961567
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3611039942
Short name T819
Test name
Test status
Simulation time 424539090 ps
CPU time 1.52 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201680 kb
Host smart-36266366-1d22-4e4c-8cf8-cb03be7403a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611039942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3611039942
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.791933415
Short name T877
Test name
Test status
Simulation time 2599319505 ps
CPU time 6.11 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:54 PM PDT 24
Peak memory 201740 kb
Host smart-a3fadec1-2f7f-4747-a2b2-965a381cb302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791933415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.791933415
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2985464968
Short name T887
Test name
Test status
Simulation time 1024520077 ps
CPU time 3.06 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:54 PM PDT 24
Peak memory 217840 kb
Host smart-899c9056-fec8-48ef-a997-778cfae94a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985464968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2985464968
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2548111162
Short name T343
Test name
Test status
Simulation time 4471563196 ps
CPU time 7.5 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:57 PM PDT 24
Peak memory 201948 kb
Host smart-5ac4d728-3b61-4fa3-b68f-6af0ce187f81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548111162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2548111162
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2988050929
Short name T842
Test name
Test status
Simulation time 600791553 ps
CPU time 2.35 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:50 PM PDT 24
Peak memory 201696 kb
Host smart-37dac76d-4444-46e1-96a3-4df3123bd54c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988050929 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2988050929
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3131073552
Short name T108
Test name
Test status
Simulation time 449825996 ps
CPU time 1.78 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201732 kb
Host smart-00b63f5b-4e6f-47f3-a305-4bdf5100fc1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131073552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3131073552
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1728679544
Short name T810
Test name
Test status
Simulation time 419447735 ps
CPU time 0.75 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201652 kb
Host smart-0a64b05b-387b-4a28-8709-a5ff4ff595e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728679544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1728679544
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3359890969
Short name T818
Test name
Test status
Simulation time 2368729766 ps
CPU time 2.59 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201740 kb
Host smart-1372b7d4-f52b-4031-8735-bff90a6b25c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359890969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3359890969
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.116332628
Short name T856
Test name
Test status
Simulation time 1102669969 ps
CPU time 2.71 seconds
Started May 16 02:39:47 PM PDT 24
Finished May 16 02:39:54 PM PDT 24
Peak memory 202024 kb
Host smart-ebfd1a38-31c9-47f2-a8a1-d5790398e3d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116332628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.116332628
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1605003565
Short name T76
Test name
Test status
Simulation time 4586481624 ps
CPU time 3.88 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201876 kb
Host smart-4beb4ce0-c06e-4c47-822d-033eb25f937d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605003565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1605003565
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3358849673
Short name T859
Test name
Test status
Simulation time 478508457 ps
CPU time 2.06 seconds
Started May 16 02:39:43 PM PDT 24
Finished May 16 02:39:48 PM PDT 24
Peak memory 201708 kb
Host smart-53d9bb3d-fe6e-44ee-8e89-61658cc8b6db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358849673 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3358849673
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3520385919
Short name T823
Test name
Test status
Simulation time 393117868 ps
CPU time 0.87 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201724 kb
Host smart-a69dc60f-de77-4453-a0ef-eb11b3dfd50e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520385919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3520385919
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2386228947
Short name T918
Test name
Test status
Simulation time 487234673 ps
CPU time 0.93 seconds
Started May 16 02:39:47 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201676 kb
Host smart-bd15408a-e4d2-4aa9-be75-b7031baa67e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386228947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2386228947
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1256427322
Short name T849
Test name
Test status
Simulation time 4488465708 ps
CPU time 11.61 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:40:01 PM PDT 24
Peak memory 202004 kb
Host smart-bc026a15-2ba0-476e-9068-48027bed3e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256427322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1256427322
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4209948185
Short name T873
Test name
Test status
Simulation time 764823350 ps
CPU time 3.69 seconds
Started May 16 02:39:43 PM PDT 24
Finished May 16 02:39:50 PM PDT 24
Peak memory 201960 kb
Host smart-1ba0535d-688b-4d3f-924c-6118213d93fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209948185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4209948185
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.970593014
Short name T868
Test name
Test status
Simulation time 3847914275 ps
CPU time 6.22 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:57 PM PDT 24
Peak memory 201908 kb
Host smart-226963a3-1e08-45de-a8c5-e0059a2cb3a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970593014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.970593014
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3534914827
Short name T885
Test name
Test status
Simulation time 507992115 ps
CPU time 2 seconds
Started May 16 02:39:47 PM PDT 24
Finished May 16 02:39:53 PM PDT 24
Peak memory 201712 kb
Host smart-6e6a434d-89af-4969-b7b9-83d8df0bfcde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534914827 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3534914827
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1521084443
Short name T875
Test name
Test status
Simulation time 484908054 ps
CPU time 1.91 seconds
Started May 16 02:39:43 PM PDT 24
Finished May 16 02:39:48 PM PDT 24
Peak memory 201684 kb
Host smart-c6d9710e-8649-472a-8768-4719ce64a197
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521084443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1521084443
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2908788398
Short name T814
Test name
Test status
Simulation time 337711370 ps
CPU time 1.4 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:48 PM PDT 24
Peak memory 201652 kb
Host smart-704510ec-db67-4190-ba81-4e2c085df196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908788398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2908788398
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2058976765
Short name T865
Test name
Test status
Simulation time 4223394685 ps
CPU time 14.75 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:40:03 PM PDT 24
Peak memory 202000 kb
Host smart-7f01ad6a-3f98-48b1-b195-589cf64c77fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058976765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2058976765
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3224610195
Short name T908
Test name
Test status
Simulation time 445846790 ps
CPU time 3.24 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201960 kb
Host smart-4f9da38c-b955-4e76-aec4-a7cb7ff97acd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224610195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3224610195
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2811146256
Short name T342
Test name
Test status
Simulation time 7891693137 ps
CPU time 6.58 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:57 PM PDT 24
Peak memory 201904 kb
Host smart-f60f249d-cdbf-44bc-98e4-d4d20be30625
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811146256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2811146256
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4066256395
Short name T107
Test name
Test status
Simulation time 1441477453 ps
CPU time 4.97 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 201880 kb
Host smart-911d14dd-b731-42ad-aee7-e3a0e19cd117
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066256395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4066256395
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2501285645
Short name T881
Test name
Test status
Simulation time 1104399534 ps
CPU time 3.25 seconds
Started May 16 02:39:10 PM PDT 24
Finished May 16 02:39:17 PM PDT 24
Peak memory 201624 kb
Host smart-4d2844b8-3042-4ee0-970e-e575639858ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501285645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2501285645
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2123688276
Short name T838
Test name
Test status
Simulation time 380039165 ps
CPU time 1.7 seconds
Started May 16 02:39:24 PM PDT 24
Finished May 16 02:39:30 PM PDT 24
Peak memory 201780 kb
Host smart-ab1ed007-bb2b-453a-bf23-d803adccb872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123688276 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2123688276
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1899560491
Short name T112
Test name
Test status
Simulation time 450590949 ps
CPU time 1.71 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:24 PM PDT 24
Peak memory 201676 kb
Host smart-c9f1184a-485d-4dc3-b2aa-8fe18c2e8a31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899560491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1899560491
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2304601272
Short name T919
Test name
Test status
Simulation time 409183371 ps
CPU time 1.69 seconds
Started May 16 02:39:11 PM PDT 24
Finished May 16 02:39:16 PM PDT 24
Peak memory 201628 kb
Host smart-1e148610-2f1b-4b5f-9d68-3baad1f6b169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304601272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2304601272
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3088661956
Short name T52
Test name
Test status
Simulation time 4383712180 ps
CPU time 14.79 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:38 PM PDT 24
Peak memory 201920 kb
Host smart-122e813a-f541-4f79-9d78-e774ead55fe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088661956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3088661956
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.713194184
Short name T68
Test name
Test status
Simulation time 590851429 ps
CPU time 1.5 seconds
Started May 16 02:39:12 PM PDT 24
Finished May 16 02:39:17 PM PDT 24
Peak memory 209952 kb
Host smart-6cd8dc6c-051f-450f-a6e3-da1e1ec8febd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713194184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.713194184
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.432817840
Short name T59
Test name
Test status
Simulation time 4296739970 ps
CPU time 3.91 seconds
Started May 16 02:39:12 PM PDT 24
Finished May 16 02:39:19 PM PDT 24
Peak memory 201984 kb
Host smart-5e2e1ad7-de64-4c9d-9cb9-b664446bdef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432817840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.432817840
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1982239342
Short name T858
Test name
Test status
Simulation time 419789605 ps
CPU time 1.11 seconds
Started May 16 02:39:43 PM PDT 24
Finished May 16 02:39:48 PM PDT 24
Peak memory 201772 kb
Host smart-5d90384d-1190-4af1-a334-a368b4667278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982239342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1982239342
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4124125757
Short name T802
Test name
Test status
Simulation time 565220716 ps
CPU time 0.82 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201684 kb
Host smart-b7078c33-a543-44d7-a34e-7fa40a163cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124125757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4124125757
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.279901361
Short name T867
Test name
Test status
Simulation time 492149685 ps
CPU time 0.98 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201660 kb
Host smart-6a0746bf-16c8-45a8-9a1e-a8b8cc1364f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279901361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.279901361
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3319177002
Short name T813
Test name
Test status
Simulation time 300489374 ps
CPU time 1.05 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201716 kb
Host smart-12fb2026-035a-41fa-8d2b-75179989b694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319177002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3319177002
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2370321776
Short name T805
Test name
Test status
Simulation time 474269321 ps
CPU time 1.81 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201620 kb
Host smart-1708b070-eb35-4e50-b3be-feea871baf81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370321776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2370321776
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3595822874
Short name T811
Test name
Test status
Simulation time 496618707 ps
CPU time 1.89 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:50 PM PDT 24
Peak memory 201692 kb
Host smart-8ea82104-8950-433e-a36f-37296c8c8f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595822874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3595822874
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3189509866
Short name T900
Test name
Test status
Simulation time 400688195 ps
CPU time 0.86 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201712 kb
Host smart-e5aeba6d-44c8-4440-b5a3-015ef2599f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189509866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3189509866
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1776599095
Short name T839
Test name
Test status
Simulation time 338837832 ps
CPU time 1.41 seconds
Started May 16 02:39:47 PM PDT 24
Finished May 16 02:39:53 PM PDT 24
Peak memory 201608 kb
Host smart-4787b0db-b57b-4fcd-bd66-39d682e81bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776599095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1776599095
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2636967849
Short name T816
Test name
Test status
Simulation time 282164140 ps
CPU time 1.28 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201684 kb
Host smart-2bef4f1a-a961-4b1d-bf7b-182a82a31302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636967849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2636967849
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4199978745
Short name T907
Test name
Test status
Simulation time 503737889 ps
CPU time 1.67 seconds
Started May 16 02:39:44 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201672 kb
Host smart-7158fe2a-576d-4a73-9ac7-ed2639b4230b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199978745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4199978745
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.359635217
Short name T114
Test name
Test status
Simulation time 1054819054 ps
CPU time 5.65 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:30 PM PDT 24
Peak memory 201928 kb
Host smart-a4b6b55b-7471-4d39-8c15-6926764887f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359635217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.359635217
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2819114536
Short name T109
Test name
Test status
Simulation time 28086408906 ps
CPU time 29.29 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:55 PM PDT 24
Peak memory 201652 kb
Host smart-61010757-0a45-4fa6-bb1f-243302a1cc0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819114536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2819114536
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.909971476
Short name T847
Test name
Test status
Simulation time 807183287 ps
CPU time 1.65 seconds
Started May 16 02:39:25 PM PDT 24
Finished May 16 02:39:30 PM PDT 24
Peak memory 201656 kb
Host smart-5534f022-08e8-498e-8307-95662c3b52c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909971476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.909971476
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.778013737
Short name T834
Test name
Test status
Simulation time 541282794 ps
CPU time 2.08 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:26 PM PDT 24
Peak memory 201780 kb
Host smart-79e63f59-1068-46ce-b84c-80adc09c809f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778013737 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.778013737
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1538889100
Short name T123
Test name
Test status
Simulation time 443070926 ps
CPU time 1.25 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:25 PM PDT 24
Peak memory 201716 kb
Host smart-f3b7a8f7-8fde-42db-a68d-a3954b2a671a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538889100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1538889100
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3261186284
Short name T804
Test name
Test status
Simulation time 422386713 ps
CPU time 0.9 seconds
Started May 16 02:39:18 PM PDT 24
Finished May 16 02:39:20 PM PDT 24
Peak memory 201664 kb
Host smart-04a1564f-2d09-40d1-b0f6-73f361e171c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261186284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3261186284
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1448840631
Short name T822
Test name
Test status
Simulation time 4014201968 ps
CPU time 14.18 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:38 PM PDT 24
Peak memory 202004 kb
Host smart-4241fd51-77ba-4404-b54f-accc25e0e55f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448840631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1448840631
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1799570157
Short name T851
Test name
Test status
Simulation time 513631027 ps
CPU time 2.08 seconds
Started May 16 02:39:18 PM PDT 24
Finished May 16 02:39:22 PM PDT 24
Peak memory 201840 kb
Host smart-935e5cf9-9c01-4ca3-be92-dbe24265d68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799570157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1799570157
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.30920521
Short name T879
Test name
Test status
Simulation time 4684677285 ps
CPU time 13.18 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:34 PM PDT 24
Peak memory 201916 kb
Host smart-be597885-4f27-420d-b015-a4d9ff693aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30920521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg
_err.30920521
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1683586579
Short name T886
Test name
Test status
Simulation time 457184286 ps
CPU time 1.7 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201580 kb
Host smart-16486155-3323-4322-bed3-967b2bbd41a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683586579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1683586579
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2631278013
Short name T890
Test name
Test status
Simulation time 452898036 ps
CPU time 0.92 seconds
Started May 16 02:39:48 PM PDT 24
Finished May 16 02:39:53 PM PDT 24
Peak memory 201672 kb
Host smart-0c35cc0c-d552-458c-a2e5-e7765055dc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631278013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2631278013
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1096220102
Short name T835
Test name
Test status
Simulation time 338978068 ps
CPU time 1.45 seconds
Started May 16 02:39:47 PM PDT 24
Finished May 16 02:39:53 PM PDT 24
Peak memory 201608 kb
Host smart-270c7971-891b-4d34-8f59-b51ee4c2ff4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096220102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1096220102
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3918905665
Short name T812
Test name
Test status
Simulation time 501854413 ps
CPU time 1.73 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201660 kb
Host smart-c5280e45-4626-4b21-bea0-6f1c41666f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918905665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3918905665
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1123458189
Short name T863
Test name
Test status
Simulation time 442273617 ps
CPU time 1.67 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:51 PM PDT 24
Peak memory 201660 kb
Host smart-fea0654d-beee-4cfe-9b42-65cb378bfaeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123458189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1123458189
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1751295688
Short name T815
Test name
Test status
Simulation time 486263018 ps
CPU time 1.83 seconds
Started May 16 02:39:46 PM PDT 24
Finished May 16 02:39:52 PM PDT 24
Peak memory 201700 kb
Host smart-901f8feb-14f6-423c-87f5-e9c851bde38f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751295688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1751295688
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2525834567
Short name T892
Test name
Test status
Simulation time 319484964 ps
CPU time 1.39 seconds
Started May 16 02:39:47 PM PDT 24
Finished May 16 02:39:53 PM PDT 24
Peak memory 201616 kb
Host smart-544c79e4-60fe-4fb1-95c4-ac48ddcf0109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525834567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2525834567
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3637781807
Short name T864
Test name
Test status
Simulation time 527013380 ps
CPU time 0.77 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:49 PM PDT 24
Peak memory 201692 kb
Host smart-b550f174-0acd-435c-a0f6-e21ec0cfb004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637781807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3637781807
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2787086093
Short name T893
Test name
Test status
Simulation time 339089073 ps
CPU time 1.48 seconds
Started May 16 02:39:45 PM PDT 24
Finished May 16 02:39:50 PM PDT 24
Peak memory 201640 kb
Host smart-0bd1ca44-b429-426e-804a-4ae33df8ce7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787086093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2787086093
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.960332934
Short name T843
Test name
Test status
Simulation time 513347493 ps
CPU time 1.25 seconds
Started May 16 02:39:56 PM PDT 24
Finished May 16 02:40:04 PM PDT 24
Peak memory 201648 kb
Host smart-ff606562-2b68-453f-8839-ebc1f6bf2547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960332934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.960332934
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.148407109
Short name T113
Test name
Test status
Simulation time 827809207 ps
CPU time 3.16 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:27 PM PDT 24
Peak memory 201884 kb
Host smart-57ba2bbb-024a-49e1-a724-c9580b5104bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148407109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.148407109
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2496669469
Short name T866
Test name
Test status
Simulation time 27263662706 ps
CPU time 17.03 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:42 PM PDT 24
Peak memory 201960 kb
Host smart-4c6bcc10-3de1-4968-b18b-f0f631d71533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496669469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2496669469
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2022700523
Short name T905
Test name
Test status
Simulation time 788115882 ps
CPU time 2.38 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:25 PM PDT 24
Peak memory 201672 kb
Host smart-aac99dc8-83f3-43d1-931d-af5c30eb4109
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022700523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2022700523
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.709095782
Short name T848
Test name
Test status
Simulation time 454276420 ps
CPU time 1.37 seconds
Started May 16 02:39:18 PM PDT 24
Finished May 16 02:39:21 PM PDT 24
Peak memory 201732 kb
Host smart-a1aa0efb-6aee-4b2a-8e55-3994145cc1ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709095782 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.709095782
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.771769075
Short name T117
Test name
Test status
Simulation time 418426003 ps
CPU time 0.94 seconds
Started May 16 02:39:23 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 201652 kb
Host smart-065d724d-2179-4156-b3bf-db70bd537966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771769075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.771769075
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2043777965
Short name T896
Test name
Test status
Simulation time 525836070 ps
CPU time 1.87 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:23 PM PDT 24
Peak memory 201688 kb
Host smart-c17c4d38-18ba-4fff-96d6-7838abf200cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043777965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2043777965
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2292783578
Short name T118
Test name
Test status
Simulation time 2179525923 ps
CPU time 6.3 seconds
Started May 16 02:39:18 PM PDT 24
Finished May 16 02:39:27 PM PDT 24
Peak memory 201740 kb
Host smart-4a9f0236-2ad0-49cf-adc6-5b2945cf34a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292783578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2292783578
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1019392993
Short name T860
Test name
Test status
Simulation time 459577478 ps
CPU time 2.25 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:26 PM PDT 24
Peak memory 201944 kb
Host smart-ba73984a-1467-43fb-ae96-73c2e7b809dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019392993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1019392993
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3897238604
Short name T57
Test name
Test status
Simulation time 4024503497 ps
CPU time 11.9 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:35 PM PDT 24
Peak memory 201912 kb
Host smart-5dc5168e-0213-40c7-847a-46907e07f0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897238604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3897238604
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1764601711
Short name T903
Test name
Test status
Simulation time 347858348 ps
CPU time 0.71 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:04 PM PDT 24
Peak memory 201660 kb
Host smart-f0c5d4c0-e536-47ef-9aef-b91236c2b780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764601711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1764601711
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1434848971
Short name T878
Test name
Test status
Simulation time 322059690 ps
CPU time 1.35 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:40:01 PM PDT 24
Peak memory 201724 kb
Host smart-e8730456-4fbc-46d2-b191-af43ff4288e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434848971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1434848971
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3499638315
Short name T916
Test name
Test status
Simulation time 334066219 ps
CPU time 1.42 seconds
Started May 16 02:39:53 PM PDT 24
Finished May 16 02:39:59 PM PDT 24
Peak memory 201584 kb
Host smart-971c7d81-c364-4d74-b9e3-d1976cbcf994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499638315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3499638315
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1128595452
Short name T888
Test name
Test status
Simulation time 391726134 ps
CPU time 0.86 seconds
Started May 16 02:39:54 PM PDT 24
Finished May 16 02:40:00 PM PDT 24
Peak memory 201700 kb
Host smart-7964e2c4-7870-4be9-b0e5-402e646aac31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128595452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1128595452
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2967166155
Short name T830
Test name
Test status
Simulation time 316569248 ps
CPU time 0.84 seconds
Started May 16 02:39:58 PM PDT 24
Finished May 16 02:40:05 PM PDT 24
Peak memory 201652 kb
Host smart-76d0d770-4acf-47dd-a7e6-e358e1799289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967166155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2967166155
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2403641656
Short name T807
Test name
Test status
Simulation time 534014638 ps
CPU time 0.86 seconds
Started May 16 02:39:53 PM PDT 24
Finished May 16 02:39:57 PM PDT 24
Peak memory 201668 kb
Host smart-761777f6-19ed-4c75-8a6b-da6ab9bf08f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403641656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2403641656
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3190711349
Short name T801
Test name
Test status
Simulation time 478762234 ps
CPU time 1.19 seconds
Started May 16 02:39:54 PM PDT 24
Finished May 16 02:39:59 PM PDT 24
Peak memory 201660 kb
Host smart-b467f056-b6d5-43fa-b251-a90d869ba882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190711349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3190711349
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.813196639
Short name T910
Test name
Test status
Simulation time 491664682 ps
CPU time 1.22 seconds
Started May 16 02:39:54 PM PDT 24
Finished May 16 02:40:00 PM PDT 24
Peak memory 201656 kb
Host smart-1ec47bc2-1baf-40de-86a3-32f2cbbf11d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813196639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.813196639
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2379725038
Short name T806
Test name
Test status
Simulation time 443063260 ps
CPU time 1.65 seconds
Started May 16 02:39:57 PM PDT 24
Finished May 16 02:40:05 PM PDT 24
Peak memory 201660 kb
Host smart-efb4adcc-b539-4197-8d33-d4b21b80899f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379725038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2379725038
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.278093433
Short name T821
Test name
Test status
Simulation time 399429357 ps
CPU time 1.11 seconds
Started May 16 02:39:55 PM PDT 24
Finished May 16 02:40:01 PM PDT 24
Peak memory 201672 kb
Host smart-da5eb858-6e3f-4a27-92f8-001041b7af46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278093433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.278093433
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2922690694
Short name T917
Test name
Test status
Simulation time 613011523 ps
CPU time 1.42 seconds
Started May 16 02:39:24 PM PDT 24
Finished May 16 02:39:30 PM PDT 24
Peak memory 201724 kb
Host smart-e01c1914-fcb4-4e84-be75-fc7b56da7645
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922690694 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2922690694
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4184709341
Short name T882
Test name
Test status
Simulation time 401132863 ps
CPU time 1.22 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:24 PM PDT 24
Peak memory 201736 kb
Host smart-ca7d0c36-7333-4a1f-9c1c-5deb9fa8e496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184709341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4184709341
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1297109471
Short name T845
Test name
Test status
Simulation time 382935261 ps
CPU time 0.86 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:23 PM PDT 24
Peak memory 201624 kb
Host smart-6ab37413-5eaa-4c32-a9d3-12e1029bb983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297109471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1297109471
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1933122100
Short name T824
Test name
Test status
Simulation time 4313179456 ps
CPU time 16.43 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:39 PM PDT 24
Peak memory 202048 kb
Host smart-cfff4242-2079-4f30-8e29-a782bbb269f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933122100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1933122100
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2294661465
Short name T62
Test name
Test status
Simulation time 532034435 ps
CPU time 3.07 seconds
Started May 16 02:39:18 PM PDT 24
Finished May 16 02:39:22 PM PDT 24
Peak memory 210180 kb
Host smart-d5b2949d-6150-44c5-8db2-e119e9943de6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294661465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2294661465
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2210690239
Short name T100
Test name
Test status
Simulation time 4791824910 ps
CPU time 9.08 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:31 PM PDT 24
Peak memory 201992 kb
Host smart-08eb7b3e-ff42-434d-8377-dcc85262ecf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210690239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2210690239
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1056913723
Short name T840
Test name
Test status
Simulation time 437431068 ps
CPU time 1.97 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:26 PM PDT 24
Peak memory 201788 kb
Host smart-4ea61806-7cca-4051-8363-d70499883af3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056913723 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1056913723
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4172319285
Short name T115
Test name
Test status
Simulation time 433459426 ps
CPU time 1.78 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:25 PM PDT 24
Peak memory 201736 kb
Host smart-7f4a80b2-d18b-4bf0-b8db-42fcd62e0464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172319285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4172319285
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1164280734
Short name T817
Test name
Test status
Simulation time 483153540 ps
CPU time 1.77 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:24 PM PDT 24
Peak memory 201680 kb
Host smart-a3fc24a3-c17b-487c-831d-44669f8ed1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164280734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1164280734
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.444292318
Short name T862
Test name
Test status
Simulation time 4984332098 ps
CPU time 6.2 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:29 PM PDT 24
Peak memory 201912 kb
Host smart-2063ecb4-c2f7-4b7b-9031-9ed0bbb68592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444292318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.444292318
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3862704401
Short name T871
Test name
Test status
Simulation time 502302234 ps
CPU time 2.67 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:25 PM PDT 24
Peak memory 201964 kb
Host smart-a9b77458-6676-4480-8217-2b9bb7147792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862704401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3862704401
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3462833392
Short name T870
Test name
Test status
Simulation time 8257493498 ps
CPU time 6.67 seconds
Started May 16 02:39:21 PM PDT 24
Finished May 16 02:39:32 PM PDT 24
Peak memory 202016 kb
Host smart-48965114-005e-40f3-944d-c78b3ea1d9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462833392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3462833392
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2173811809
Short name T901
Test name
Test status
Simulation time 495739997 ps
CPU time 1.37 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 201756 kb
Host smart-ab1e7e0e-5c5f-495f-a767-0824eae95b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173811809 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2173811809
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1369362556
Short name T852
Test name
Test status
Simulation time 653216709 ps
CPU time 0.81 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:26 PM PDT 24
Peak memory 201424 kb
Host smart-12ecbc04-bb51-40ae-a486-625c567b23f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369362556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1369362556
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.219967768
Short name T808
Test name
Test status
Simulation time 339886859 ps
CPU time 1.44 seconds
Started May 16 02:39:19 PM PDT 24
Finished May 16 02:39:24 PM PDT 24
Peak memory 201688 kb
Host smart-986757d7-fee2-4341-b9cb-b87441d19b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219967768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.219967768
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2073173432
Short name T894
Test name
Test status
Simulation time 4640465114 ps
CPU time 15.98 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:40 PM PDT 24
Peak memory 201876 kb
Host smart-9de45936-208a-4efc-a76c-a031ced440d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073173432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2073173432
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2897192218
Short name T836
Test name
Test status
Simulation time 576512247 ps
CPU time 2.9 seconds
Started May 16 02:39:20 PM PDT 24
Finished May 16 02:39:27 PM PDT 24
Peak memory 218336 kb
Host smart-0d8b4fcb-f666-4943-b6eb-27394466c6a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897192218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2897192218
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1408660888
Short name T63
Test name
Test status
Simulation time 4392931769 ps
CPU time 7.16 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:33 PM PDT 24
Peak memory 201956 kb
Host smart-af882a32-631c-43e2-ac75-7332a8ed83a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408660888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1408660888
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.882077152
Short name T99
Test name
Test status
Simulation time 354444052 ps
CPU time 1.62 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 201732 kb
Host smart-c9af8455-955a-49e5-9a19-23e90bd3dbf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882077152 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.882077152
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1146246396
Short name T829
Test name
Test status
Simulation time 375015330 ps
CPU time 1.62 seconds
Started May 16 02:39:24 PM PDT 24
Finished May 16 02:39:30 PM PDT 24
Peak memory 201660 kb
Host smart-3cafdd8e-7553-4a09-88f2-2020213fa766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146246396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1146246396
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3115185705
Short name T889
Test name
Test status
Simulation time 466834013 ps
CPU time 0.86 seconds
Started May 16 02:39:23 PM PDT 24
Finished May 16 02:39:27 PM PDT 24
Peak memory 201684 kb
Host smart-9926f573-3ecf-4ca0-b003-424b18aa3b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115185705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3115185705
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3637397777
Short name T827
Test name
Test status
Simulation time 2273996104 ps
CPU time 5.5 seconds
Started May 16 02:39:23 PM PDT 24
Finished May 16 02:39:33 PM PDT 24
Peak memory 201752 kb
Host smart-d73dd303-10a5-4679-90da-12cb1d9d2286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637397777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3637397777
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4294629881
Short name T884
Test name
Test status
Simulation time 509308432 ps
CPU time 2.86 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 218308 kb
Host smart-9fec5d7c-2396-4315-b2a2-5267a5fa71ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294629881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.4294629881
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1468780294
Short name T857
Test name
Test status
Simulation time 4685846305 ps
CPU time 2.73 seconds
Started May 16 02:39:21 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 201952 kb
Host smart-1b41a1b1-13cb-4f94-88f8-3726ddb6db43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468780294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1468780294
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.856840251
Short name T898
Test name
Test status
Simulation time 455683319 ps
CPU time 2 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:27 PM PDT 24
Peak memory 201692 kb
Host smart-750c1071-c627-483f-85a7-2c13b759c9ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856840251 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.856840251
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1074308716
Short name T832
Test name
Test status
Simulation time 413412747 ps
CPU time 0.87 seconds
Started May 16 02:39:25 PM PDT 24
Finished May 16 02:39:30 PM PDT 24
Peak memory 201688 kb
Host smart-2f7d2b58-506c-4cc1-b7b5-a7aae81b78cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074308716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1074308716
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.563333645
Short name T872
Test name
Test status
Simulation time 360017710 ps
CPU time 0.86 seconds
Started May 16 02:39:21 PM PDT 24
Finished May 16 02:39:25 PM PDT 24
Peak memory 201548 kb
Host smart-4e318d45-a330-453a-9785-6f8380e6780e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563333645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.563333645
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1221793436
Short name T826
Test name
Test status
Simulation time 4657116300 ps
CPU time 6.28 seconds
Started May 16 02:39:23 PM PDT 24
Finished May 16 02:39:34 PM PDT 24
Peak memory 201956 kb
Host smart-d9f9105f-95f0-42e2-b836-5a29b099dd22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221793436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1221793436
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1986103182
Short name T880
Test name
Test status
Simulation time 406651447 ps
CPU time 1.83 seconds
Started May 16 02:39:22 PM PDT 24
Finished May 16 02:39:28 PM PDT 24
Peak memory 201964 kb
Host smart-b7fab2cc-563f-446e-b4c6-575e23897eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986103182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1986103182
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2208903644
Short name T468
Test name
Test status
Simulation time 521109467 ps
CPU time 0.96 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:05:35 PM PDT 24
Peak memory 201508 kb
Host smart-1f6cb5aa-ac98-4e79-ae0d-f5d72718fc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208903644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2208903644
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3750019511
Short name T276
Test name
Test status
Simulation time 329832986947 ps
CPU time 362.22 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:11:38 PM PDT 24
Peak memory 201784 kb
Host smart-260e5f0e-7448-4a94-8e02-df92c535b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750019511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3750019511
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.138204458
Short name T576
Test name
Test status
Simulation time 496431155370 ps
CPU time 1097.92 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:23:53 PM PDT 24
Peak memory 201816 kb
Host smart-5a02f2dc-b946-4de0-8435-4534eba4c115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138204458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.138204458
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.279794422
Short name T477
Test name
Test status
Simulation time 492726757479 ps
CPU time 1172.69 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:25:07 PM PDT 24
Peak memory 201688 kb
Host smart-559b88c9-897f-4bff-92ca-20143210bef2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=279794422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.279794422
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.153048568
Short name T746
Test name
Test status
Simulation time 320835897917 ps
CPU time 653.91 seconds
Started May 16 02:05:22 PM PDT 24
Finished May 16 02:16:20 PM PDT 24
Peak memory 201792 kb
Host smart-cb412aee-8c94-4591-ad73-fdb8a5f28c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153048568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.153048568
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3604801801
Short name T563
Test name
Test status
Simulation time 490218227096 ps
CPU time 261.88 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:09:58 PM PDT 24
Peak memory 201848 kb
Host smart-237b0e76-0667-4e8b-a33f-0fb2e496627f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604801801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3604801801
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.762493155
Short name T716
Test name
Test status
Simulation time 366517862609 ps
CPU time 407.72 seconds
Started May 16 02:05:37 PM PDT 24
Finished May 16 02:12:26 PM PDT 24
Peak memory 201900 kb
Host smart-52eb642e-9b52-4eb2-8612-5acbba8d1aec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762493155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.762493155
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.284685513
Short name T377
Test name
Test status
Simulation time 580070652299 ps
CPU time 320.46 seconds
Started May 16 02:05:37 PM PDT 24
Finished May 16 02:10:59 PM PDT 24
Peak memory 201800 kb
Host smart-74f0840b-d252-4a16-80a5-1f9b2d0bd5a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284685513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.284685513
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2083418913
Short name T609
Test name
Test status
Simulation time 112865877646 ps
CPU time 422.72 seconds
Started May 16 02:05:35 PM PDT 24
Finished May 16 02:12:40 PM PDT 24
Peak memory 202192 kb
Host smart-1649c796-982c-4ac7-bfe1-40449b189aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083418913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2083418913
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.34698334
Short name T152
Test name
Test status
Simulation time 43135166294 ps
CPU time 24.75 seconds
Started May 16 02:05:38 PM PDT 24
Finished May 16 02:06:04 PM PDT 24
Peak memory 201648 kb
Host smart-6f699512-89b5-4f2b-9164-863cc8981fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34698334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.34698334
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3512441830
Short name T358
Test name
Test status
Simulation time 4905781649 ps
CPU time 5.98 seconds
Started May 16 02:05:31 PM PDT 24
Finished May 16 02:05:40 PM PDT 24
Peak memory 201656 kb
Host smart-7c628b5c-3c3c-4655-837d-677bda206b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512441830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3512441830
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3137045020
Short name T378
Test name
Test status
Simulation time 5748885084 ps
CPU time 3.93 seconds
Started May 16 02:05:23 PM PDT 24
Finished May 16 02:05:31 PM PDT 24
Peak memory 201624 kb
Host smart-ba0b411b-6248-423f-8792-0a5dc07b3e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137045020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3137045020
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1515401928
Short name T348
Test name
Test status
Simulation time 398320730516 ps
CPU time 759.23 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:18:15 PM PDT 24
Peak memory 202060 kb
Host smart-4391928e-8414-4528-8bad-957030ce4010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515401928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1515401928
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1223249237
Short name T23
Test name
Test status
Simulation time 437463808955 ps
CPU time 491.23 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:13:47 PM PDT 24
Peak memory 210440 kb
Host smart-3d1e1ce4-d62a-4c1c-8806-1a69240a3556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223249237 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1223249237
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4200394468
Short name T783
Test name
Test status
Simulation time 502850662 ps
CPU time 1.25 seconds
Started May 16 02:05:40 PM PDT 24
Finished May 16 02:05:43 PM PDT 24
Peak memory 201312 kb
Host smart-cd881a1c-9ae9-44f6-8be9-0b2eb1302e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200394468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4200394468
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1987997560
Short name T308
Test name
Test status
Simulation time 167677304543 ps
CPU time 373.15 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:11:49 PM PDT 24
Peak memory 201864 kb
Host smart-be95c23d-0b4b-41b1-9b0b-38df9b67f1c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987997560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1987997560
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4278223533
Short name T240
Test name
Test status
Simulation time 161666442622 ps
CPU time 128.26 seconds
Started May 16 02:05:31 PM PDT 24
Finished May 16 02:07:42 PM PDT 24
Peak memory 201720 kb
Host smart-454e2b3a-cca8-4788-b0db-5bb6d694f7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278223533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4278223533
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.257733262
Short name T130
Test name
Test status
Simulation time 322123075958 ps
CPU time 166.67 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:08:30 PM PDT 24
Peak memory 201860 kb
Host smart-97d1d937-adb1-4300-aeab-3a7b0ed62468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257733262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.257733262
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2997632804
Short name T511
Test name
Test status
Simulation time 487493779834 ps
CPU time 555.03 seconds
Started May 16 02:05:37 PM PDT 24
Finished May 16 02:14:53 PM PDT 24
Peak memory 201892 kb
Host smart-40c3ce6f-4dcc-4198-bad6-d69303e216dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997632804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2997632804
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3133146642
Short name T777
Test name
Test status
Simulation time 167103071199 ps
CPU time 91.62 seconds
Started May 16 02:05:31 PM PDT 24
Finished May 16 02:07:05 PM PDT 24
Peak memory 201840 kb
Host smart-13712709-6038-486b-b3dc-8031a8e7eb36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133146642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3133146642
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4034629669
Short name T458
Test name
Test status
Simulation time 199741024574 ps
CPU time 475.2 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:13:38 PM PDT 24
Peak memory 201784 kb
Host smart-93f6c89c-2317-453c-83bc-20e36f662160
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034629669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4034629669
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2596618292
Short name T646
Test name
Test status
Simulation time 81381465248 ps
CPU time 394.91 seconds
Started May 16 02:05:27 PM PDT 24
Finished May 16 02:12:04 PM PDT 24
Peak memory 202040 kb
Host smart-6ad89f13-18ab-4dc2-b58a-e79367f9c92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596618292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2596618292
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3903426845
Short name T355
Test name
Test status
Simulation time 23467508653 ps
CPU time 53.49 seconds
Started May 16 02:05:36 PM PDT 24
Finished May 16 02:06:31 PM PDT 24
Peak memory 201668 kb
Host smart-d50a1736-5d5e-43f0-9af9-fa865c14f22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903426845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3903426845
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.919632544
Short name T485
Test name
Test status
Simulation time 3798680559 ps
CPU time 2.8 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:05:45 PM PDT 24
Peak memory 201504 kb
Host smart-2f14503f-07ee-4d6b-9c2a-64c67e743113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919632544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.919632544
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.787146413
Short name T66
Test name
Test status
Simulation time 8085240003 ps
CPU time 5.78 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:05:39 PM PDT 24
Peak memory 218416 kb
Host smart-9225e798-83ca-4151-a4b2-5bf8cf6538d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787146413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.787146413
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4226496917
Short name T374
Test name
Test status
Simulation time 5831201313 ps
CPU time 5.89 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:05:48 PM PDT 24
Peak memory 201672 kb
Host smart-45dfd333-8d3b-491a-830f-c4fb67bc9731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226496917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4226496917
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1674989895
Short name T86
Test name
Test status
Simulation time 239664130669 ps
CPU time 772.71 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:18:29 PM PDT 24
Peak memory 202136 kb
Host smart-da446a3b-c4fd-470e-8c43-841ffa0d608c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674989895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1674989895
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.332535212
Short name T552
Test name
Test status
Simulation time 461365879759 ps
CPU time 527.63 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:14:22 PM PDT 24
Peak memory 210436 kb
Host smart-9c66192b-95b0-44af-911d-86aadae50cfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332535212 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.332535212
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2452125328
Short name T521
Test name
Test status
Simulation time 482765268 ps
CPU time 0.89 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:06:10 PM PDT 24
Peak memory 201520 kb
Host smart-5534c37b-cb57-4456-8228-d695140352ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452125328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2452125328
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.62137550
Short name T581
Test name
Test status
Simulation time 369713355513 ps
CPU time 79.15 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:07:29 PM PDT 24
Peak memory 201804 kb
Host smart-f03fb158-b842-4414-81a3-727c2643953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62137550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.62137550
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1673454129
Short name T302
Test name
Test status
Simulation time 486894516170 ps
CPU time 79.57 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:07:29 PM PDT 24
Peak memory 201840 kb
Host smart-e263de31-4b02-4086-aa2c-17ebd205a021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673454129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1673454129
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1479377041
Short name T460
Test name
Test status
Simulation time 496550752296 ps
CPU time 198.32 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:09:32 PM PDT 24
Peak memory 201924 kb
Host smart-4a1a17ce-4d35-485c-af91-f0542ae48e4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479377041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1479377041
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3330134019
Short name T703
Test name
Test status
Simulation time 490572343147 ps
CPU time 563.63 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:15:33 PM PDT 24
Peak memory 201896 kb
Host smart-b94a72eb-e462-465e-8523-6608c805fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330134019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3330134019
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2747332445
Short name T28
Test name
Test status
Simulation time 489350165465 ps
CPU time 617.6 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:16:26 PM PDT 24
Peak memory 201784 kb
Host smart-6a39dcea-a88f-47b5-9202-0b515d95c27c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747332445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2747332445
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3506926875
Short name T373
Test name
Test status
Simulation time 191771037956 ps
CPU time 108.36 seconds
Started May 16 02:06:08 PM PDT 24
Finished May 16 02:08:01 PM PDT 24
Peak memory 201728 kb
Host smart-342f2a73-9716-4431-9ede-db5f5e27ca2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506926875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3506926875
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2738661071
Short name T555
Test name
Test status
Simulation time 93417462031 ps
CPU time 289.38 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:10:58 PM PDT 24
Peak memory 202284 kb
Host smart-b9e31a60-3833-4161-8560-456f4f73cadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738661071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2738661071
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1880741447
Short name T426
Test name
Test status
Simulation time 40673923617 ps
CPU time 97.56 seconds
Started May 16 02:06:05 PM PDT 24
Finished May 16 02:07:46 PM PDT 24
Peak memory 201604 kb
Host smart-cfd7e606-14cf-4271-a640-d8fdb8090579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880741447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1880741447
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4201261359
Short name T745
Test name
Test status
Simulation time 3664607607 ps
CPU time 4.96 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:06:19 PM PDT 24
Peak memory 201544 kb
Host smart-87291dfb-ca4d-4d34-8410-12e7d3bf90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201261359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4201261359
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.539019118
Short name T747
Test name
Test status
Simulation time 5809751593 ps
CPU time 15.46 seconds
Started May 16 02:06:09 PM PDT 24
Finished May 16 02:06:29 PM PDT 24
Peak memory 201572 kb
Host smart-7ec04e46-9f3c-4f96-b6ba-1d5a9edde046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539019118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.539019118
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1682157568
Short name T587
Test name
Test status
Simulation time 62870283394 ps
CPU time 75.07 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:07:30 PM PDT 24
Peak memory 210116 kb
Host smart-cfc9f421-0c7a-4fd9-898d-71aa11166f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682157568 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1682157568
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.827502844
Short name T546
Test name
Test status
Simulation time 415841232 ps
CPU time 1.55 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:06:16 PM PDT 24
Peak memory 201528 kb
Host smart-a033058b-c49d-43f6-a241-76996c1bfe33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827502844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.827502844
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3276217222
Short name T250
Test name
Test status
Simulation time 161793064798 ps
CPU time 190.79 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:09:25 PM PDT 24
Peak memory 201788 kb
Host smart-9bebee55-4c6a-4f46-9de1-717e08f6342d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276217222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3276217222
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2749377651
Short name T30
Test name
Test status
Simulation time 444520837880 ps
CPU time 92.18 seconds
Started May 16 02:06:09 PM PDT 24
Finished May 16 02:07:45 PM PDT 24
Peak memory 201796 kb
Host smart-38e85702-d8b3-431b-a31e-25033959fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749377651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2749377651
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3303807082
Short name T440
Test name
Test status
Simulation time 163147959822 ps
CPU time 401.65 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:12:53 PM PDT 24
Peak memory 201808 kb
Host smart-7b9a4b24-7917-4384-82dd-7cf012f25e56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303807082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3303807082
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3570283183
Short name T288
Test name
Test status
Simulation time 486062195709 ps
CPU time 1150.44 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:25:22 PM PDT 24
Peak memory 201776 kb
Host smart-fa546851-b956-49ac-aa16-e05b290344ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570283183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3570283183
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1686851462
Short name T682
Test name
Test status
Simulation time 323424399455 ps
CPU time 726.63 seconds
Started May 16 02:06:05 PM PDT 24
Finished May 16 02:18:15 PM PDT 24
Peak memory 201800 kb
Host smart-b02c28c8-7b5b-4a93-8d78-7ac4b48de180
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686851462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1686851462
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1586257417
Short name T137
Test name
Test status
Simulation time 180476575367 ps
CPU time 23.58 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:06:38 PM PDT 24
Peak memory 201872 kb
Host smart-7dc970da-8d17-43dc-b971-0db7eeeca2bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586257417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1586257417
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1537604062
Short name T641
Test name
Test status
Simulation time 615626469983 ps
CPU time 730.48 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:18:20 PM PDT 24
Peak memory 201812 kb
Host smart-ca831869-8e00-471e-9100-3eb2db8d73b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537604062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1537604062
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1520702367
Short name T47
Test name
Test status
Simulation time 118958031441 ps
CPU time 478.96 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:14:13 PM PDT 24
Peak memory 202144 kb
Host smart-b4789506-f718-4bde-975c-000818b67310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520702367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1520702367
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3930994309
Short name T419
Test name
Test status
Simulation time 33688699398 ps
CPU time 24.87 seconds
Started May 16 02:06:05 PM PDT 24
Finished May 16 02:06:33 PM PDT 24
Peak memory 201644 kb
Host smart-9c14843a-72de-4b77-86cc-2406ba9328fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930994309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3930994309
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2846006682
Short name T486
Test name
Test status
Simulation time 2713675396 ps
CPU time 7.2 seconds
Started May 16 02:06:08 PM PDT 24
Finished May 16 02:06:20 PM PDT 24
Peak memory 201532 kb
Host smart-6a09cc2f-b052-44f5-baba-6079e76e3e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846006682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2846006682
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2169999264
Short name T469
Test name
Test status
Simulation time 5765568469 ps
CPU time 14.81 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:06:24 PM PDT 24
Peak memory 201636 kb
Host smart-4be708a2-73fe-4a0a-a67f-77510a3f3fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169999264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2169999264
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4076735834
Short name T295
Test name
Test status
Simulation time 229209047257 ps
CPU time 330.49 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:11:42 PM PDT 24
Peak memory 201824 kb
Host smart-52c696fc-a1d4-4cc2-aa5e-8885134a5efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076735834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4076735834
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1899288606
Short name T20
Test name
Test status
Simulation time 203185837372 ps
CPU time 121.88 seconds
Started May 16 02:06:09 PM PDT 24
Finished May 16 02:08:15 PM PDT 24
Peak memory 210196 kb
Host smart-50e714e5-c580-4941-9655-9a4ca419de2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899288606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1899288606
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.913113201
Short name T428
Test name
Test status
Simulation time 367970709 ps
CPU time 1.02 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:06:24 PM PDT 24
Peak memory 201420 kb
Host smart-f70aafc1-6181-4464-95f6-3f1ca013ae81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913113201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.913113201
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.399341569
Short name T707
Test name
Test status
Simulation time 171508749492 ps
CPU time 58.84 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:07:21 PM PDT 24
Peak memory 201824 kb
Host smart-4736b97a-6d22-499e-bf70-72ba0653e0b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399341569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.399341569
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1732974494
Short name T243
Test name
Test status
Simulation time 164232751884 ps
CPU time 389.22 seconds
Started May 16 02:06:20 PM PDT 24
Finished May 16 02:12:50 PM PDT 24
Peak memory 201912 kb
Host smart-93b9f5e3-0710-4b27-bfc2-166432617629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732974494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1732974494
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2910954395
Short name T422
Test name
Test status
Simulation time 489559077766 ps
CPU time 545.32 seconds
Started May 16 02:06:28 PM PDT 24
Finished May 16 02:15:35 PM PDT 24
Peak memory 201808 kb
Host smart-ab5de84d-0226-4544-95b4-4a08a12a92e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910954395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2910954395
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.256415820
Short name T507
Test name
Test status
Simulation time 329636573103 ps
CPU time 209.45 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:09:44 PM PDT 24
Peak memory 201844 kb
Host smart-83a8f398-e9a0-4991-be1c-1867314d4ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256415820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.256415820
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3336656203
Short name T795
Test name
Test status
Simulation time 330395864407 ps
CPU time 748.51 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:19:03 PM PDT 24
Peak memory 201800 kb
Host smart-acd7a6c5-2649-4797-8cfe-011bfa0e1fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336656203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3336656203
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3104151027
Short name T598
Test name
Test status
Simulation time 196981120583 ps
CPU time 404.18 seconds
Started May 16 02:06:20 PM PDT 24
Finished May 16 02:13:05 PM PDT 24
Peak memory 201848 kb
Host smart-8f3d0eb0-e9a0-4356-baf3-31d5b9ecba4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104151027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3104151027
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1439509386
Short name T577
Test name
Test status
Simulation time 593207362744 ps
CPU time 710.8 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:18:13 PM PDT 24
Peak memory 201880 kb
Host smart-b8a6cba7-010f-44cb-ad62-6a55bd0e5239
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439509386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1439509386
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1936548266
Short name T567
Test name
Test status
Simulation time 108965816849 ps
CPU time 621.91 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:16:44 PM PDT 24
Peak memory 202200 kb
Host smart-d64c8db4-a04a-4294-a6c8-eddb39afd252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936548266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1936548266
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2753162845
Short name T586
Test name
Test status
Simulation time 28635849388 ps
CPU time 28.56 seconds
Started May 16 02:06:22 PM PDT 24
Finished May 16 02:06:51 PM PDT 24
Peak memory 201664 kb
Host smart-bc2c7791-a670-4b38-bee1-8672e0ceefb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753162845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2753162845
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.217421411
Short name T400
Test name
Test status
Simulation time 3639005463 ps
CPU time 4.78 seconds
Started May 16 02:06:20 PM PDT 24
Finished May 16 02:06:26 PM PDT 24
Peak memory 201576 kb
Host smart-fb88a3fb-a1a3-4c55-a930-75fc02dea9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217421411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.217421411
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3706438548
Short name T1
Test name
Test status
Simulation time 5849612886 ps
CPU time 4.41 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:06:18 PM PDT 24
Peak memory 201688 kb
Host smart-a63fb933-b3f4-48f6-946b-cb1bcf14d18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706438548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3706438548
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2739414317
Short name T642
Test name
Test status
Simulation time 178315593001 ps
CPU time 11.69 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:06:46 PM PDT 24
Peak memory 201828 kb
Host smart-458014a7-60e1-4445-9126-d914d4cc19de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739414317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2739414317
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.227916947
Short name T337
Test name
Test status
Simulation time 59098127130 ps
CPU time 66.41 seconds
Started May 16 02:06:26 PM PDT 24
Finished May 16 02:07:34 PM PDT 24
Peak memory 210120 kb
Host smart-412d0b81-31e9-4668-8331-51353d3c0480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227916947 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.227916947
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2299911554
Short name T601
Test name
Test status
Simulation time 291350412 ps
CPU time 0.97 seconds
Started May 16 02:06:30 PM PDT 24
Finished May 16 02:06:33 PM PDT 24
Peak memory 201504 kb
Host smart-5a1338ba-eff4-41cd-b8c1-44040babd8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299911554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2299911554
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1651646417
Short name T272
Test name
Test status
Simulation time 165691472367 ps
CPU time 199.53 seconds
Started May 16 02:06:28 PM PDT 24
Finished May 16 02:09:48 PM PDT 24
Peak memory 201896 kb
Host smart-fdca6249-4329-41fa-a94a-6c3d3aa7d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651646417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1651646417
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.396695419
Short name T489
Test name
Test status
Simulation time 168958285908 ps
CPU time 81.38 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:07:44 PM PDT 24
Peak memory 201780 kb
Host smart-f43ad739-9759-4cfb-a8b2-a570626c3808
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=396695419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.396695419
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.4253815446
Short name T126
Test name
Test status
Simulation time 323767312873 ps
CPU time 59.4 seconds
Started May 16 02:06:28 PM PDT 24
Finished May 16 02:07:29 PM PDT 24
Peak memory 201800 kb
Host smart-9d018096-9848-4865-b7eb-dd8c8bd649ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253815446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.4253815446
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.677413498
Short name T431
Test name
Test status
Simulation time 330538539065 ps
CPU time 103.53 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:08:18 PM PDT 24
Peak memory 201684 kb
Host smart-c1865c4a-fc8a-4e65-9e22-b3c71f5b58aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=677413498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.677413498
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2796469462
Short name T139
Test name
Test status
Simulation time 551238622015 ps
CPU time 244.81 seconds
Started May 16 02:06:18 PM PDT 24
Finished May 16 02:10:23 PM PDT 24
Peak memory 201856 kb
Host smart-d6353364-eeed-44ba-8012-ff80ce711b03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796469462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2796469462
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2745371288
Short name T610
Test name
Test status
Simulation time 394231467979 ps
CPU time 918.83 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:21:53 PM PDT 24
Peak memory 201892 kb
Host smart-7e558409-8dea-40db-ac17-a86c2b561f89
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745371288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2745371288
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3822400707
Short name T95
Test name
Test status
Simulation time 22347286843 ps
CPU time 7.56 seconds
Started May 16 02:06:23 PM PDT 24
Finished May 16 02:06:32 PM PDT 24
Peak memory 201684 kb
Host smart-6745dff7-bc47-4a4f-baa9-2d722abaf317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822400707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3822400707
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4049477772
Short name T792
Test name
Test status
Simulation time 5173726849 ps
CPU time 12.25 seconds
Started May 16 02:06:21 PM PDT 24
Finished May 16 02:06:35 PM PDT 24
Peak memory 201624 kb
Host smart-4696338a-880b-4990-b4d7-d7333f744b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049477772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4049477772
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.86036118
Short name T170
Test name
Test status
Simulation time 5750598194 ps
CPU time 15.35 seconds
Started May 16 02:06:27 PM PDT 24
Finished May 16 02:06:44 PM PDT 24
Peak memory 201644 kb
Host smart-a84029e0-89de-4ddf-9dda-31853c1e4c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86036118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.86036118
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3099985195
Short name T588
Test name
Test status
Simulation time 417210267 ps
CPU time 1.66 seconds
Started May 16 02:06:41 PM PDT 24
Finished May 16 02:06:44 PM PDT 24
Peak memory 201492 kb
Host smart-d09faf3d-5e1b-43c4-a951-24a3c7c1b3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099985195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3099985195
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.739294755
Short name T220
Test name
Test status
Simulation time 160582709251 ps
CPU time 368.5 seconds
Started May 16 02:06:31 PM PDT 24
Finished May 16 02:12:43 PM PDT 24
Peak memory 201776 kb
Host smart-98fc88c8-9bef-4427-a13f-c2185b191b9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739294755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.739294755
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.25472299
Short name T304
Test name
Test status
Simulation time 165281020142 ps
CPU time 394.65 seconds
Started May 16 02:06:30 PM PDT 24
Finished May 16 02:13:07 PM PDT 24
Peak memory 201864 kb
Host smart-c7f6c0c1-9baf-4a49-8b1b-b5cbbea620e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25472299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.25472299
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3700278657
Short name T178
Test name
Test status
Simulation time 326294949135 ps
CPU time 210.22 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:10:05 PM PDT 24
Peak memory 201836 kb
Host smart-ee2d920a-ee58-4950-8b08-b8f2a6cb4951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700278657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3700278657
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.62613560
Short name T791
Test name
Test status
Simulation time 493479537789 ps
CPU time 1157.88 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:25:53 PM PDT 24
Peak memory 201716 kb
Host smart-4075f4c9-679d-4cfe-848d-1ff4ec6f8ffc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=62613560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt
_fixed.62613560
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2294644424
Short name T446
Test name
Test status
Simulation time 337932457284 ps
CPU time 789.63 seconds
Started May 16 02:06:33 PM PDT 24
Finished May 16 02:19:45 PM PDT 24
Peak memory 201780 kb
Host smart-704edce0-96f9-49d2-8a9a-c44900baf4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294644424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2294644424
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3799513487
Short name T474
Test name
Test status
Simulation time 161815221145 ps
CPU time 298.63 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:11:33 PM PDT 24
Peak memory 201920 kb
Host smart-9df38159-a5a1-461b-90a3-0fbf38a354a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799513487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3799513487
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.14922434
Short name T237
Test name
Test status
Simulation time 203353904201 ps
CPU time 117.31 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:08:32 PM PDT 24
Peak memory 201800 kb
Host smart-560519a0-5eac-4fbf-b2fd-fbaad616013a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14922434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_w
akeup.14922434
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1562617419
Short name T376
Test name
Test status
Simulation time 412728615632 ps
CPU time 961.33 seconds
Started May 16 02:06:33 PM PDT 24
Finished May 16 02:22:36 PM PDT 24
Peak memory 201820 kb
Host smart-7dc60a17-2dae-4524-bf0f-dc317c962a7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562617419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1562617419
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1260324340
Short name T742
Test name
Test status
Simulation time 108627689334 ps
CPU time 397.16 seconds
Started May 16 02:06:36 PM PDT 24
Finished May 16 02:13:14 PM PDT 24
Peak memory 202120 kb
Host smart-df05f896-822d-4a81-8142-4668d122ff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260324340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1260324340
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3789877506
Short name T731
Test name
Test status
Simulation time 41667673232 ps
CPU time 87.86 seconds
Started May 16 02:06:33 PM PDT 24
Finished May 16 02:08:03 PM PDT 24
Peak memory 201656 kb
Host smart-965175dd-4b1d-4729-8132-030f6f66c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789877506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3789877506
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2040816807
Short name T380
Test name
Test status
Simulation time 5000227290 ps
CPU time 2.27 seconds
Started May 16 02:06:35 PM PDT 24
Finished May 16 02:06:38 PM PDT 24
Peak memory 201648 kb
Host smart-147ef1b7-3646-40bc-9c97-5757084d4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040816807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2040816807
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.602587713
Short name T706
Test name
Test status
Simulation time 5688254589 ps
CPU time 7.65 seconds
Started May 16 02:06:37 PM PDT 24
Finished May 16 02:06:45 PM PDT 24
Peak memory 201652 kb
Host smart-66f7e663-90cb-4f08-b2bc-dffb2276650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602587713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.602587713
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3446548301
Short name T338
Test name
Test status
Simulation time 665745968579 ps
CPU time 278.27 seconds
Started May 16 02:06:41 PM PDT 24
Finished May 16 02:11:21 PM PDT 24
Peak memory 201844 kb
Host smart-15ec89a5-a827-4a2a-9bdd-ab5c5d624142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446548301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3446548301
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2540013849
Short name T754
Test name
Test status
Simulation time 4308758185503 ps
CPU time 841.73 seconds
Started May 16 02:06:32 PM PDT 24
Finished May 16 02:20:37 PM PDT 24
Peak memory 218180 kb
Host smart-cce2f5e5-a18a-4dde-8659-99130bf3d79f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540013849 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2540013849
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2409053880
Short name T461
Test name
Test status
Simulation time 581930315 ps
CPU time 0.71 seconds
Started May 16 02:06:51 PM PDT 24
Finished May 16 02:06:54 PM PDT 24
Peak memory 201520 kb
Host smart-a718ffa6-8509-4059-8055-e66b87bb41e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409053880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2409053880
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2119170057
Short name T221
Test name
Test status
Simulation time 169535106484 ps
CPU time 383.98 seconds
Started May 16 02:06:40 PM PDT 24
Finished May 16 02:13:05 PM PDT 24
Peak memory 201800 kb
Host smart-13d77dc3-334f-4c67-bb36-f74994040065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119170057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2119170057
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3564748684
Short name T692
Test name
Test status
Simulation time 162431585853 ps
CPU time 185.04 seconds
Started May 16 02:06:44 PM PDT 24
Finished May 16 02:09:50 PM PDT 24
Peak memory 201824 kb
Host smart-cdea49ca-eb04-48fc-9cab-55f47f2c693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564748684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3564748684
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2429717627
Short name T33
Test name
Test status
Simulation time 492526601107 ps
CPU time 1219.45 seconds
Started May 16 02:06:43 PM PDT 24
Finished May 16 02:27:04 PM PDT 24
Peak memory 201812 kb
Host smart-9137e270-bf36-461e-a8e9-a875bd456322
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429717627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2429717627
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.671177912
Short name T259
Test name
Test status
Simulation time 159336101898 ps
CPU time 90.62 seconds
Started May 16 02:06:42 PM PDT 24
Finished May 16 02:08:14 PM PDT 24
Peak memory 201892 kb
Host smart-b8d55286-704a-4bcf-a55f-5d0284446d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671177912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.671177912
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2922181292
Short name T470
Test name
Test status
Simulation time 330673481732 ps
CPU time 206.64 seconds
Started May 16 02:06:40 PM PDT 24
Finished May 16 02:10:09 PM PDT 24
Peak memory 201876 kb
Host smart-e546c6e9-53f0-4e1e-88cf-847f9b918324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922181292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2922181292
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2112666071
Short name T15
Test name
Test status
Simulation time 205809190175 ps
CPU time 483.42 seconds
Started May 16 02:06:42 PM PDT 24
Finished May 16 02:14:47 PM PDT 24
Peak memory 201784 kb
Host smart-f89af31a-4c4e-4d56-8492-dac1e61da93f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112666071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2112666071
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2835386810
Short name T395
Test name
Test status
Simulation time 192589689413 ps
CPU time 122.46 seconds
Started May 16 02:06:41 PM PDT 24
Finished May 16 02:08:45 PM PDT 24
Peak memory 201812 kb
Host smart-875ddc23-e4f8-495e-a1af-86de8b41c1b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835386810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2835386810
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2151008319
Short name T443
Test name
Test status
Simulation time 42209564018 ps
CPU time 51.68 seconds
Started May 16 02:06:40 PM PDT 24
Finished May 16 02:07:33 PM PDT 24
Peak memory 201540 kb
Host smart-949ac9e3-24bf-4a19-b93f-96ab6f12cb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151008319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2151008319
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4164750501
Short name T532
Test name
Test status
Simulation time 4394611779 ps
CPU time 2.89 seconds
Started May 16 02:06:41 PM PDT 24
Finished May 16 02:06:45 PM PDT 24
Peak memory 201656 kb
Host smart-8eb681ea-7ba3-4bf8-8132-612f733c74c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164750501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4164750501
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1881922480
Short name T693
Test name
Test status
Simulation time 5710554877 ps
CPU time 3.47 seconds
Started May 16 02:06:42 PM PDT 24
Finished May 16 02:06:47 PM PDT 24
Peak memory 201660 kb
Host smart-954e452b-6be0-430b-a2e0-1133dd195bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881922480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1881922480
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.4222826821
Short name T744
Test name
Test status
Simulation time 321287865242 ps
CPU time 796.64 seconds
Started May 16 02:06:49 PM PDT 24
Finished May 16 02:20:08 PM PDT 24
Peak memory 201820 kb
Host smart-74c810d1-2498-4b25-9424-37e98458e346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222826821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.4222826821
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.196923789
Short name T595
Test name
Test status
Simulation time 63425870017 ps
CPU time 139.33 seconds
Started May 16 02:06:42 PM PDT 24
Finished May 16 02:09:03 PM PDT 24
Peak memory 210088 kb
Host smart-b14fb877-3783-4505-94bb-50b52b2a8efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196923789 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.196923789
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2835339573
Short name T771
Test name
Test status
Simulation time 372327075 ps
CPU time 0.84 seconds
Started May 16 02:07:05 PM PDT 24
Finished May 16 02:07:07 PM PDT 24
Peak memory 201420 kb
Host smart-f8ac8dc2-1853-43b2-a39e-d678ff318311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835339573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2835339573
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1352320501
Short name T735
Test name
Test status
Simulation time 492015083833 ps
CPU time 257.99 seconds
Started May 16 02:06:51 PM PDT 24
Finished May 16 02:11:11 PM PDT 24
Peak memory 201776 kb
Host smart-096bbb44-c29d-438f-b8bd-1209973458f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352320501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1352320501
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1415695928
Short name T542
Test name
Test status
Simulation time 165631580864 ps
CPU time 392.73 seconds
Started May 16 02:06:52 PM PDT 24
Finished May 16 02:13:27 PM PDT 24
Peak memory 201824 kb
Host smart-35fc7a51-0090-4387-a2c0-0782f5142f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415695928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1415695928
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3486540862
Short name T529
Test name
Test status
Simulation time 494082704148 ps
CPU time 304 seconds
Started May 16 02:06:50 PM PDT 24
Finished May 16 02:11:56 PM PDT 24
Peak memory 201836 kb
Host smart-37d76882-16c5-451b-a2f2-e91fc846c5e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486540862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3486540862
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1461714918
Short name T13
Test name
Test status
Simulation time 494094498404 ps
CPU time 1169.33 seconds
Started May 16 02:06:50 PM PDT 24
Finished May 16 02:26:22 PM PDT 24
Peak memory 201836 kb
Host smart-573c3c23-0206-4d73-b72b-6b208bf54d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461714918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1461714918
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2442393264
Short name T361
Test name
Test status
Simulation time 168824217140 ps
CPU time 402.46 seconds
Started May 16 02:06:49 PM PDT 24
Finished May 16 02:13:34 PM PDT 24
Peak memory 201876 kb
Host smart-12115a23-8068-4221-b1e9-7d703087566a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442393264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2442393264
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4180277241
Short name T198
Test name
Test status
Simulation time 377116056084 ps
CPU time 313.74 seconds
Started May 16 02:06:49 PM PDT 24
Finished May 16 02:12:05 PM PDT 24
Peak memory 201792 kb
Host smart-426813ad-fe05-45f6-9e95-cb99359e310e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180277241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4180277241
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2799319433
Short name T696
Test name
Test status
Simulation time 409980544782 ps
CPU time 258.82 seconds
Started May 16 02:06:49 PM PDT 24
Finished May 16 02:11:10 PM PDT 24
Peak memory 201728 kb
Host smart-c1e8c03d-2d80-4378-b599-cba4240fc1e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799319433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2799319433
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3033432449
Short name T702
Test name
Test status
Simulation time 96761899923 ps
CPU time 392.91 seconds
Started May 16 02:07:01 PM PDT 24
Finished May 16 02:13:35 PM PDT 24
Peak memory 202212 kb
Host smart-7cb4621f-58ed-40a0-964f-44d93dc03c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033432449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3033432449
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2014841598
Short name T566
Test name
Test status
Simulation time 36912609498 ps
CPU time 16.04 seconds
Started May 16 02:06:50 PM PDT 24
Finished May 16 02:07:08 PM PDT 24
Peak memory 201648 kb
Host smart-7a863cc3-ef6b-40ec-98c8-787c879f946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014841598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2014841598
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2742710931
Short name T793
Test name
Test status
Simulation time 4069928497 ps
CPU time 4.83 seconds
Started May 16 02:06:50 PM PDT 24
Finished May 16 02:06:57 PM PDT 24
Peak memory 201576 kb
Host smart-00e6bafb-ff81-4a27-8006-0145827eb422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742710931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2742710931
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3499515110
Short name T649
Test name
Test status
Simulation time 5696890290 ps
CPU time 1.78 seconds
Started May 16 02:06:51 PM PDT 24
Finished May 16 02:06:54 PM PDT 24
Peak memory 201672 kb
Host smart-83bba674-022e-4675-9870-15bda42ab1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499515110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3499515110
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3162618126
Short name T246
Test name
Test status
Simulation time 363440651522 ps
CPU time 221.09 seconds
Started May 16 02:07:01 PM PDT 24
Finished May 16 02:10:44 PM PDT 24
Peak memory 201792 kb
Host smart-953e7536-54dd-4620-8b33-087688da73e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162618126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3162618126
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1540502494
Short name T228
Test name
Test status
Simulation time 259842809998 ps
CPU time 526.66 seconds
Started May 16 02:06:59 PM PDT 24
Finished May 16 02:15:48 PM PDT 24
Peak memory 210412 kb
Host smart-11121ba0-ea42-4a59-8ea2-633e73d7c03b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540502494 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1540502494
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1810691175
Short name T668
Test name
Test status
Simulation time 313202401 ps
CPU time 0.81 seconds
Started May 16 02:07:09 PM PDT 24
Finished May 16 02:07:12 PM PDT 24
Peak memory 201476 kb
Host smart-a2a1c549-19f5-44dc-84f3-d9e99f0910f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810691175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1810691175
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2571930071
Short name T82
Test name
Test status
Simulation time 493598554397 ps
CPU time 281.29 seconds
Started May 16 02:06:58 PM PDT 24
Finished May 16 02:11:41 PM PDT 24
Peak memory 201896 kb
Host smart-3ff494b8-c5e1-42be-97c3-f71759bb5ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571930071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2571930071
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3897052681
Short name T659
Test name
Test status
Simulation time 492226961561 ps
CPU time 289.1 seconds
Started May 16 02:06:59 PM PDT 24
Finished May 16 02:11:50 PM PDT 24
Peak memory 201820 kb
Host smart-e182c9cc-9adc-417f-8580-053bf8b83de9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897052681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3897052681
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2294948202
Short name T599
Test name
Test status
Simulation time 334862250986 ps
CPU time 389.13 seconds
Started May 16 02:06:58 PM PDT 24
Finished May 16 02:13:29 PM PDT 24
Peak memory 201848 kb
Host smart-b8c065b1-c20d-414d-b916-0c8e871679d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294948202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2294948202
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1487252065
Short name T455
Test name
Test status
Simulation time 332462336435 ps
CPU time 381.3 seconds
Started May 16 02:06:58 PM PDT 24
Finished May 16 02:13:21 PM PDT 24
Peak memory 201816 kb
Host smart-5e295a4f-f5ed-4fb8-934c-c529493a23d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487252065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1487252065
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3129502207
Short name T142
Test name
Test status
Simulation time 548846358491 ps
CPU time 314.45 seconds
Started May 16 02:07:02 PM PDT 24
Finished May 16 02:12:17 PM PDT 24
Peak memory 201840 kb
Host smart-ba0e9a59-d6a0-4bc6-a327-8df621e2a356
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129502207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3129502207
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1084145086
Short name T421
Test name
Test status
Simulation time 383992162455 ps
CPU time 922.48 seconds
Started May 16 02:06:58 PM PDT 24
Finished May 16 02:22:22 PM PDT 24
Peak memory 201856 kb
Host smart-d6963639-5783-46cd-86da-1670c078958e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084145086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1084145086
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.422908832
Short name T399
Test name
Test status
Simulation time 129782253199 ps
CPU time 484.76 seconds
Started May 16 02:07:11 PM PDT 24
Finished May 16 02:15:17 PM PDT 24
Peak memory 202168 kb
Host smart-65a12369-2307-4155-b1df-c95adb1a3567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422908832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.422908832
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2177254352
Short name T690
Test name
Test status
Simulation time 42805751974 ps
CPU time 5.87 seconds
Started May 16 02:07:07 PM PDT 24
Finished May 16 02:07:15 PM PDT 24
Peak memory 201672 kb
Host smart-96e4a158-f0e2-483b-bb87-6cebff830716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177254352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2177254352
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1813972531
Short name T32
Test name
Test status
Simulation time 5579791989 ps
CPU time 14.08 seconds
Started May 16 02:07:06 PM PDT 24
Finished May 16 02:07:22 PM PDT 24
Peak memory 201648 kb
Host smart-1bfb1963-479a-4c38-bd28-c0370df9193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813972531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1813972531
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1313793442
Short name T432
Test name
Test status
Simulation time 5583511176 ps
CPU time 14.7 seconds
Started May 16 02:07:00 PM PDT 24
Finished May 16 02:07:16 PM PDT 24
Peak memory 201604 kb
Host smart-7f6ee081-59f2-4643-aeed-7b58cbc1e4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313793442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1313793442
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1888478735
Short name T763
Test name
Test status
Simulation time 455416236496 ps
CPU time 525.55 seconds
Started May 16 02:07:11 PM PDT 24
Finished May 16 02:15:58 PM PDT 24
Peak memory 212444 kb
Host smart-77fafcfe-d7a9-42f1-823f-78fee54d3c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888478735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1888478735
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.42905468
Short name T39
Test name
Test status
Simulation time 49219087022 ps
CPU time 60.7 seconds
Started May 16 02:07:08 PM PDT 24
Finished May 16 02:08:10 PM PDT 24
Peak memory 201964 kb
Host smart-396cc41d-52b3-43c2-b936-c563ef4e8f43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42905468 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.42905468
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.991556337
Short name T683
Test name
Test status
Simulation time 464976740 ps
CPU time 0.87 seconds
Started May 16 02:07:27 PM PDT 24
Finished May 16 02:07:30 PM PDT 24
Peak memory 201500 kb
Host smart-26aec0a2-c50a-4d13-9b15-1fe104f2142f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991556337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.991556337
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3591401516
Short name T300
Test name
Test status
Simulation time 492693438084 ps
CPU time 100.84 seconds
Started May 16 02:07:18 PM PDT 24
Finished May 16 02:09:00 PM PDT 24
Peak memory 201800 kb
Host smart-e776f7fc-3a8b-48be-9db7-2d1567d3dadd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591401516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3591401516
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3950238649
Short name T565
Test name
Test status
Simulation time 188922903891 ps
CPU time 114.06 seconds
Started May 16 02:07:19 PM PDT 24
Finished May 16 02:09:14 PM PDT 24
Peak memory 201728 kb
Host smart-bfb68286-333b-41b3-9c00-26dd8721fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950238649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3950238649
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1901734107
Short name T773
Test name
Test status
Simulation time 485295671773 ps
CPU time 558.06 seconds
Started May 16 02:07:20 PM PDT 24
Finished May 16 02:16:39 PM PDT 24
Peak memory 201896 kb
Host smart-62fa5175-93ca-4c63-9599-e6efd1fc3ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901734107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1901734107
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.524692657
Short name T415
Test name
Test status
Simulation time 331365042326 ps
CPU time 508.06 seconds
Started May 16 02:07:18 PM PDT 24
Finished May 16 02:15:48 PM PDT 24
Peak memory 201844 kb
Host smart-766651dc-7fdd-4d4a-b6da-f6eeb261f75c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=524692657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.524692657
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1650771387
Short name T333
Test name
Test status
Simulation time 165843445330 ps
CPU time 370.76 seconds
Started May 16 02:07:08 PM PDT 24
Finished May 16 02:13:20 PM PDT 24
Peak memory 201804 kb
Host smart-45e9e8b6-bc33-4578-be4c-107e5e04f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650771387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1650771387
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1876246090
Short name T410
Test name
Test status
Simulation time 330814796288 ps
CPU time 232.32 seconds
Started May 16 02:07:07 PM PDT 24
Finished May 16 02:11:01 PM PDT 24
Peak memory 201892 kb
Host smart-388cea12-8ae9-40d3-a52a-88ae6d91653a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876246090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1876246090
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3374923194
Short name T275
Test name
Test status
Simulation time 568384337400 ps
CPU time 685.5 seconds
Started May 16 02:07:18 PM PDT 24
Finished May 16 02:18:45 PM PDT 24
Peak memory 201836 kb
Host smart-da1a897f-5296-4053-aca5-4df4e8e7345b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374923194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3374923194
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.420416539
Short name T500
Test name
Test status
Simulation time 614706073640 ps
CPU time 367.27 seconds
Started May 16 02:07:17 PM PDT 24
Finished May 16 02:13:25 PM PDT 24
Peak memory 201912 kb
Host smart-d592fe99-2f1a-4d1a-8389-d91b37b13732
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420416539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.420416539
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3441762207
Short name T354
Test name
Test status
Simulation time 24966061656 ps
CPU time 56.45 seconds
Started May 16 02:07:18 PM PDT 24
Finished May 16 02:08:16 PM PDT 24
Peak memory 201632 kb
Host smart-34e17cb9-1bd6-4c95-9fa1-403e78989cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441762207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3441762207
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2979223124
Short name T775
Test name
Test status
Simulation time 3445769638 ps
CPU time 2.82 seconds
Started May 16 02:07:17 PM PDT 24
Finished May 16 02:07:22 PM PDT 24
Peak memory 201544 kb
Host smart-84770104-df1c-42b8-91ef-3f683fa9c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979223124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2979223124
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4103953499
Short name T688
Test name
Test status
Simulation time 6039462445 ps
CPU time 2.37 seconds
Started May 16 02:07:08 PM PDT 24
Finished May 16 02:07:12 PM PDT 24
Peak memory 201636 kb
Host smart-2c149693-d116-49d4-b3f8-e8ef379603ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103953499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4103953499
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3046684157
Short name T286
Test name
Test status
Simulation time 170086554230 ps
CPU time 383.21 seconds
Started May 16 02:07:26 PM PDT 24
Finished May 16 02:13:50 PM PDT 24
Peak memory 201828 kb
Host smart-167337d2-0e29-43a5-88ef-0b31656238c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046684157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3046684157
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2709355149
Short name T520
Test name
Test status
Simulation time 58475117839 ps
CPU time 122.97 seconds
Started May 16 02:07:27 PM PDT 24
Finished May 16 02:09:31 PM PDT 24
Peak memory 211536 kb
Host smart-c520d5a0-739e-4fd8-93d8-6de717f00e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709355149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2709355149
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3777221652
Short name T433
Test name
Test status
Simulation time 456633994 ps
CPU time 1.67 seconds
Started May 16 02:07:38 PM PDT 24
Finished May 16 02:07:41 PM PDT 24
Peak memory 201540 kb
Host smart-32093040-6baa-46a6-83d8-9e1fca634076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777221652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3777221652
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3946891586
Short name T329
Test name
Test status
Simulation time 576827185693 ps
CPU time 1099.38 seconds
Started May 16 02:07:27 PM PDT 24
Finished May 16 02:25:48 PM PDT 24
Peak memory 201820 kb
Host smart-4f5a0ae6-ec19-4a88-b936-36c27bcdda05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946891586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3946891586
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3927553259
Short name T751
Test name
Test status
Simulation time 166681448397 ps
CPU time 95.3 seconds
Started May 16 02:07:26 PM PDT 24
Finished May 16 02:09:03 PM PDT 24
Peak memory 201768 kb
Host smart-3afc49f2-157e-44a1-88e2-20cb0878f609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927553259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3927553259
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.559689570
Short name T634
Test name
Test status
Simulation time 331507228536 ps
CPU time 760.7 seconds
Started May 16 02:07:27 PM PDT 24
Finished May 16 02:20:09 PM PDT 24
Peak memory 201936 kb
Host smart-677e7897-7360-460d-afc6-3ecb564efb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559689570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.559689570
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3856124414
Short name T393
Test name
Test status
Simulation time 486942576587 ps
CPU time 282.8 seconds
Started May 16 02:07:26 PM PDT 24
Finished May 16 02:12:10 PM PDT 24
Peak memory 201844 kb
Host smart-13c96775-0638-48b9-9c47-5fdd3dd90dd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856124414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3856124414
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1610106940
Short name T510
Test name
Test status
Simulation time 159971913638 ps
CPU time 97.18 seconds
Started May 16 02:07:29 PM PDT 24
Finished May 16 02:09:07 PM PDT 24
Peak memory 201768 kb
Host smart-adebb290-77cd-4d59-b5d9-7e894476a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610106940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1610106940
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1664578969
Short name T365
Test name
Test status
Simulation time 163205965207 ps
CPU time 371.25 seconds
Started May 16 02:07:27 PM PDT 24
Finished May 16 02:13:39 PM PDT 24
Peak memory 201792 kb
Host smart-f11b719b-d511-449d-890f-d7dc07b9187e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664578969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1664578969
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.664337341
Short name T661
Test name
Test status
Simulation time 180805191582 ps
CPU time 434.34 seconds
Started May 16 02:07:28 PM PDT 24
Finished May 16 02:14:43 PM PDT 24
Peak memory 201820 kb
Host smart-a7b89f40-6fa6-47c6-8a2b-5f42e43eb006
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664337341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.664337341
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3147411796
Short name T143
Test name
Test status
Simulation time 201131462844 ps
CPU time 111.52 seconds
Started May 16 02:07:28 PM PDT 24
Finished May 16 02:09:21 PM PDT 24
Peak memory 201712 kb
Host smart-f1730e3b-5568-44b9-9dc6-63d5c3f4f86f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147411796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3147411796
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1676652195
Short name T50
Test name
Test status
Simulation time 118161961012 ps
CPU time 379.41 seconds
Started May 16 02:07:37 PM PDT 24
Finished May 16 02:13:57 PM PDT 24
Peak memory 202144 kb
Host smart-388361b6-1328-432c-84f5-bd5859b166be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676652195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1676652195
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1425874574
Short name T596
Test name
Test status
Simulation time 22244763093 ps
CPU time 54.15 seconds
Started May 16 02:07:28 PM PDT 24
Finished May 16 02:08:24 PM PDT 24
Peak memory 201612 kb
Host smart-b5c884ec-e0f5-43b6-a238-cdb54498d8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425874574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1425874574
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2100230308
Short name T387
Test name
Test status
Simulation time 5608643970 ps
CPU time 14.47 seconds
Started May 16 02:07:26 PM PDT 24
Finished May 16 02:07:42 PM PDT 24
Peak memory 201660 kb
Host smart-e087ada7-e583-47b3-ad16-fb4f00bdadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100230308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2100230308
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3925985119
Short name T427
Test name
Test status
Simulation time 6077688698 ps
CPU time 12.66 seconds
Started May 16 02:07:27 PM PDT 24
Finished May 16 02:07:41 PM PDT 24
Peak memory 201668 kb
Host smart-5ba0e33e-a67c-4793-8718-3f9c8f4f1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925985119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3925985119
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4146547398
Short name T593
Test name
Test status
Simulation time 333510492 ps
CPU time 1.03 seconds
Started May 16 02:05:36 PM PDT 24
Finished May 16 02:05:39 PM PDT 24
Peak memory 201528 kb
Host smart-1d0775f3-e244-4c52-b981-8c8490461ef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146547398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4146547398
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2473928079
Short name T312
Test name
Test status
Simulation time 384044253288 ps
CPU time 947.25 seconds
Started May 16 02:05:37 PM PDT 24
Finished May 16 02:21:26 PM PDT 24
Peak memory 201872 kb
Host smart-c0ee8004-d3b4-4122-8e8b-8e0eff8de44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473928079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2473928079
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3382443456
Short name T175
Test name
Test status
Simulation time 164429438146 ps
CPU time 213.86 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:09:10 PM PDT 24
Peak memory 201728 kb
Host smart-040c019b-1e91-4c65-a791-a46f7cc9515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382443456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3382443456
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1895091809
Short name T602
Test name
Test status
Simulation time 170210456725 ps
CPU time 380.45 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:11:57 PM PDT 24
Peak memory 201804 kb
Host smart-4f8c361c-45a0-4eb2-9662-44ec42669972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895091809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1895091809
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2437909614
Short name T625
Test name
Test status
Simulation time 319215772413 ps
CPU time 281.3 seconds
Started May 16 02:05:34 PM PDT 24
Finished May 16 02:10:18 PM PDT 24
Peak memory 201812 kb
Host smart-1129abd9-21bc-41b0-b2e4-3d7ed0259375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437909614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2437909614
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2320014078
Short name T157
Test name
Test status
Simulation time 499411506787 ps
CPU time 310.67 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:10:46 PM PDT 24
Peak memory 201792 kb
Host smart-93691cdb-43f9-4114-87d6-0441764958ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320014078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2320014078
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3512750647
Short name T456
Test name
Test status
Simulation time 200147647314 ps
CPU time 427.24 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:12:42 PM PDT 24
Peak memory 201820 kb
Host smart-b88ad7f9-1996-4db0-b830-80a40f44b4ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512750647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3512750647
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.754781928
Short name T780
Test name
Test status
Simulation time 97278834956 ps
CPU time 490.99 seconds
Started May 16 02:05:33 PM PDT 24
Finished May 16 02:13:46 PM PDT 24
Peak memory 202144 kb
Host smart-fe6c81cc-c48b-4353-900b-e3219211f775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754781928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.754781928
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3883281276
Short name T681
Test name
Test status
Simulation time 32107166293 ps
CPU time 20.54 seconds
Started May 16 02:05:37 PM PDT 24
Finished May 16 02:05:59 PM PDT 24
Peak memory 201652 kb
Host smart-adee22a9-bc9d-479a-a238-c7e61955b97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883281276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3883281276
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3548361721
Short name T418
Test name
Test status
Simulation time 4763757354 ps
CPU time 11.43 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:05:54 PM PDT 24
Peak memory 201648 kb
Host smart-12e0e869-2a54-4d5a-b157-7caa977f7135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548361721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3548361721
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2760245873
Short name T79
Test name
Test status
Simulation time 4309895247 ps
CPU time 10.89 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:05:54 PM PDT 24
Peak memory 217476 kb
Host smart-de1d6b55-7d79-4dfa-9571-ca79eaf9cf21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760245873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2760245873
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1313704270
Short name T394
Test name
Test status
Simulation time 5589118075 ps
CPU time 7.19 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:05:42 PM PDT 24
Peak memory 201640 kb
Host smart-14c835bb-31f2-4182-a82c-6ed5000c1588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313704270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1313704270
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.343799708
Short name T266
Test name
Test status
Simulation time 510130579447 ps
CPU time 223.59 seconds
Started May 16 02:05:40 PM PDT 24
Finished May 16 02:09:25 PM PDT 24
Peak memory 201768 kb
Host smart-6b719213-8b4c-4663-8302-29a2fa365813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343799708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.343799708
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2614508556
Short name T245
Test name
Test status
Simulation time 44885117709 ps
CPU time 89.8 seconds
Started May 16 02:05:32 PM PDT 24
Finished May 16 02:07:05 PM PDT 24
Peak memory 210348 kb
Host smart-6df0c4e6-887a-467a-a5c1-78cf3bca4c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614508556 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2614508556
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1262293126
Short name T534
Test name
Test status
Simulation time 342807791970 ps
CPU time 861.78 seconds
Started May 16 02:07:46 PM PDT 24
Finished May 16 02:22:09 PM PDT 24
Peak memory 201904 kb
Host smart-d6a3b0cf-8757-4a29-9581-fa9bd9cf7af1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262293126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1262293126
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3513044601
Short name T231
Test name
Test status
Simulation time 182500696600 ps
CPU time 320.23 seconds
Started May 16 02:07:47 PM PDT 24
Finished May 16 02:13:08 PM PDT 24
Peak memory 201772 kb
Host smart-5413da8e-3076-47a4-9eb4-4604c1d653a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513044601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3513044601
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2770074763
Short name T265
Test name
Test status
Simulation time 327541588307 ps
CPU time 375.85 seconds
Started May 16 02:07:47 PM PDT 24
Finished May 16 02:14:04 PM PDT 24
Peak memory 201908 kb
Host smart-c3e9683b-4b8a-4964-b421-518e3883bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770074763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2770074763
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.788265144
Short name T404
Test name
Test status
Simulation time 327597306573 ps
CPU time 79.88 seconds
Started May 16 02:07:47 PM PDT 24
Finished May 16 02:09:08 PM PDT 24
Peak memory 201732 kb
Host smart-029210a5-782d-4b5e-9392-87bc69975dc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=788265144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.788265144
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2261862817
Short name T340
Test name
Test status
Simulation time 319990733234 ps
CPU time 195.62 seconds
Started May 16 02:07:38 PM PDT 24
Finished May 16 02:10:55 PM PDT 24
Peak memory 201840 kb
Host smart-ff2dc778-9aa1-4fba-8b78-10aa377f7a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261862817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2261862817
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.647149661
Short name T502
Test name
Test status
Simulation time 494917675132 ps
CPU time 407.21 seconds
Started May 16 02:07:36 PM PDT 24
Finished May 16 02:14:24 PM PDT 24
Peak memory 201816 kb
Host smart-3b059bb4-ab53-43c8-abdd-6dcb3f9dcbe3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=647149661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.647149661
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2532801973
Short name T569
Test name
Test status
Simulation time 187102737679 ps
CPU time 448.61 seconds
Started May 16 02:07:45 PM PDT 24
Finished May 16 02:15:15 PM PDT 24
Peak memory 201728 kb
Host smart-21214de6-af94-4146-bdfd-dada91c0ccd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532801973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2532801973
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1882453852
Short name T9
Test name
Test status
Simulation time 604751417517 ps
CPU time 1247.66 seconds
Started May 16 02:07:47 PM PDT 24
Finished May 16 02:28:36 PM PDT 24
Peak memory 201744 kb
Host smart-501c51c4-cdb9-48bc-85d0-9d4d244978e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882453852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1882453852
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.470037216
Short name T352
Test name
Test status
Simulation time 88780225079 ps
CPU time 381.63 seconds
Started May 16 02:07:46 PM PDT 24
Finished May 16 02:14:08 PM PDT 24
Peak memory 202048 kb
Host smart-f1037e5e-00ea-46c4-8ae4-cae270ae316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470037216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.470037216
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1259668404
Short name T384
Test name
Test status
Simulation time 34690317066 ps
CPU time 60.03 seconds
Started May 16 02:07:49 PM PDT 24
Finished May 16 02:08:50 PM PDT 24
Peak memory 201620 kb
Host smart-c88a026a-f281-4ec5-b8ee-f5a7b971022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259668404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1259668404
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.636094158
Short name T172
Test name
Test status
Simulation time 3757932444 ps
CPU time 2.12 seconds
Started May 16 02:07:46 PM PDT 24
Finished May 16 02:07:49 PM PDT 24
Peak memory 201568 kb
Host smart-e7ceb071-70d3-4dcc-92fc-e5033221bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636094158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.636094158
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3682825646
Short name T632
Test name
Test status
Simulation time 5659333399 ps
CPU time 7.77 seconds
Started May 16 02:07:40 PM PDT 24
Finished May 16 02:07:48 PM PDT 24
Peak memory 201540 kb
Host smart-43052a5e-a05c-4be5-adef-f006b0106963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682825646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3682825646
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2880440281
Short name T530
Test name
Test status
Simulation time 174743133384 ps
CPU time 113.68 seconds
Started May 16 02:07:57 PM PDT 24
Finished May 16 02:09:52 PM PDT 24
Peak memory 201832 kb
Host smart-6cb10687-bc6a-4f9d-9e56-1593248e0fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880440281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2880440281
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4015178463
Short name T673
Test name
Test status
Simulation time 380185480245 ps
CPU time 188.18 seconds
Started May 16 02:07:47 PM PDT 24
Finished May 16 02:10:56 PM PDT 24
Peak memory 210136 kb
Host smart-f7e39d89-0b24-4973-97ef-3f7a300329be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015178463 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4015178463
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1300444219
Short name T667
Test name
Test status
Simulation time 373411784 ps
CPU time 0.81 seconds
Started May 16 02:08:07 PM PDT 24
Finished May 16 02:08:09 PM PDT 24
Peak memory 201520 kb
Host smart-2d51fb60-adf5-4e75-ad43-9c5d6c473827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300444219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1300444219
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2823127065
Short name T141
Test name
Test status
Simulation time 325794709496 ps
CPU time 822.64 seconds
Started May 16 02:08:06 PM PDT 24
Finished May 16 02:21:50 PM PDT 24
Peak memory 201800 kb
Host smart-d7ab4c5f-bb30-41ec-b525-0ed5e8b67627
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823127065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2823127065
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1894658842
Short name T164
Test name
Test status
Simulation time 323976944192 ps
CPU time 137.35 seconds
Started May 16 02:07:55 PM PDT 24
Finished May 16 02:10:14 PM PDT 24
Peak memory 201844 kb
Host smart-b40c9e2b-4549-480e-86e9-d6533f05f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894658842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1894658842
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1212040906
Short name T514
Test name
Test status
Simulation time 331433711687 ps
CPU time 228.51 seconds
Started May 16 02:07:56 PM PDT 24
Finished May 16 02:11:46 PM PDT 24
Peak memory 201788 kb
Host smart-005fc2ff-7563-4b60-99f7-a7c4bdebcb0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212040906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1212040906
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.4111030769
Short name T81
Test name
Test status
Simulation time 331683033751 ps
CPU time 216.95 seconds
Started May 16 02:07:56 PM PDT 24
Finished May 16 02:11:35 PM PDT 24
Peak memory 201884 kb
Host smart-3e8f8f3a-f571-4858-b1c6-ade3a23aad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111030769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4111030769
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1484349730
Short name T480
Test name
Test status
Simulation time 158470568626 ps
CPU time 337.07 seconds
Started May 16 02:07:56 PM PDT 24
Finished May 16 02:13:34 PM PDT 24
Peak memory 201760 kb
Host smart-e7a3083a-05f3-4695-8d0e-a7bf615b806d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484349730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1484349730
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3441932756
Short name T799
Test name
Test status
Simulation time 211277405477 ps
CPU time 43.85 seconds
Started May 16 02:07:56 PM PDT 24
Finished May 16 02:08:41 PM PDT 24
Peak memory 201896 kb
Host smart-dee31cab-487c-42e7-9767-261c3a1c6f11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441932756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3441932756
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2847810375
Short name T550
Test name
Test status
Simulation time 86423562748 ps
CPU time 303.5 seconds
Started May 16 02:08:05 PM PDT 24
Finished May 16 02:13:09 PM PDT 24
Peak memory 202196 kb
Host smart-9ba6ac07-5dc3-43b6-8f69-7aaba8e61b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847810375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2847810375
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3982258043
Short name T493
Test name
Test status
Simulation time 46197005256 ps
CPU time 18.51 seconds
Started May 16 02:08:09 PM PDT 24
Finished May 16 02:08:28 PM PDT 24
Peak memory 201620 kb
Host smart-ed18c13e-769e-4d90-8df4-62fedc3f720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982258043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3982258043
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1228060341
Short name T519
Test name
Test status
Simulation time 3517622731 ps
CPU time 4.86 seconds
Started May 16 02:08:06 PM PDT 24
Finished May 16 02:08:11 PM PDT 24
Peak memory 201564 kb
Host smart-1fc614b7-3409-42b5-9eb1-3551fb73b91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228060341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1228060341
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.477890962
Short name T562
Test name
Test status
Simulation time 6000992663 ps
CPU time 4.33 seconds
Started May 16 02:07:56 PM PDT 24
Finished May 16 02:08:02 PM PDT 24
Peak memory 201636 kb
Host smart-ada9e443-ae02-4bbc-b60b-c07e3f138007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477890962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.477890962
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3227432072
Short name T737
Test name
Test status
Simulation time 341154581978 ps
CPU time 206.85 seconds
Started May 16 02:08:09 PM PDT 24
Finished May 16 02:11:37 PM PDT 24
Peak memory 201792 kb
Host smart-b6805beb-c469-4ff8-bc7a-82bc9eb15fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227432072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3227432072
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1095347335
Short name T267
Test name
Test status
Simulation time 60570433294 ps
CPU time 294.23 seconds
Started May 16 02:08:07 PM PDT 24
Finished May 16 02:13:02 PM PDT 24
Peak memory 210424 kb
Host smart-82e59146-b17b-46fd-8f6e-a8823f48ccde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095347335 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1095347335
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3172588141
Short name T491
Test name
Test status
Simulation time 356451749 ps
CPU time 0.85 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:08:32 PM PDT 24
Peak memory 201556 kb
Host smart-c2c7709e-e60b-4580-a7e1-da13c075ba83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172588141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3172588141
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2742612589
Short name T497
Test name
Test status
Simulation time 183365507577 ps
CPU time 45.9 seconds
Started May 16 02:08:18 PM PDT 24
Finished May 16 02:09:05 PM PDT 24
Peak memory 201780 kb
Host smart-8729c3f5-8d86-41ec-a26c-b1c9315d8350
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742612589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2742612589
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2864191606
Short name T498
Test name
Test status
Simulation time 324539119214 ps
CPU time 169.11 seconds
Started May 16 02:08:18 PM PDT 24
Finished May 16 02:11:08 PM PDT 24
Peak memory 201836 kb
Host smart-d784cfc2-4e8f-476f-accd-781347d59917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864191606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2864191606
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.742287178
Short name T453
Test name
Test status
Simulation time 164530136849 ps
CPU time 66.87 seconds
Started May 16 02:08:17 PM PDT 24
Finished May 16 02:09:25 PM PDT 24
Peak memory 201764 kb
Host smart-02451a6e-b8ca-42ff-88b3-96534ba5eb2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=742287178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.742287178
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.910302120
Short name T711
Test name
Test status
Simulation time 319474490017 ps
CPU time 387.53 seconds
Started May 16 02:08:17 PM PDT 24
Finished May 16 02:14:46 PM PDT 24
Peak memory 201812 kb
Host smart-de417ca9-0573-44f4-a21c-4a6fd8dc4730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910302120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.910302120
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1635786605
Short name T102
Test name
Test status
Simulation time 323663238866 ps
CPU time 184.99 seconds
Started May 16 02:08:17 PM PDT 24
Finished May 16 02:11:23 PM PDT 24
Peak memory 201816 kb
Host smart-0fd5a3ed-c66c-4435-a899-bfdc2fc22451
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635786605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1635786605
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1759574503
Short name T282
Test name
Test status
Simulation time 209964419998 ps
CPU time 82.22 seconds
Started May 16 02:08:18 PM PDT 24
Finished May 16 02:09:41 PM PDT 24
Peak memory 201832 kb
Host smart-80829685-1bf7-46e5-9da7-47f7a6c48b34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759574503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1759574503
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1995901044
Short name T362
Test name
Test status
Simulation time 203490114857 ps
CPU time 116.43 seconds
Started May 16 02:08:17 PM PDT 24
Finished May 16 02:10:15 PM PDT 24
Peak memory 201828 kb
Host smart-c4775838-8fff-4864-a4e0-a5a0b16230d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995901044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1995901044
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.591205852
Short name T505
Test name
Test status
Simulation time 72656219079 ps
CPU time 245.88 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:12:39 PM PDT 24
Peak memory 202088 kb
Host smart-c35f008c-3ca8-4954-8f10-a47f3188bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591205852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.591205852
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.333047664
Short name T369
Test name
Test status
Simulation time 37746683884 ps
CPU time 35.56 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:09:08 PM PDT 24
Peak memory 201640 kb
Host smart-5686934a-19da-4192-b733-0d58726e0dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333047664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.333047664
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2234775937
Short name T629
Test name
Test status
Simulation time 4656715771 ps
CPU time 10.32 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:08:43 PM PDT 24
Peak memory 201608 kb
Host smart-af47a99f-2624-4bed-a634-d36fea0b80f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234775937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2234775937
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2998656403
Short name T397
Test name
Test status
Simulation time 5886265205 ps
CPU time 4.6 seconds
Started May 16 02:08:05 PM PDT 24
Finished May 16 02:08:11 PM PDT 24
Peak memory 201644 kb
Host smart-10fc3e13-5031-44b9-ae01-8a94a3fb52d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998656403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2998656403
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2520467193
Short name T776
Test name
Test status
Simulation time 330310539114 ps
CPU time 759.57 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:21:11 PM PDT 24
Peak memory 201824 kb
Host smart-38cc1931-70af-40d1-9393-036a29a3116e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520467193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2520467193
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.606176477
Short name T714
Test name
Test status
Simulation time 340528422 ps
CPU time 0.85 seconds
Started May 16 02:08:40 PM PDT 24
Finished May 16 02:08:42 PM PDT 24
Peak memory 201500 kb
Host smart-ca3d2f5a-5cfb-43c0-87b3-f7f014172f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606176477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.606176477
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1164312664
Short name T85
Test name
Test status
Simulation time 323481272806 ps
CPU time 149.12 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:11:02 PM PDT 24
Peak memory 201784 kb
Host smart-6da84ec7-bd78-4b35-a0c8-2de9610c582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164312664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1164312664
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2561427124
Short name T607
Test name
Test status
Simulation time 164721752575 ps
CPU time 349.39 seconds
Started May 16 02:08:32 PM PDT 24
Finished May 16 02:14:23 PM PDT 24
Peak memory 201836 kb
Host smart-ccb95b66-b110-407e-a35c-8ff973ec5456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561427124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2561427124
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1879550705
Short name T524
Test name
Test status
Simulation time 163539969894 ps
CPU time 201.65 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:11:52 PM PDT 24
Peak memory 201828 kb
Host smart-03600629-3849-46cb-bdd1-e115b0f2bf1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879550705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1879550705
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4065093038
Short name T772
Test name
Test status
Simulation time 493597589251 ps
CPU time 587.1 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:18:18 PM PDT 24
Peak memory 201808 kb
Host smart-1efd9388-cf4f-4fea-9246-4d3b43f4c695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065093038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4065093038
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3636865390
Short name T678
Test name
Test status
Simulation time 162220718166 ps
CPU time 83.94 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:09:56 PM PDT 24
Peak memory 201760 kb
Host smart-2dcd0f15-fcdb-421d-a586-31542feb059d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636865390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3636865390
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3289608472
Short name T134
Test name
Test status
Simulation time 181918507702 ps
CPU time 432.9 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:15:46 PM PDT 24
Peak memory 201916 kb
Host smart-42bef447-ecca-42cc-beb2-989a198f8c93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289608472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3289608472
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.964374727
Short name T592
Test name
Test status
Simulation time 209864005428 ps
CPU time 478.77 seconds
Started May 16 02:08:31 PM PDT 24
Finished May 16 02:16:31 PM PDT 24
Peak memory 201772 kb
Host smart-9ab2f492-688d-4936-b750-afacd8716422
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964374727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.964374727
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.680878408
Short name T466
Test name
Test status
Simulation time 40924977412 ps
CPU time 14.06 seconds
Started May 16 02:08:32 PM PDT 24
Finished May 16 02:08:47 PM PDT 24
Peak memory 201596 kb
Host smart-42801c0c-7a29-4b33-b0f6-c80cebcc83d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680878408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.680878408
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2946040079
Short name T728
Test name
Test status
Simulation time 4370291296 ps
CPU time 10.86 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:08:41 PM PDT 24
Peak memory 201652 kb
Host smart-b6d11bec-733e-492a-bb1e-63ad896958e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946040079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2946040079
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3475403927
Short name T788
Test name
Test status
Simulation time 5937384735 ps
CPU time 8.1 seconds
Started May 16 02:08:30 PM PDT 24
Finished May 16 02:08:39 PM PDT 24
Peak memory 201668 kb
Host smart-53077dc5-acc2-4818-9ddb-2d5218183599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475403927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3475403927
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.384544168
Short name T332
Test name
Test status
Simulation time 164150246008 ps
CPU time 68.39 seconds
Started May 16 02:08:40 PM PDT 24
Finished May 16 02:09:50 PM PDT 24
Peak memory 201984 kb
Host smart-09f6abed-20d7-4e4f-b4e3-6aaaa6b874d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384544168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
384544168
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.251051826
Short name T43
Test name
Test status
Simulation time 35266758571 ps
CPU time 94.86 seconds
Started May 16 02:08:40 PM PDT 24
Finished May 16 02:10:16 PM PDT 24
Peak memory 210452 kb
Host smart-ddb69b71-e0fe-4de3-b424-a97da567659a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251051826 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.251051826
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3483192153
Short name T94
Test name
Test status
Simulation time 442524731 ps
CPU time 1.37 seconds
Started May 16 02:09:02 PM PDT 24
Finished May 16 02:09:04 PM PDT 24
Peak memory 201408 kb
Host smart-b257c943-2096-414d-be66-029e7d45a9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483192153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3483192153
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3833998438
Short name T148
Test name
Test status
Simulation time 322515114723 ps
CPU time 96.67 seconds
Started May 16 02:08:48 PM PDT 24
Finished May 16 02:10:26 PM PDT 24
Peak memory 201828 kb
Host smart-569d3d32-0982-47e1-a542-1a3cfb5b647c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833998438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3833998438
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2803663403
Short name T93
Test name
Test status
Simulation time 167866202315 ps
CPU time 105.14 seconds
Started May 16 02:08:50 PM PDT 24
Finished May 16 02:10:36 PM PDT 24
Peak memory 201816 kb
Host smart-724d2456-9539-4119-8a48-b0e9b10db902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803663403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2803663403
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1287668104
Short name T277
Test name
Test status
Simulation time 163689917842 ps
CPU time 95.89 seconds
Started May 16 02:08:40 PM PDT 24
Finished May 16 02:10:17 PM PDT 24
Peak memory 201840 kb
Host smart-ab2017bb-40fc-4639-9ae6-df12fa4fe563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287668104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1287668104
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3315315020
Short name T655
Test name
Test status
Simulation time 502327305428 ps
CPU time 1143.72 seconds
Started May 16 02:08:38 PM PDT 24
Finished May 16 02:27:43 PM PDT 24
Peak memory 201828 kb
Host smart-c74bcff5-0fc9-41d5-b820-c76de3ddfc49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315315020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3315315020
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2410317060
Short name T83
Test name
Test status
Simulation time 331264919903 ps
CPU time 744.48 seconds
Started May 16 02:08:39 PM PDT 24
Finished May 16 02:21:05 PM PDT 24
Peak memory 201824 kb
Host smart-51c2964e-e259-4b57-944d-0ba2968c3ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410317060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2410317060
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.679163580
Short name T173
Test name
Test status
Simulation time 494329675575 ps
CPU time 583.85 seconds
Started May 16 02:08:39 PM PDT 24
Finished May 16 02:18:24 PM PDT 24
Peak memory 201820 kb
Host smart-180a97c6-be48-4deb-836e-977cc6526935
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=679163580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.679163580
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2789564788
Short name T672
Test name
Test status
Simulation time 427698982094 ps
CPU time 229.55 seconds
Started May 16 02:08:49 PM PDT 24
Finished May 16 02:12:40 PM PDT 24
Peak memory 201880 kb
Host smart-fccaede1-2a6f-40ce-9408-e8391fa5db2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789564788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2789564788
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3729012084
Short name T452
Test name
Test status
Simulation time 595200103998 ps
CPU time 1492.77 seconds
Started May 16 02:08:49 PM PDT 24
Finished May 16 02:33:43 PM PDT 24
Peak memory 201820 kb
Host smart-9864e007-95b8-449c-bfdc-7aa9487e9d4b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729012084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3729012084
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1696576332
Short name T665
Test name
Test status
Simulation time 95975422253 ps
CPU time 400.79 seconds
Started May 16 02:08:50 PM PDT 24
Finished May 16 02:15:32 PM PDT 24
Peak memory 202124 kb
Host smart-b7f04fab-9167-404d-8f74-e7bdbf031f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696576332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1696576332
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1425375525
Short name T435
Test name
Test status
Simulation time 28049461697 ps
CPU time 17.71 seconds
Started May 16 02:08:49 PM PDT 24
Finished May 16 02:09:07 PM PDT 24
Peak memory 201640 kb
Host smart-0bd9ee63-4585-4b88-9bdf-f7d5bdcaf35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425375525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1425375525
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1140931680
Short name T748
Test name
Test status
Simulation time 3877431320 ps
CPU time 3.12 seconds
Started May 16 02:08:49 PM PDT 24
Finished May 16 02:08:53 PM PDT 24
Peak memory 201588 kb
Host smart-6b855e1f-e843-4444-acc2-835b60ba9089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140931680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1140931680
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.759741198
Short name T392
Test name
Test status
Simulation time 6094280273 ps
CPU time 3.95 seconds
Started May 16 02:08:40 PM PDT 24
Finished May 16 02:08:45 PM PDT 24
Peak memory 201568 kb
Host smart-312429ea-de87-4bb7-9892-bcf5dae61f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759741198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.759741198
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4287108080
Short name T207
Test name
Test status
Simulation time 492495032613 ps
CPU time 689.51 seconds
Started May 16 02:08:52 PM PDT 24
Finished May 16 02:20:22 PM PDT 24
Peak memory 201732 kb
Host smart-529f4fce-a729-442f-b17c-105ae281e047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287108080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4287108080
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3084558659
Short name T762
Test name
Test status
Simulation time 100123286483 ps
CPU time 241.21 seconds
Started May 16 02:08:49 PM PDT 24
Finished May 16 02:12:52 PM PDT 24
Peak memory 210524 kb
Host smart-da6608b3-3733-42f8-a136-ccaaa7098919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084558659 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3084558659
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3385759348
Short name T733
Test name
Test status
Simulation time 384423201 ps
CPU time 1.57 seconds
Started May 16 02:09:13 PM PDT 24
Finished May 16 02:09:17 PM PDT 24
Peak memory 201516 kb
Host smart-8a0eadfb-f32f-479a-b3bd-175f72776baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385759348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3385759348
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1764702137
Short name T789
Test name
Test status
Simulation time 537159945203 ps
CPU time 119.78 seconds
Started May 16 02:09:14 PM PDT 24
Finished May 16 02:11:15 PM PDT 24
Peak memory 201716 kb
Host smart-cf608d89-ca51-4a7a-8a62-b23082571851
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764702137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1764702137
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2317461940
Short name T651
Test name
Test status
Simulation time 326655376788 ps
CPU time 753.58 seconds
Started May 16 02:09:05 PM PDT 24
Finished May 16 02:21:39 PM PDT 24
Peak memory 201832 kb
Host smart-aff7b5c4-91e9-40cb-b5e9-2ec8ae4392a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317461940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2317461940
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1863016463
Short name T544
Test name
Test status
Simulation time 159886707940 ps
CPU time 407.25 seconds
Started May 16 02:09:02 PM PDT 24
Finished May 16 02:15:50 PM PDT 24
Peak memory 201832 kb
Host smart-38c593e6-7414-49b0-90c9-eee029012b4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863016463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1863016463
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.228029070
Short name T306
Test name
Test status
Simulation time 325807691072 ps
CPU time 235.9 seconds
Started May 16 02:09:05 PM PDT 24
Finished May 16 02:13:02 PM PDT 24
Peak memory 201860 kb
Host smart-343a01de-8568-4a4d-b4d4-8ba21a337fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228029070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.228029070
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1766310234
Short name T364
Test name
Test status
Simulation time 163797937356 ps
CPU time 196.96 seconds
Started May 16 02:09:02 PM PDT 24
Finished May 16 02:12:20 PM PDT 24
Peak memory 201808 kb
Host smart-8fcf9f28-2254-439f-bde4-fd8a1172013a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766310234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1766310234
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1289245942
Short name T44
Test name
Test status
Simulation time 187522681517 ps
CPU time 455.01 seconds
Started May 16 02:09:02 PM PDT 24
Finished May 16 02:16:38 PM PDT 24
Peak memory 201732 kb
Host smart-bb297cad-448b-41fe-acd9-96aa8d2aad96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289245942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1289245942
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.414402619
Short name T750
Test name
Test status
Simulation time 400309292555 ps
CPU time 229.38 seconds
Started May 16 02:09:14 PM PDT 24
Finished May 16 02:13:05 PM PDT 24
Peak memory 201732 kb
Host smart-0601cc06-b5c8-485c-9ad2-f562637c69a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414402619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.414402619
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2844110334
Short name T154
Test name
Test status
Simulation time 38684055262 ps
CPU time 24.42 seconds
Started May 16 02:09:10 PM PDT 24
Finished May 16 02:09:37 PM PDT 24
Peak memory 201656 kb
Host smart-21c9a96c-1622-448c-a01a-09f62c7454ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844110334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2844110334
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.509633521
Short name T372
Test name
Test status
Simulation time 4079712604 ps
CPU time 5.83 seconds
Started May 16 02:09:10 PM PDT 24
Finished May 16 02:09:18 PM PDT 24
Peak memory 201548 kb
Host smart-1dce1470-f627-4675-b2e5-77a2d974f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509633521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.509633521
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3293530110
Short name T721
Test name
Test status
Simulation time 6097169093 ps
CPU time 1.74 seconds
Started May 16 02:09:01 PM PDT 24
Finished May 16 02:09:04 PM PDT 24
Peak memory 201652 kb
Host smart-39ec7217-3784-4523-b4a2-2c52f18e1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293530110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3293530110
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2654558105
Short name T686
Test name
Test status
Simulation time 199170722051 ps
CPU time 406.61 seconds
Started May 16 02:09:11 PM PDT 24
Finished May 16 02:16:00 PM PDT 24
Peak memory 201800 kb
Host smart-fbffef7b-3138-431d-b381-76a6aedc19ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654558105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2654558105
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3878143752
Short name T21
Test name
Test status
Simulation time 198070462820 ps
CPU time 194.1 seconds
Started May 16 02:09:11 PM PDT 24
Finished May 16 02:12:27 PM PDT 24
Peak memory 217744 kb
Host smart-4d99bc9d-04a0-4185-89a3-488980291954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878143752 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3878143752
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2550225313
Short name T87
Test name
Test status
Simulation time 434849648 ps
CPU time 0.87 seconds
Started May 16 02:09:31 PM PDT 24
Finished May 16 02:09:34 PM PDT 24
Peak memory 201556 kb
Host smart-fe5cc65b-7e2e-4223-8bad-e215528b0b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550225313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2550225313
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1581662259
Short name T645
Test name
Test status
Simulation time 529348277931 ps
CPU time 240.38 seconds
Started May 16 02:09:33 PM PDT 24
Finished May 16 02:13:34 PM PDT 24
Peak memory 201784 kb
Host smart-ffa5b3f1-aef6-415c-8e27-fc48fb9492bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581662259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1581662259
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2536534169
Short name T551
Test name
Test status
Simulation time 339163266525 ps
CPU time 216.32 seconds
Started May 16 02:09:31 PM PDT 24
Finished May 16 02:13:09 PM PDT 24
Peak memory 201832 kb
Host smart-8418b561-924e-4cc6-b456-8de69d0aaced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536534169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2536534169
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.975490107
Short name T163
Test name
Test status
Simulation time 340725050083 ps
CPU time 130.51 seconds
Started May 16 02:09:23 PM PDT 24
Finished May 16 02:11:35 PM PDT 24
Peak memory 201828 kb
Host smart-7656f655-9951-4f72-abe3-ea3cee8da605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975490107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.975490107
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2671389101
Short name T557
Test name
Test status
Simulation time 167146686274 ps
CPU time 380.54 seconds
Started May 16 02:09:21 PM PDT 24
Finished May 16 02:15:42 PM PDT 24
Peak memory 201792 kb
Host smart-86eacc8a-f6b3-4fcb-82e1-499ea4710d81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671389101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2671389101
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.4096794565
Short name T132
Test name
Test status
Simulation time 165858459728 ps
CPU time 103.13 seconds
Started May 16 02:09:21 PM PDT 24
Finished May 16 02:11:05 PM PDT 24
Peak memory 201812 kb
Host smart-5e65633c-746f-4dd9-8e4d-d94ebd7752ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096794565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4096794565
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1433236743
Short name T579
Test name
Test status
Simulation time 493509007834 ps
CPU time 281.7 seconds
Started May 16 02:09:21 PM PDT 24
Finished May 16 02:14:04 PM PDT 24
Peak memory 201872 kb
Host smart-f5b1ccb7-54c4-403e-8b25-6a2a8f160124
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433236743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1433236743
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2172463897
Short name T144
Test name
Test status
Simulation time 524046626141 ps
CPU time 1213.35 seconds
Started May 16 02:09:21 PM PDT 24
Finished May 16 02:29:35 PM PDT 24
Peak memory 201908 kb
Host smart-8a59d82f-3ae1-4fea-81b3-01fba93cabdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172463897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2172463897
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3198848900
Short name T408
Test name
Test status
Simulation time 582723563128 ps
CPU time 938 seconds
Started May 16 02:09:33 PM PDT 24
Finished May 16 02:25:13 PM PDT 24
Peak memory 201804 kb
Host smart-b08e5427-6da8-4377-b2e7-7dd9df2e9d33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198848900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3198848900
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2327244424
Short name T535
Test name
Test status
Simulation time 82233587160 ps
CPU time 461.11 seconds
Started May 16 02:09:32 PM PDT 24
Finished May 16 02:17:15 PM PDT 24
Peak memory 202140 kb
Host smart-c40ae3ad-88e8-4205-ad59-9f09f3f28cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327244424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2327244424
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3569991292
Short name T548
Test name
Test status
Simulation time 23332885006 ps
CPU time 7.61 seconds
Started May 16 02:09:32 PM PDT 24
Finished May 16 02:09:41 PM PDT 24
Peak memory 201620 kb
Host smart-66e42062-99b6-4af2-9e8c-4df248f99994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569991292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3569991292
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3714913190
Short name T484
Test name
Test status
Simulation time 3717972765 ps
CPU time 2.92 seconds
Started May 16 02:09:31 PM PDT 24
Finished May 16 02:09:35 PM PDT 24
Peak memory 201552 kb
Host smart-0fafc475-d239-45d2-8b90-9b3a3b3ddaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714913190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3714913190
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2234174692
Short name T594
Test name
Test status
Simulation time 5669711862 ps
CPU time 12.79 seconds
Started May 16 02:09:21 PM PDT 24
Finished May 16 02:09:35 PM PDT 24
Peak memory 201668 kb
Host smart-d79167a9-576f-414e-9fc6-7e28b8d6285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234174692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2234174692
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.52251202
Short name T315
Test name
Test status
Simulation time 167375086833 ps
CPU time 321.1 seconds
Started May 16 02:09:33 PM PDT 24
Finished May 16 02:14:55 PM PDT 24
Peak memory 201792 kb
Host smart-2a711d94-87a9-4708-928f-c73a7ecefe13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52251202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.52251202
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3746874555
Short name T430
Test name
Test status
Simulation time 391748435 ps
CPU time 1.09 seconds
Started May 16 02:09:51 PM PDT 24
Finished May 16 02:09:53 PM PDT 24
Peak memory 201420 kb
Host smart-035705f5-17b6-488c-9c7a-cfbef8c449e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746874555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3746874555
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2788654068
Short name T179
Test name
Test status
Simulation time 480704315723 ps
CPU time 90.74 seconds
Started May 16 02:09:43 PM PDT 24
Finished May 16 02:11:15 PM PDT 24
Peak memory 201884 kb
Host smart-a271e72f-f41f-4c49-9d83-21d1b063c157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788654068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2788654068
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.711003979
Short name T503
Test name
Test status
Simulation time 170206845710 ps
CPU time 107.72 seconds
Started May 16 02:09:43 PM PDT 24
Finished May 16 02:11:32 PM PDT 24
Peak memory 201796 kb
Host smart-aba99e98-1da1-4729-94fc-529e5da08683
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=711003979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.711003979
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3524761260
Short name T149
Test name
Test status
Simulation time 161145084970 ps
CPU time 47.12 seconds
Started May 16 02:09:42 PM PDT 24
Finished May 16 02:10:30 PM PDT 24
Peak memory 201868 kb
Host smart-4b557318-97fc-4220-a425-b9d4b6e86c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524761260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3524761260
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.987538744
Short name T739
Test name
Test status
Simulation time 334867395726 ps
CPU time 357.57 seconds
Started May 16 02:09:41 PM PDT 24
Finished May 16 02:15:40 PM PDT 24
Peak memory 201900 kb
Host smart-6d18b0e4-6149-4665-ab57-5cb689433387
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=987538744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.987538744
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.423744644
Short name T236
Test name
Test status
Simulation time 194215305016 ps
CPU time 470.74 seconds
Started May 16 02:09:42 PM PDT 24
Finished May 16 02:17:34 PM PDT 24
Peak memory 201732 kb
Host smart-ac8f150a-e703-45ce-a94f-c63072d5ab39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423744644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.423744644
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.611470084
Short name T564
Test name
Test status
Simulation time 608518448873 ps
CPU time 729.5 seconds
Started May 16 02:09:42 PM PDT 24
Finished May 16 02:21:53 PM PDT 24
Peak memory 201780 kb
Host smart-6ac7ea9c-ba34-4e6d-941a-5ce70e63d200
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611470084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.611470084
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3516332380
Short name T48
Test name
Test status
Simulation time 106054391685 ps
CPU time 598.42 seconds
Started May 16 02:09:53 PM PDT 24
Finished May 16 02:19:54 PM PDT 24
Peak memory 202136 kb
Host smart-60c2670e-5c13-4ba5-bcb8-6205fb296922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516332380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3516332380
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2765499456
Short name T713
Test name
Test status
Simulation time 43638992920 ps
CPU time 13.11 seconds
Started May 16 02:09:43 PM PDT 24
Finished May 16 02:09:58 PM PDT 24
Peak memory 201644 kb
Host smart-323ccddd-5cfe-4ddd-85ce-fc9560cc14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765499456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2765499456
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1656269638
Short name T740
Test name
Test status
Simulation time 3530886430 ps
CPU time 2.5 seconds
Started May 16 02:09:43 PM PDT 24
Finished May 16 02:09:47 PM PDT 24
Peak memory 201564 kb
Host smart-03aef1a4-7c5f-4acf-a778-2bbcfd1a0f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656269638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1656269638
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3888369467
Short name T409
Test name
Test status
Simulation time 5969825714 ps
CPU time 4.41 seconds
Started May 16 02:09:33 PM PDT 24
Finished May 16 02:09:39 PM PDT 24
Peak memory 201660 kb
Host smart-b79e860c-a347-4390-9066-671691e98a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888369467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3888369467
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3920945496
Short name T200
Test name
Test status
Simulation time 183633826452 ps
CPU time 105.93 seconds
Started May 16 02:09:53 PM PDT 24
Finished May 16 02:11:41 PM PDT 24
Peak memory 201732 kb
Host smart-69e4f4c7-ac0d-49d4-b9c3-d7c02324af4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920945496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3920945496
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3285961478
Short name T181
Test name
Test status
Simulation time 73309245515 ps
CPU time 137.64 seconds
Started May 16 02:09:52 PM PDT 24
Finished May 16 02:12:12 PM PDT 24
Peak memory 210464 kb
Host smart-b96b3aca-e99d-40c5-a4ff-9b0710d86822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285961478 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3285961478
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1759466249
Short name T758
Test name
Test status
Simulation time 369555736 ps
CPU time 1.37 seconds
Started May 16 02:10:05 PM PDT 24
Finished May 16 02:10:08 PM PDT 24
Peak memory 201528 kb
Host smart-a253419e-28ec-48eb-a5b5-8df1a6d48a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759466249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1759466249
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3673736802
Short name T770
Test name
Test status
Simulation time 201704553527 ps
CPU time 454.1 seconds
Started May 16 02:09:52 PM PDT 24
Finished May 16 02:17:28 PM PDT 24
Peak memory 201788 kb
Host smart-855688c1-179d-4b99-8016-f150f4a56d99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673736802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3673736802
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2070748273
Short name T174
Test name
Test status
Simulation time 326985307888 ps
CPU time 51.3 seconds
Started May 16 02:09:53 PM PDT 24
Finished May 16 02:10:46 PM PDT 24
Peak memory 201828 kb
Host smart-76144686-d1ba-4917-8991-f7fe79947bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070748273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2070748273
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1589272223
Short name T621
Test name
Test status
Simulation time 486564766796 ps
CPU time 1064.83 seconds
Started May 16 02:09:54 PM PDT 24
Finished May 16 02:27:40 PM PDT 24
Peak memory 201780 kb
Host smart-b5e737f5-7eb4-4802-894e-89e3a627a457
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589272223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1589272223
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.643373977
Short name T299
Test name
Test status
Simulation time 324252973748 ps
CPU time 104.58 seconds
Started May 16 02:09:53 PM PDT 24
Finished May 16 02:11:40 PM PDT 24
Peak memory 201812 kb
Host smart-bd59e174-c911-4bff-9a61-b5fdbbd50a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643373977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.643373977
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.4184750067
Short name T624
Test name
Test status
Simulation time 491613005779 ps
CPU time 609.21 seconds
Started May 16 02:09:51 PM PDT 24
Finished May 16 02:20:02 PM PDT 24
Peak memory 201812 kb
Host smart-10a8acba-3af4-4579-af67-ca77d057fa52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184750067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.4184750067
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1411144390
Short name T31
Test name
Test status
Simulation time 545516816864 ps
CPU time 299.29 seconds
Started May 16 02:09:54 PM PDT 24
Finished May 16 02:14:55 PM PDT 24
Peak memory 201792 kb
Host smart-a9b1ba31-8807-48e8-b1dd-aa4795a584d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411144390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1411144390
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1701555042
Short name T390
Test name
Test status
Simulation time 601221432913 ps
CPU time 1457.18 seconds
Started May 16 02:09:53 PM PDT 24
Finished May 16 02:34:12 PM PDT 24
Peak memory 201892 kb
Host smart-c7701149-b652-461b-93c5-8e2b3624c0e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701555042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1701555042
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.77095838
Short name T600
Test name
Test status
Simulation time 93732119006 ps
CPU time 336.14 seconds
Started May 16 02:10:05 PM PDT 24
Finished May 16 02:15:43 PM PDT 24
Peak memory 202120 kb
Host smart-0ecec58d-75ec-4e5b-a063-7d99124317ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77095838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.77095838
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.309206397
Short name T475
Test name
Test status
Simulation time 32509315735 ps
CPU time 69.04 seconds
Started May 16 02:10:04 PM PDT 24
Finished May 16 02:11:14 PM PDT 24
Peak memory 201604 kb
Host smart-d4bc1d7b-8230-41f4-abd9-c7dff117756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309206397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.309206397
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1835778234
Short name T389
Test name
Test status
Simulation time 3335774990 ps
CPU time 8.79 seconds
Started May 16 02:09:52 PM PDT 24
Finished May 16 02:10:03 PM PDT 24
Peak memory 201588 kb
Host smart-72271a0b-964e-4b30-80b3-9b14be96ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835778234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1835778234
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3318965088
Short name T528
Test name
Test status
Simulation time 5964680968 ps
CPU time 4.48 seconds
Started May 16 02:09:52 PM PDT 24
Finished May 16 02:09:58 PM PDT 24
Peak memory 201644 kb
Host smart-bf81da5b-6ced-4a6f-979d-53286f34cb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318965088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3318965088
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3560001817
Short name T281
Test name
Test status
Simulation time 270717723989 ps
CPU time 74.22 seconds
Started May 16 02:10:05 PM PDT 24
Finished May 16 02:11:21 PM PDT 24
Peak memory 210116 kb
Host smart-504b718d-f098-4bc6-9c18-6c4025e16342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560001817 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3560001817
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2267053731
Short name T411
Test name
Test status
Simulation time 383659905 ps
CPU time 1.49 seconds
Started May 16 02:10:14 PM PDT 24
Finished May 16 02:10:16 PM PDT 24
Peak memory 201556 kb
Host smart-dc92ff88-f098-4a5c-ad1e-f6a7d33ba49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267053731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2267053731
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1701518639
Short name T56
Test name
Test status
Simulation time 159915251695 ps
CPU time 290.36 seconds
Started May 16 02:10:04 PM PDT 24
Finished May 16 02:14:56 PM PDT 24
Peak memory 201776 kb
Host smart-ed075577-45c0-4365-bed9-93e540afa329
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701518639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1701518639
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3765046143
Short name T252
Test name
Test status
Simulation time 170325198783 ps
CPU time 52.55 seconds
Started May 16 02:10:04 PM PDT 24
Finished May 16 02:10:58 PM PDT 24
Peak memory 201832 kb
Host smart-ae530ee9-969b-42f5-80e8-79a11376d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765046143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3765046143
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2223629179
Short name T4
Test name
Test status
Simulation time 162126703298 ps
CPU time 55.97 seconds
Started May 16 02:10:06 PM PDT 24
Finished May 16 02:11:04 PM PDT 24
Peak memory 201808 kb
Host smart-f1c1cf74-ae05-471c-a611-bd5708370a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223629179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2223629179
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1949994486
Short name T663
Test name
Test status
Simulation time 324215045642 ps
CPU time 217.72 seconds
Started May 16 02:10:06 PM PDT 24
Finished May 16 02:13:45 PM PDT 24
Peak memory 201844 kb
Host smart-5425150c-b1eb-44b5-9a6b-8914c64aa1de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949994486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1949994486
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.114645859
Short name T98
Test name
Test status
Simulation time 330051420984 ps
CPU time 404.3 seconds
Started May 16 02:10:06 PM PDT 24
Finished May 16 02:16:52 PM PDT 24
Peak memory 201844 kb
Host smart-d18bca01-5240-48b3-9931-230065a7e55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114645859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.114645859
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.253729129
Short name T504
Test name
Test status
Simulation time 495743591762 ps
CPU time 182.85 seconds
Started May 16 02:10:05 PM PDT 24
Finished May 16 02:13:09 PM PDT 24
Peak memory 201804 kb
Host smart-ac803ccd-e489-4c30-b543-09655509a61c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=253729129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.253729129
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.107101695
Short name T479
Test name
Test status
Simulation time 167398974423 ps
CPU time 93.82 seconds
Started May 16 02:10:04 PM PDT 24
Finished May 16 02:11:40 PM PDT 24
Peak memory 201900 kb
Host smart-733c91b2-ebaf-492a-8c63-8f0ed7ea3213
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107101695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.107101695
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3707864120
Short name T612
Test name
Test status
Simulation time 602500248106 ps
CPU time 825.24 seconds
Started May 16 02:10:04 PM PDT 24
Finished May 16 02:23:51 PM PDT 24
Peak memory 201776 kb
Host smart-0304c5d7-3a95-4bf3-b92f-6f506c7a83f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707864120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3707864120
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.778459118
Short name T6
Test name
Test status
Simulation time 111046514304 ps
CPU time 557.48 seconds
Started May 16 02:10:14 PM PDT 24
Finished May 16 02:19:33 PM PDT 24
Peak memory 202176 kb
Host smart-c92c65f0-2d9e-4a5d-b1f3-b0ea683f3ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778459118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.778459118
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3325611077
Short name T785
Test name
Test status
Simulation time 29915491533 ps
CPU time 74.93 seconds
Started May 16 02:10:16 PM PDT 24
Finished May 16 02:11:32 PM PDT 24
Peak memory 201672 kb
Host smart-f4ececf3-5c48-46a2-9b9f-d1645d51a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325611077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3325611077
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4289006930
Short name T434
Test name
Test status
Simulation time 3237271332 ps
CPU time 4.54 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:10:21 PM PDT 24
Peak memory 201588 kb
Host smart-878b9e78-afb5-423f-ab40-54cb86ac86b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289006930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4289006930
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3176595231
Short name T383
Test name
Test status
Simulation time 5757847913 ps
CPU time 7.93 seconds
Started May 16 02:10:05 PM PDT 24
Finished May 16 02:10:15 PM PDT 24
Peak memory 201536 kb
Host smart-0aabed19-d72d-4ce3-a24c-41eee7e87037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176595231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3176595231
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.608188410
Short name T49
Test name
Test status
Simulation time 28917517144 ps
CPU time 70.56 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:11:27 PM PDT 24
Peak memory 201668 kb
Host smart-60e06d57-6080-4e7f-90ae-96b47853e4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608188410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
608188410
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1876033048
Short name T25
Test name
Test status
Simulation time 482780651288 ps
CPU time 353.02 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:16:09 PM PDT 24
Peak memory 210436 kb
Host smart-22e16529-7ebe-4138-9751-6af933e15fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876033048 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1876033048
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3326471968
Short name T738
Test name
Test status
Simulation time 531683571 ps
CPU time 1.94 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:05:51 PM PDT 24
Peak memory 201608 kb
Host smart-f7e9338a-71f3-4a44-ade0-12d911365267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326471968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3326471968
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2303071622
Short name T279
Test name
Test status
Simulation time 165754908081 ps
CPU time 419.68 seconds
Started May 16 02:05:43 PM PDT 24
Finished May 16 02:12:45 PM PDT 24
Peak memory 201884 kb
Host smart-ea04028b-de87-4222-881d-65e59abf2283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303071622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2303071622
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.189371890
Short name T293
Test name
Test status
Simulation time 496124101748 ps
CPU time 1185.09 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:25:35 PM PDT 24
Peak memory 201848 kb
Host smart-6dead93e-d24d-4325-a879-e27ca6b555c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189371890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.189371890
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2902108396
Short name T653
Test name
Test status
Simulation time 322478142123 ps
CPU time 121.55 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:07:48 PM PDT 24
Peak memory 201804 kb
Host smart-7e7bcf72-3833-4f24-aa08-f44123885652
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902108396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2902108396
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2311946590
Short name T168
Test name
Test status
Simulation time 333938734753 ps
CPU time 204.39 seconds
Started May 16 02:05:41 PM PDT 24
Finished May 16 02:09:07 PM PDT 24
Peak memory 201772 kb
Host smart-a12eda75-fa4b-4fba-9410-2378d001a2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311946590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2311946590
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1852368613
Short name T454
Test name
Test status
Simulation time 160730034576 ps
CPU time 384.56 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:12:14 PM PDT 24
Peak memory 201844 kb
Host smart-dbfacc31-9a8b-461d-a8e7-038169c8b2a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852368613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1852368613
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4199142122
Short name T547
Test name
Test status
Simulation time 196289149007 ps
CPU time 62.97 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:06:50 PM PDT 24
Peak memory 201888 kb
Host smart-9d6dca5e-5c29-49eb-a25e-163311d14967
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199142122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4199142122
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4235103308
Short name T784
Test name
Test status
Simulation time 119210100742 ps
CPU time 527.84 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:14:38 PM PDT 24
Peak memory 202144 kb
Host smart-7ba68c65-42c2-44b0-bc70-6ed378e990be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235103308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4235103308
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3832902954
Short name T695
Test name
Test status
Simulation time 23236340594 ps
CPU time 15.38 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:06:07 PM PDT 24
Peak memory 201600 kb
Host smart-af93e8e7-ca1b-4eb4-bdb5-6bce06f75b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832902954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3832902954
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3447259188
Short name T8
Test name
Test status
Simulation time 4778203399 ps
CPU time 3.45 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:05:54 PM PDT 24
Peak memory 201596 kb
Host smart-9cf3e1f8-0fb1-4bf4-8f3f-5eaa7b9bb8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447259188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3447259188
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1034487154
Short name T78
Test name
Test status
Simulation time 8353839123 ps
CPU time 3.32 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:05:54 PM PDT 24
Peak memory 218360 kb
Host smart-3ae389cb-e9ca-4ddf-aeef-75170c86eb6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034487154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1034487154
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.789557913
Short name T687
Test name
Test status
Simulation time 5643474429 ps
CPU time 11.08 seconds
Started May 16 02:05:42 PM PDT 24
Finished May 16 02:05:54 PM PDT 24
Peak memory 201620 kb
Host smart-d3b01946-b939-43b7-8bf8-5b0bee0a541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789557913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.789557913
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.505373250
Short name T297
Test name
Test status
Simulation time 22624849766 ps
CPU time 51.25 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:06:39 PM PDT 24
Peak memory 210480 kb
Host smart-19b25dac-4bee-4df9-9c90-16de1e55b5f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505373250 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.505373250
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1756743011
Short name T448
Test name
Test status
Simulation time 486783058 ps
CPU time 0.93 seconds
Started May 16 02:10:26 PM PDT 24
Finished May 16 02:10:28 PM PDT 24
Peak memory 201556 kb
Host smart-9378c9b6-41db-4b8f-9ec8-69bbf1af6e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756743011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1756743011
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3247098288
Short name T701
Test name
Test status
Simulation time 451949979756 ps
CPU time 426.27 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:17:34 PM PDT 24
Peak memory 201824 kb
Host smart-192c7a04-9e54-42af-8504-58c8704a4345
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247098288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3247098288
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3785272227
Short name T167
Test name
Test status
Simulation time 521068401224 ps
CPU time 176.2 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:13:25 PM PDT 24
Peak memory 201800 kb
Host smart-4a6c8878-aa4e-4d2f-a55b-c16e8d7cabb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785272227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3785272227
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2900062489
Short name T14
Test name
Test status
Simulation time 167048984660 ps
CPU time 222.14 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:13:59 PM PDT 24
Peak memory 201820 kb
Host smart-fe094968-47fd-4083-b2fe-08bd5dea155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900062489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2900062489
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.394741541
Short name T786
Test name
Test status
Simulation time 328819461324 ps
CPU time 738.01 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:22:35 PM PDT 24
Peak memory 201820 kb
Host smart-1cc52bbe-8716-48f4-ae88-569ed8910fcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=394741541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.394741541
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2873588236
Short name T328
Test name
Test status
Simulation time 497657753649 ps
CPU time 550.86 seconds
Started May 16 02:10:14 PM PDT 24
Finished May 16 02:19:26 PM PDT 24
Peak memory 201840 kb
Host smart-66101da5-8f33-463b-b8e7-c32e55b9309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873588236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2873588236
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2584335439
Short name T680
Test name
Test status
Simulation time 166513527189 ps
CPU time 35.3 seconds
Started May 16 02:10:14 PM PDT 24
Finished May 16 02:10:51 PM PDT 24
Peak memory 201752 kb
Host smart-777d29b7-64c4-40fd-b63e-5e271ef90463
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584335439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2584335439
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2376502420
Short name T202
Test name
Test status
Simulation time 163840738770 ps
CPU time 188.85 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:13:24 PM PDT 24
Peak memory 201928 kb
Host smart-fa151660-d83f-4f22-88b9-cf98ba426754
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376502420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2376502420
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.969480699
Short name T402
Test name
Test status
Simulation time 199670499736 ps
CPU time 110.65 seconds
Started May 16 02:10:16 PM PDT 24
Finished May 16 02:12:08 PM PDT 24
Peak memory 201844 kb
Host smart-e0a93f01-6025-42f4-aa57-e0145905b057
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969480699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.969480699
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2915078933
Short name T465
Test name
Test status
Simulation time 68968950064 ps
CPU time 263.44 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:14:52 PM PDT 24
Peak memory 202136 kb
Host smart-027f37b3-1af6-433e-9f3e-f0b4cf031465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915078933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2915078933
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3091539181
Short name T616
Test name
Test status
Simulation time 41534419322 ps
CPU time 12.55 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:10:41 PM PDT 24
Peak memory 201604 kb
Host smart-a9bf6bc6-befe-43eb-b961-b5e47dcedbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091539181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3091539181
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.500485024
Short name T658
Test name
Test status
Simulation time 3679472910 ps
CPU time 1.48 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:10:29 PM PDT 24
Peak memory 201600 kb
Host smart-1b577021-473d-4742-afc7-ffd834662132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500485024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.500485024
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4188539583
Short name T689
Test name
Test status
Simulation time 6068170892 ps
CPU time 2.54 seconds
Started May 16 02:10:15 PM PDT 24
Finished May 16 02:10:19 PM PDT 24
Peak memory 201636 kb
Host smart-739240a4-f959-408e-97fc-6da852f4ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188539583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4188539583
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2616189932
Short name T251
Test name
Test status
Simulation time 526279873193 ps
CPU time 643.19 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:21:11 PM PDT 24
Peak memory 201984 kb
Host smart-397e49e4-8d80-4450-9da0-1c4cefc019e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616189932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2616189932
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3332505125
Short name T741
Test name
Test status
Simulation time 131441676592 ps
CPU time 197.48 seconds
Started May 16 02:10:26 PM PDT 24
Finished May 16 02:13:45 PM PDT 24
Peak memory 210520 kb
Host smart-abdba632-95eb-4f7d-aa84-78a9eae455eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332505125 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3332505125
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3728856691
Short name T674
Test name
Test status
Simulation time 509530968 ps
CPU time 1.68 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:10:46 PM PDT 24
Peak memory 201508 kb
Host smart-2084b5f0-1d60-4015-a8e2-9328361030cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728856691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3728856691
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1324837446
Short name T169
Test name
Test status
Simulation time 185450282777 ps
CPU time 70.9 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:11:55 PM PDT 24
Peak memory 201812 kb
Host smart-6a14e0f3-5d9d-41eb-a648-223a6461a4aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324837446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1324837446
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4089734829
Short name T230
Test name
Test status
Simulation time 165403841311 ps
CPU time 198.86 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:14:04 PM PDT 24
Peak memory 201768 kb
Host smart-19882493-6dce-47c1-8483-3368ef4c64b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089734829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4089734829
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3671667897
Short name T537
Test name
Test status
Simulation time 484986622475 ps
CPU time 1093.44 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:28:58 PM PDT 24
Peak memory 201816 kb
Host smart-8ec4c429-d1a3-43c5-8320-7f8534560517
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671667897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3671667897
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.541355760
Short name T473
Test name
Test status
Simulation time 164889674363 ps
CPU time 378.7 seconds
Started May 16 02:10:28 PM PDT 24
Finished May 16 02:16:48 PM PDT 24
Peak memory 201892 kb
Host smart-c57975d1-ef5b-4ad2-81c4-e06cd4aeb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541355760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.541355760
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.908649932
Short name T553
Test name
Test status
Simulation time 325208127677 ps
CPU time 365.28 seconds
Started May 16 02:10:27 PM PDT 24
Finished May 16 02:16:33 PM PDT 24
Peak memory 201888 kb
Host smart-b4e1b056-eaa5-4502-a690-d87ea384e014
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=908649932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.908649932
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.186268684
Short name T319
Test name
Test status
Simulation time 191863636138 ps
CPU time 143.83 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:13:09 PM PDT 24
Peak memory 201900 kb
Host smart-0a963985-3a8e-472e-abb6-0d5c286d69c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186268684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.186268684
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2265901586
Short name T631
Test name
Test status
Simulation time 202713814164 ps
CPU time 120.97 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:12:46 PM PDT 24
Peak memory 201828 kb
Host smart-5e104e3a-5415-455d-a1f7-c97bf04f0416
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265901586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2265901586
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.888769120
Short name T644
Test name
Test status
Simulation time 73201561037 ps
CPU time 400.92 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:17:26 PM PDT 24
Peak memory 202228 kb
Host smart-c235f64a-fd4c-4b04-8fe9-2e8cdbd66cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888769120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.888769120
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.75498815
Short name T153
Test name
Test status
Simulation time 43214363346 ps
CPU time 98.6 seconds
Started May 16 02:10:42 PM PDT 24
Finished May 16 02:12:21 PM PDT 24
Peak memory 201660 kb
Host smart-f8722773-c952-4c4b-b409-55a18568615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75498815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.75498815
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.848426933
Short name T656
Test name
Test status
Simulation time 3924506011 ps
CPU time 3.21 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:10:47 PM PDT 24
Peak memory 201608 kb
Host smart-370a7c27-556f-4902-b0eb-cdcc5e81a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848426933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.848426933
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2173664524
Short name T494
Test name
Test status
Simulation time 5888214471 ps
CPU time 14.67 seconds
Started May 16 02:10:28 PM PDT 24
Finished May 16 02:10:43 PM PDT 24
Peak memory 201648 kb
Host smart-489c7904-a884-42db-b9d1-ad4f85611ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173664524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2173664524
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1237195225
Short name T213
Test name
Test status
Simulation time 208156984504 ps
CPU time 462.24 seconds
Started May 16 02:10:43 PM PDT 24
Finished May 16 02:18:27 PM PDT 24
Peak memory 201836 kb
Host smart-b60b2bf9-5311-4ef3-8e49-766f7f59d97c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237195225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1237195225
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1472835553
Short name T184
Test name
Test status
Simulation time 145500805092 ps
CPU time 97.01 seconds
Started May 16 02:10:42 PM PDT 24
Finished May 16 02:12:20 PM PDT 24
Peak memory 210124 kb
Host smart-3990d215-00ba-4aa5-9602-86b313512ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472835553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1472835553
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3884194870
Short name T572
Test name
Test status
Simulation time 553431355 ps
CPU time 0.97 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:11:09 PM PDT 24
Peak memory 201536 kb
Host smart-b89a5b58-cb4f-421c-90ab-ebc57e2ce18a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884194870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3884194870
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4097939699
Short name T219
Test name
Test status
Simulation time 181409241072 ps
CPU time 207.29 seconds
Started May 16 02:10:54 PM PDT 24
Finished May 16 02:14:22 PM PDT 24
Peak memory 201848 kb
Host smart-958497c9-c37b-4207-b5e7-13863038bdee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097939699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4097939699
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2972161434
Short name T125
Test name
Test status
Simulation time 180138597180 ps
CPU time 101.14 seconds
Started May 16 02:10:57 PM PDT 24
Finished May 16 02:12:40 PM PDT 24
Peak memory 201720 kb
Host smart-4323dac0-04b9-40a7-a246-443e49202d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972161434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2972161434
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1895727002
Short name T652
Test name
Test status
Simulation time 325532170374 ps
CPU time 181.46 seconds
Started May 16 02:10:53 PM PDT 24
Finished May 16 02:13:56 PM PDT 24
Peak memory 201812 kb
Host smart-7158799c-ad73-41e4-b19f-0ee14e1dbac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895727002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1895727002
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.912489919
Short name T676
Test name
Test status
Simulation time 165141306812 ps
CPU time 390.31 seconds
Started May 16 02:10:54 PM PDT 24
Finished May 16 02:17:25 PM PDT 24
Peak memory 201808 kb
Host smart-d80183cd-e26e-417b-a171-687d4d8ddf8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=912489919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.912489919
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3391114263
Short name T699
Test name
Test status
Simulation time 334489217590 ps
CPU time 699.79 seconds
Started May 16 02:10:57 PM PDT 24
Finished May 16 02:22:39 PM PDT 24
Peak memory 201736 kb
Host smart-4967ad61-629e-43ef-af6a-01c140c341ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391114263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3391114263
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1369917960
Short name T92
Test name
Test status
Simulation time 325745726768 ps
CPU time 175.74 seconds
Started May 16 02:10:55 PM PDT 24
Finished May 16 02:13:52 PM PDT 24
Peak memory 201760 kb
Host smart-354f1687-d0ec-42b0-a652-a8e1f2231f58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369917960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1369917960
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1254490360
Short name T80
Test name
Test status
Simulation time 209561639745 ps
CPU time 122.19 seconds
Started May 16 02:10:53 PM PDT 24
Finished May 16 02:12:56 PM PDT 24
Peak memory 201836 kb
Host smart-b412d4e4-df26-453c-8419-c9f9387d4263
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254490360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1254490360
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2441873297
Short name T449
Test name
Test status
Simulation time 626246795208 ps
CPU time 343.02 seconds
Started May 16 02:10:55 PM PDT 24
Finished May 16 02:16:39 PM PDT 24
Peak memory 201828 kb
Host smart-85c4e39c-40d8-4eb1-8afd-d5281438f98f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441873297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2441873297
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1131994111
Short name T608
Test name
Test status
Simulation time 98672564351 ps
CPU time 521.06 seconds
Started May 16 02:10:55 PM PDT 24
Finished May 16 02:19:38 PM PDT 24
Peak memory 202200 kb
Host smart-4ce5065b-e611-4806-8a6d-d852e3973e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131994111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1131994111
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.883169356
Short name T401
Test name
Test status
Simulation time 27090898615 ps
CPU time 15.12 seconds
Started May 16 02:10:54 PM PDT 24
Finished May 16 02:11:10 PM PDT 24
Peak memory 201600 kb
Host smart-9f8bf308-0252-4451-a93a-fc1bda363d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883169356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.883169356
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.908313735
Short name T403
Test name
Test status
Simulation time 4321824102 ps
CPU time 3.75 seconds
Started May 16 02:10:54 PM PDT 24
Finished May 16 02:10:59 PM PDT 24
Peak memory 201676 kb
Host smart-a00f09e9-f4c2-4e02-8de3-d8a02a80afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908313735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.908313735
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.752051415
Short name T379
Test name
Test status
Simulation time 5858370518 ps
CPU time 14.73 seconds
Started May 16 02:10:42 PM PDT 24
Finished May 16 02:10:58 PM PDT 24
Peak memory 201660 kb
Host smart-091e56d4-7dd3-40b4-9ebb-a4da247da0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752051415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.752051415
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.841919276
Short name T69
Test name
Test status
Simulation time 325816932767 ps
CPU time 743.59 seconds
Started May 16 02:10:55 PM PDT 24
Finished May 16 02:23:20 PM PDT 24
Peak memory 201844 kb
Host smart-b0041bd8-ebcf-4f52-ad34-6685e6dc628f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841919276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
841919276
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3727795139
Short name T60
Test name
Test status
Simulation time 72278367859 ps
CPU time 61.01 seconds
Started May 16 02:10:54 PM PDT 24
Finished May 16 02:11:56 PM PDT 24
Peak memory 212088 kb
Host smart-44be27d9-4d49-4736-8a61-958fa907cdb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727795139 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3727795139
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3669884750
Short name T630
Test name
Test status
Simulation time 351012506 ps
CPU time 0.75 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:11:09 PM PDT 24
Peak memory 201536 kb
Host smart-cb9e7171-22b2-4780-a743-2fd927ba8f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669884750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3669884750
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1726880459
Short name T619
Test name
Test status
Simulation time 192153791074 ps
CPU time 117.65 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:13:05 PM PDT 24
Peak memory 201824 kb
Host smart-5bfe13dc-f9a8-49e1-9d2e-c52d56136924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726880459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1726880459
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1504078911
Short name T151
Test name
Test status
Simulation time 164276869636 ps
CPU time 389.5 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:17:38 PM PDT 24
Peak memory 201728 kb
Host smart-6d89cf01-f11e-4c54-8181-2ec6c1cdf4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504078911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1504078911
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3639289753
Short name T209
Test name
Test status
Simulation time 495839467538 ps
CPU time 1143.24 seconds
Started May 16 02:11:05 PM PDT 24
Finished May 16 02:30:10 PM PDT 24
Peak memory 201804 kb
Host smart-4139afff-37b0-4ea5-8100-baf0628f0c7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639289753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3639289753
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2934584382
Short name T560
Test name
Test status
Simulation time 162580910675 ps
CPU time 108.61 seconds
Started May 16 02:11:07 PM PDT 24
Finished May 16 02:12:57 PM PDT 24
Peak memory 201772 kb
Host smart-99f0754a-8770-48ba-abeb-7a6cbee573b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934584382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2934584382
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.351180187
Short name T420
Test name
Test status
Simulation time 163944382886 ps
CPU time 194.74 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:14:23 PM PDT 24
Peak memory 201824 kb
Host smart-f0606f81-93bf-417d-8670-5dfdcbb2b760
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=351180187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.351180187
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3376219781
Short name T623
Test name
Test status
Simulation time 200666906234 ps
CPU time 440.05 seconds
Started May 16 02:11:07 PM PDT 24
Finished May 16 02:18:29 PM PDT 24
Peak memory 201824 kb
Host smart-244853f1-4f72-4d60-8873-562a8cd0a6f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376219781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3376219781
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3531965071
Short name T84
Test name
Test status
Simulation time 138270704866 ps
CPU time 412.59 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:18:01 PM PDT 24
Peak memory 202092 kb
Host smart-b19b8cc0-5313-460b-be2d-7ef724afd6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531965071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3531965071
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1095286207
Short name T591
Test name
Test status
Simulation time 34030187440 ps
CPU time 69.48 seconds
Started May 16 02:11:07 PM PDT 24
Finished May 16 02:12:18 PM PDT 24
Peak memory 201616 kb
Host smart-4bc579bb-553c-4d63-b250-60046e432f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095286207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1095286207
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3620484912
Short name T573
Test name
Test status
Simulation time 4872704077 ps
CPU time 3.65 seconds
Started May 16 02:11:05 PM PDT 24
Finished May 16 02:11:10 PM PDT 24
Peak memory 201648 kb
Host smart-d727885e-aba2-41f9-bf11-810acae1aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620484912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3620484912
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3390724522
Short name T495
Test name
Test status
Simulation time 5812081864 ps
CPU time 15.25 seconds
Started May 16 02:11:05 PM PDT 24
Finished May 16 02:11:21 PM PDT 24
Peak memory 201676 kb
Host smart-4dfd33b4-ab3e-4e58-afa4-8b0ac7c8eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390724522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3390724522
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2361563785
Short name T186
Test name
Test status
Simulation time 347957474507 ps
CPU time 697.79 seconds
Started May 16 02:11:06 PM PDT 24
Finished May 16 02:22:45 PM PDT 24
Peak memory 202164 kb
Host smart-710f9540-62ac-4c18-964e-61d99b1f91b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361563785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2361563785
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.580761901
Short name T639
Test name
Test status
Simulation time 352457453 ps
CPU time 0.88 seconds
Started May 16 02:11:29 PM PDT 24
Finished May 16 02:11:32 PM PDT 24
Peak memory 201508 kb
Host smart-31cc901d-fa53-4478-ad7a-477ce4377d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580761901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.580761901
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2774428511
Short name T203
Test name
Test status
Simulation time 362186269868 ps
CPU time 464.83 seconds
Started May 16 02:11:27 PM PDT 24
Finished May 16 02:19:13 PM PDT 24
Peak memory 201832 kb
Host smart-313d9751-d9f1-4b37-9cf6-19f6b8300a68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774428511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2774428511
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1725275291
Short name T330
Test name
Test status
Simulation time 160066084402 ps
CPU time 100.33 seconds
Started May 16 02:11:16 PM PDT 24
Finished May 16 02:12:58 PM PDT 24
Peak memory 201816 kb
Host smart-3da0aed1-72c1-4069-b7ef-cd956836d461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725275291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1725275291
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1145527843
Short name T512
Test name
Test status
Simulation time 319796269482 ps
CPU time 576.84 seconds
Started May 16 02:11:16 PM PDT 24
Finished May 16 02:20:55 PM PDT 24
Peak memory 201848 kb
Host smart-dd8237db-dc53-44fa-b36a-c132d6cbeea9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145527843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1145527843
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3921825824
Short name T335
Test name
Test status
Simulation time 324791445625 ps
CPU time 463.21 seconds
Started May 16 02:11:16 PM PDT 24
Finished May 16 02:19:00 PM PDT 24
Peak memory 201816 kb
Host smart-bf9dc9af-591d-4b0c-acd7-c244e492c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921825824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3921825824
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.402164841
Short name T40
Test name
Test status
Simulation time 163230454640 ps
CPU time 203.13 seconds
Started May 16 02:11:16 PM PDT 24
Finished May 16 02:14:41 PM PDT 24
Peak memory 201912 kb
Host smart-f0d4392c-ceea-40e8-8c86-10b07da81085
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=402164841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.402164841
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3116430795
Short name T7
Test name
Test status
Simulation time 174614643344 ps
CPU time 399.62 seconds
Started May 16 02:11:18 PM PDT 24
Finished May 16 02:17:59 PM PDT 24
Peak memory 201800 kb
Host smart-fb702b5f-9c3c-4749-bac0-810af9ff0e5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116430795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3116430795
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1809988504
Short name T660
Test name
Test status
Simulation time 391655044988 ps
CPU time 471.57 seconds
Started May 16 02:11:28 PM PDT 24
Finished May 16 02:19:21 PM PDT 24
Peak memory 201856 kb
Host smart-bb6a832d-531c-4825-8b80-5a90e4184496
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809988504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1809988504
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4224891933
Short name T188
Test name
Test status
Simulation time 100001018015 ps
CPU time 411.14 seconds
Started May 16 02:11:30 PM PDT 24
Finished May 16 02:18:23 PM PDT 24
Peak memory 202112 kb
Host smart-5b0e1d65-3c3f-469d-9556-372ba487c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224891933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4224891933
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3994365023
Short name T717
Test name
Test status
Simulation time 28191894728 ps
CPU time 36.57 seconds
Started May 16 02:11:29 PM PDT 24
Finished May 16 02:12:07 PM PDT 24
Peak memory 201640 kb
Host smart-033d49a9-fd60-4a0e-8dc8-f67d1ad06e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994365023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3994365023
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.604146692
Short name T626
Test name
Test status
Simulation time 4769923983 ps
CPU time 3.26 seconds
Started May 16 02:11:27 PM PDT 24
Finished May 16 02:11:32 PM PDT 24
Peak memory 201660 kb
Host smart-a7abdbed-6efc-4a9c-ac69-d75151d4c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604146692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.604146692
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3769574590
Short name T570
Test name
Test status
Simulation time 5642488979 ps
CPU time 13.52 seconds
Started May 16 02:11:17 PM PDT 24
Finished May 16 02:11:32 PM PDT 24
Peak memory 201652 kb
Host smart-c88da353-e389-458f-b84b-c88f819452cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769574590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3769574590
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2167712959
Short name T583
Test name
Test status
Simulation time 44652960370 ps
CPU time 95.48 seconds
Started May 16 02:11:27 PM PDT 24
Finished May 16 02:13:04 PM PDT 24
Peak memory 210160 kb
Host smart-5f6a8d6e-7529-45c2-84f7-cad487b2f112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167712959 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2167712959
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3266325919
Short name T359
Test name
Test status
Simulation time 454049393 ps
CPU time 0.91 seconds
Started May 16 02:11:40 PM PDT 24
Finished May 16 02:11:42 PM PDT 24
Peak memory 201436 kb
Host smart-07fc2fe3-a466-4619-ab02-6811d7abac34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266325919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3266325919
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.778274372
Short name T712
Test name
Test status
Simulation time 166555532577 ps
CPU time 39.35 seconds
Started May 16 02:11:37 PM PDT 24
Finished May 16 02:12:18 PM PDT 24
Peak memory 201824 kb
Host smart-39d63850-3265-4ee2-8a05-c7c3479247fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778274372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.778274372
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.604830037
Short name T292
Test name
Test status
Simulation time 163061381602 ps
CPU time 182.06 seconds
Started May 16 02:11:36 PM PDT 24
Finished May 16 02:14:40 PM PDT 24
Peak memory 201804 kb
Host smart-14b4d711-24c5-4b4f-9a33-cdeedfafc286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604830037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.604830037
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4201592544
Short name T205
Test name
Test status
Simulation time 327060020117 ps
CPU time 411.6 seconds
Started May 16 02:11:37 PM PDT 24
Finished May 16 02:18:31 PM PDT 24
Peak memory 201784 kb
Host smart-97ddbb8d-b062-4015-ba37-f77d97f19c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201592544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4201592544
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.912431185
Short name T710
Test name
Test status
Simulation time 164066468859 ps
CPU time 99.82 seconds
Started May 16 02:11:37 PM PDT 24
Finished May 16 02:13:18 PM PDT 24
Peak memory 201772 kb
Host smart-622f45f7-c9ac-4fe4-80cc-25ebf4237bac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=912431185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.912431185
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3906390618
Short name T444
Test name
Test status
Simulation time 158148704141 ps
CPU time 149.15 seconds
Started May 16 02:11:29 PM PDT 24
Finished May 16 02:14:00 PM PDT 24
Peak memory 201748 kb
Host smart-e2a40e34-1c69-4d0e-b71c-11f027c98692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906390618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3906390618
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3115114187
Short name T571
Test name
Test status
Simulation time 167165327766 ps
CPU time 383.03 seconds
Started May 16 02:11:27 PM PDT 24
Finished May 16 02:17:51 PM PDT 24
Peak memory 201828 kb
Host smart-c03e604f-9c74-449e-8af8-0882befbb3fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115114187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3115114187
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.922273946
Short name T326
Test name
Test status
Simulation time 202280019670 ps
CPU time 121.76 seconds
Started May 16 02:11:38 PM PDT 24
Finished May 16 02:13:41 PM PDT 24
Peak memory 201812 kb
Host smart-e4320925-9fb5-4ab5-a6b6-2d4cfc096c63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922273946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.922273946
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3286439946
Short name T794
Test name
Test status
Simulation time 607123374631 ps
CPU time 1403.58 seconds
Started May 16 02:11:38 PM PDT 24
Finished May 16 02:35:03 PM PDT 24
Peak memory 201888 kb
Host smart-9c7e6958-2738-406d-969b-0cf5be20a92d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286439946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3286439946
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3019169985
Short name T578
Test name
Test status
Simulation time 103972508702 ps
CPU time 409.7 seconds
Started May 16 02:11:41 PM PDT 24
Finished May 16 02:18:32 PM PDT 24
Peak memory 202108 kb
Host smart-d24aa29c-d2f1-4263-901e-6db062fcbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019169985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3019169985
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2521049170
Short name T774
Test name
Test status
Simulation time 22874109778 ps
CPU time 27.53 seconds
Started May 16 02:11:37 PM PDT 24
Finished May 16 02:12:07 PM PDT 24
Peak memory 201616 kb
Host smart-6d650a52-b3a3-4d78-9589-e6a46e6ddd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521049170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2521049170
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3552666120
Short name T662
Test name
Test status
Simulation time 4469661997 ps
CPU time 6.51 seconds
Started May 16 02:11:39 PM PDT 24
Finished May 16 02:11:47 PM PDT 24
Peak memory 201652 kb
Host smart-9e005150-74c1-47fb-8cff-21ce97f7282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552666120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3552666120
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.702337761
Short name T29
Test name
Test status
Simulation time 5667982662 ps
CPU time 13.92 seconds
Started May 16 02:11:28 PM PDT 24
Finished May 16 02:11:43 PM PDT 24
Peak memory 201616 kb
Host smart-af6749ff-2eff-455d-bb70-fe9b598b9165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702337761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.702337761
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2334261696
Short name T341
Test name
Test status
Simulation time 287244692916 ps
CPU time 943.12 seconds
Started May 16 02:11:38 PM PDT 24
Finished May 16 02:27:23 PM PDT 24
Peak memory 210380 kb
Host smart-d664104a-187b-4d9e-85f6-ee0a6773563b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334261696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2334261696
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2080665597
Short name T96
Test name
Test status
Simulation time 396015198 ps
CPU time 1.58 seconds
Started May 16 02:11:47 PM PDT 24
Finished May 16 02:11:50 PM PDT 24
Peak memory 201532 kb
Host smart-83b8f860-3cba-40a3-8e73-5f3ac863ba48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080665597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2080665597
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3245988990
Short name T767
Test name
Test status
Simulation time 525113318180 ps
CPU time 314.35 seconds
Started May 16 02:11:50 PM PDT 24
Finished May 16 02:17:05 PM PDT 24
Peak memory 201908 kb
Host smart-318fa3c5-b739-415a-b833-650c1468fbc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245988990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3245988990
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1868469848
Short name T314
Test name
Test status
Simulation time 550140260562 ps
CPU time 342.27 seconds
Started May 16 02:11:49 PM PDT 24
Finished May 16 02:17:32 PM PDT 24
Peak memory 201780 kb
Host smart-06472d8e-8213-4103-bf7b-0b4157e18483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868469848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1868469848
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3449507329
Short name T727
Test name
Test status
Simulation time 160485706647 ps
CPU time 196.67 seconds
Started May 16 02:11:38 PM PDT 24
Finished May 16 02:14:56 PM PDT 24
Peak memory 201816 kb
Host smart-8d627797-7e16-4bf9-acab-99ccd14b856a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449507329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3449507329
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3752655333
Short name T334
Test name
Test status
Simulation time 490108909539 ps
CPU time 712.78 seconds
Started May 16 02:11:37 PM PDT 24
Finished May 16 02:23:32 PM PDT 24
Peak memory 201764 kb
Host smart-032b78dd-9f33-4014-828d-3d7f3106a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752655333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3752655333
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2155898543
Short name T406
Test name
Test status
Simulation time 159460707804 ps
CPU time 177.43 seconds
Started May 16 02:11:36 PM PDT 24
Finished May 16 02:14:35 PM PDT 24
Peak memory 201828 kb
Host smart-39dab43f-b9e2-45c7-ba64-e7cf16f10ccd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155898543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2155898543
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3010198563
Short name T540
Test name
Test status
Simulation time 536002191909 ps
CPU time 1312.56 seconds
Started May 16 02:11:44 PM PDT 24
Finished May 16 02:33:37 PM PDT 24
Peak memory 201912 kb
Host smart-fc140311-4539-4020-8390-44b574b6d1f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010198563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3010198563
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4062895042
Short name T482
Test name
Test status
Simulation time 386511517196 ps
CPU time 873.79 seconds
Started May 16 02:11:48 PM PDT 24
Finished May 16 02:26:23 PM PDT 24
Peak memory 201776 kb
Host smart-04d86cfe-ee15-40c1-927b-749aff6579b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062895042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4062895042
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3700162290
Short name T156
Test name
Test status
Simulation time 89407033768 ps
CPU time 380.84 seconds
Started May 16 02:11:46 PM PDT 24
Finished May 16 02:18:09 PM PDT 24
Peak memory 202040 kb
Host smart-b641fe8b-91d1-4eef-922a-ce341083c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700162290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3700162290
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.53038332
Short name T429
Test name
Test status
Simulation time 38938126466 ps
CPU time 85.03 seconds
Started May 16 02:11:47 PM PDT 24
Finished May 16 02:13:13 PM PDT 24
Peak memory 201600 kb
Host smart-ae8cc14d-e49d-44a2-8875-61f746a6846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53038332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.53038332
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3478488633
Short name T10
Test name
Test status
Simulation time 4887527411 ps
CPU time 1.86 seconds
Started May 16 02:11:48 PM PDT 24
Finished May 16 02:11:51 PM PDT 24
Peak memory 201664 kb
Host smart-a8a6f1de-5006-4fea-96df-1e8e1dd2e93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478488633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3478488633
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2744341492
Short name T657
Test name
Test status
Simulation time 5794622793 ps
CPU time 13.81 seconds
Started May 16 02:11:38 PM PDT 24
Finished May 16 02:11:53 PM PDT 24
Peak memory 201620 kb
Host smart-d20fc386-9929-4d59-80d8-7b7150a67434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744341492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2744341492
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2694517184
Short name T526
Test name
Test status
Simulation time 180044946449 ps
CPU time 335.15 seconds
Started May 16 02:11:46 PM PDT 24
Finished May 16 02:17:22 PM PDT 24
Peak memory 201812 kb
Host smart-f3c174d5-a571-43c0-918a-8aeea4f8b736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694517184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2694517184
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1357413468
Short name T614
Test name
Test status
Simulation time 431919331 ps
CPU time 1.14 seconds
Started May 16 02:11:59 PM PDT 24
Finished May 16 02:12:01 PM PDT 24
Peak memory 201504 kb
Host smart-cdcda382-1bd5-4273-8ebc-a5dd64080bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357413468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1357413468
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1090950361
Short name T704
Test name
Test status
Simulation time 161821034449 ps
CPU time 203.42 seconds
Started May 16 02:11:58 PM PDT 24
Finished May 16 02:15:23 PM PDT 24
Peak memory 201844 kb
Host smart-86c2e8cc-70e9-4fc9-877d-781ef5f88561
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090950361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1090950361
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1595033867
Short name T291
Test name
Test status
Simulation time 530513332188 ps
CPU time 1256.04 seconds
Started May 16 02:11:57 PM PDT 24
Finished May 16 02:32:53 PM PDT 24
Peak memory 201808 kb
Host smart-8cefe40d-4d9e-4f4d-9ebb-f8c1d42c8666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595033867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1595033867
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.200801357
Short name T779
Test name
Test status
Simulation time 487045059681 ps
CPU time 575.36 seconds
Started May 16 02:11:48 PM PDT 24
Finished May 16 02:21:25 PM PDT 24
Peak memory 201924 kb
Host smart-5b4d8811-8120-4175-b827-e2bc27843342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200801357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.200801357
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1606430445
Short name T533
Test name
Test status
Simulation time 492890612367 ps
CPU time 635.65 seconds
Started May 16 02:11:48 PM PDT 24
Finished May 16 02:22:25 PM PDT 24
Peak memory 201784 kb
Host smart-ca9f57eb-e22e-4be5-b871-9f21184e6ee5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606430445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1606430445
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.133507411
Short name T233
Test name
Test status
Simulation time 328001144448 ps
CPU time 192.27 seconds
Started May 16 02:11:47 PM PDT 24
Finished May 16 02:15:00 PM PDT 24
Peak memory 201904 kb
Host smart-76401552-0977-40a4-bffb-eb2201b1c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133507411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.133507411
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1741736538
Short name T671
Test name
Test status
Simulation time 495070887821 ps
CPU time 302.68 seconds
Started May 16 02:11:46 PM PDT 24
Finished May 16 02:16:51 PM PDT 24
Peak memory 201804 kb
Host smart-2ac06704-2c14-4b4a-b3e9-e5aa43a419fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741736538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1741736538
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.231470564
Short name T606
Test name
Test status
Simulation time 410169197124 ps
CPU time 949.34 seconds
Started May 16 02:11:51 PM PDT 24
Finished May 16 02:27:42 PM PDT 24
Peak memory 201824 kb
Host smart-94e09f9a-8c92-4c4f-8fa3-416c7b7c8525
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231470564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.231470564
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.45555394
Short name T436
Test name
Test status
Simulation time 25261236509 ps
CPU time 52.75 seconds
Started May 16 02:11:59 PM PDT 24
Finished May 16 02:12:53 PM PDT 24
Peak memory 201628 kb
Host smart-e2b8d89d-22c7-4eba-9f67-c2f7c46f2979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45555394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.45555394
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1636512641
Short name T357
Test name
Test status
Simulation time 4084227242 ps
CPU time 10.42 seconds
Started May 16 02:11:58 PM PDT 24
Finished May 16 02:12:09 PM PDT 24
Peak memory 201600 kb
Host smart-0b6dffe0-1025-4a26-bd13-e100a802b05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636512641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1636512641
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1134516224
Short name T757
Test name
Test status
Simulation time 5900645512 ps
CPU time 12.73 seconds
Started May 16 02:11:47 PM PDT 24
Finished May 16 02:12:01 PM PDT 24
Peak memory 201664 kb
Host smart-9c6915af-fbf9-4b8e-ae81-f2b02285b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134516224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1134516224
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1404106932
Short name T759
Test name
Test status
Simulation time 332653271066 ps
CPU time 836.22 seconds
Started May 16 02:11:58 PM PDT 24
Finished May 16 02:25:56 PM PDT 24
Peak memory 201824 kb
Host smart-807404c4-4866-4b07-a16f-cf1b8e3b5cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404106932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1404106932
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2718913913
Short name T71
Test name
Test status
Simulation time 435177000 ps
CPU time 1.16 seconds
Started May 16 02:12:12 PM PDT 24
Finished May 16 02:12:14 PM PDT 24
Peak memory 201512 kb
Host smart-b710af98-28ef-4552-b8d1-36a6958a9693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718913913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2718913913
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.4210569329
Short name T325
Test name
Test status
Simulation time 163503368926 ps
CPU time 357.15 seconds
Started May 16 02:12:10 PM PDT 24
Finished May 16 02:18:08 PM PDT 24
Peak memory 201800 kb
Host smart-2ab5afbb-bf2a-435a-a9e2-4b283ef42309
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210569329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.4210569329
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1832419256
Short name T648
Test name
Test status
Simulation time 316243374525 ps
CPU time 195 seconds
Started May 16 02:12:09 PM PDT 24
Finished May 16 02:15:26 PM PDT 24
Peak memory 201700 kb
Host smart-10e55a45-28fd-4caf-a79b-255cc0e3f2ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832419256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1832419256
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2008246666
Short name T309
Test name
Test status
Simulation time 166736856648 ps
CPU time 355.86 seconds
Started May 16 02:12:08 PM PDT 24
Finished May 16 02:18:05 PM PDT 24
Peak memory 201876 kb
Host smart-bf00ed57-3ea8-4c71-98b0-6d2f2784def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008246666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2008246666
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1727028358
Short name T133
Test name
Test status
Simulation time 329103640708 ps
CPU time 43.13 seconds
Started May 16 02:12:08 PM PDT 24
Finished May 16 02:12:52 PM PDT 24
Peak memory 201892 kb
Host smart-b9558321-bd85-4337-8eea-980d5e6e477f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727028358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1727028358
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1886148113
Short name T180
Test name
Test status
Simulation time 210634671588 ps
CPU time 230.32 seconds
Started May 16 02:12:11 PM PDT 24
Finished May 16 02:16:02 PM PDT 24
Peak memory 201848 kb
Host smart-ca2bee50-f48f-41d5-9784-e35f0d4792af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886148113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1886148113
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.485332050
Short name T590
Test name
Test status
Simulation time 599171917458 ps
CPU time 441.69 seconds
Started May 16 02:12:08 PM PDT 24
Finished May 16 02:19:31 PM PDT 24
Peak memory 201756 kb
Host smart-386dff15-8276-44ff-bca3-3fd08fa06063
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485332050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.485332050
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2792385599
Short name T787
Test name
Test status
Simulation time 133157541580 ps
CPU time 521.46 seconds
Started May 16 02:12:09 PM PDT 24
Finished May 16 02:20:53 PM PDT 24
Peak memory 202148 kb
Host smart-441f7c57-6358-4bb2-b827-6ac335a1d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792385599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2792385599
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2234871755
Short name T615
Test name
Test status
Simulation time 46893745004 ps
CPU time 109.2 seconds
Started May 16 02:12:08 PM PDT 24
Finished May 16 02:13:59 PM PDT 24
Peak memory 201628 kb
Host smart-0be25c6d-6aac-4cae-9a45-3a7d1f6b732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234871755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2234871755
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3715498287
Short name T719
Test name
Test status
Simulation time 4921991437 ps
CPU time 6.82 seconds
Started May 16 02:12:10 PM PDT 24
Finished May 16 02:12:18 PM PDT 24
Peak memory 201660 kb
Host smart-9605af2b-b344-4204-98b1-9307c8b754c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715498287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3715498287
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3559779432
Short name T488
Test name
Test status
Simulation time 6111187366 ps
CPU time 1.86 seconds
Started May 16 02:12:12 PM PDT 24
Finished May 16 02:12:15 PM PDT 24
Peak memory 201644 kb
Host smart-0cc458cc-f72b-4e6b-a85d-9247ab412814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559779432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3559779432
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.864368840
Short name T445
Test name
Test status
Simulation time 317066344664 ps
CPU time 779.31 seconds
Started May 16 02:12:11 PM PDT 24
Finished May 16 02:25:12 PM PDT 24
Peak memory 210312 kb
Host smart-08720bd9-f5b9-46f3-a2f0-888ea0f8edec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864368840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
864368840
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2897606040
Short name T42
Test name
Test status
Simulation time 81176123477 ps
CPU time 60.31 seconds
Started May 16 02:12:10 PM PDT 24
Finished May 16 02:13:11 PM PDT 24
Peak memory 201840 kb
Host smart-4fcb0a2a-ec84-4b5c-87de-4fc939bd49bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897606040 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2897606040
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2638909863
Short name T585
Test name
Test status
Simulation time 395339424 ps
CPU time 0.82 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:12:23 PM PDT 24
Peak memory 201508 kb
Host smart-54cb12f3-8d4e-4f01-ade6-ed5e99e65755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638909863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2638909863
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2166175591
Short name T506
Test name
Test status
Simulation time 499757196560 ps
CPU time 937.26 seconds
Started May 16 02:12:09 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 201912 kb
Host smart-e0a082b9-397a-4f05-a642-c9c5b4b4bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166175591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2166175591
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2184705214
Short name T478
Test name
Test status
Simulation time 322894777809 ps
CPU time 714.39 seconds
Started May 16 02:12:20 PM PDT 24
Finished May 16 02:24:16 PM PDT 24
Peak memory 201804 kb
Host smart-ff66e50d-8965-477d-b39e-f426981c7a4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184705214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2184705214
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1954347054
Short name T471
Test name
Test status
Simulation time 322733505788 ps
CPU time 133.28 seconds
Started May 16 02:12:09 PM PDT 24
Finished May 16 02:14:24 PM PDT 24
Peak memory 201776 kb
Host smart-26febe08-27fb-4fd9-b758-d570a530b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954347054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1954347054
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.851129223
Short name T536
Test name
Test status
Simulation time 160553361838 ps
CPU time 378.49 seconds
Started May 16 02:12:10 PM PDT 24
Finished May 16 02:18:30 PM PDT 24
Peak memory 201804 kb
Host smart-adf69cc1-22f4-4312-a874-8869b5d317da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=851129223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.851129223
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3325855121
Short name T353
Test name
Test status
Simulation time 393610396887 ps
CPU time 632.71 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:22:55 PM PDT 24
Peak memory 201808 kb
Host smart-5d870226-7ec4-44bf-be25-f0854f71953c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325855121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3325855121
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1313790780
Short name T462
Test name
Test status
Simulation time 84492343399 ps
CPU time 426.24 seconds
Started May 16 02:12:18 PM PDT 24
Finished May 16 02:19:25 PM PDT 24
Peak memory 202148 kb
Host smart-a8d07ef7-5bb7-4e3d-adea-af38816d02c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313790780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1313790780
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3360456609
Short name T481
Test name
Test status
Simulation time 40779967413 ps
CPU time 84.82 seconds
Started May 16 02:12:20 PM PDT 24
Finished May 16 02:13:46 PM PDT 24
Peak memory 201616 kb
Host smart-0b816632-6ad6-48b9-a633-46d0eb389f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360456609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3360456609
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3563378654
Short name T539
Test name
Test status
Simulation time 2980227176 ps
CPU time 2.42 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:12:24 PM PDT 24
Peak memory 201588 kb
Host smart-52684d95-da60-409c-bd97-dddeb27d1670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563378654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3563378654
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2029423075
Short name T756
Test name
Test status
Simulation time 6113821152 ps
CPU time 14.98 seconds
Started May 16 02:12:09 PM PDT 24
Finished May 16 02:12:26 PM PDT 24
Peak memory 201728 kb
Host smart-7cd8002a-71d1-48b8-ba92-8e92b6d41096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029423075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2029423075
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.852285615
Short name T218
Test name
Test status
Simulation time 334614408937 ps
CPU time 61.24 seconds
Started May 16 02:12:19 PM PDT 24
Finished May 16 02:13:23 PM PDT 24
Peak memory 201896 kb
Host smart-c978a6ae-1965-48d1-938d-6eacd8e4b078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852285615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
852285615
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3465010341
Short name T350
Test name
Test status
Simulation time 101056884815 ps
CPU time 153.2 seconds
Started May 16 02:12:20 PM PDT 24
Finished May 16 02:14:55 PM PDT 24
Peak memory 210520 kb
Host smart-dc774165-423f-4414-b3c3-ec5121c281d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465010341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3465010341
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3966367207
Short name T368
Test name
Test status
Simulation time 327848999 ps
CPU time 0.78 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:05:52 PM PDT 24
Peak memory 201500 kb
Host smart-6b7d0745-70fb-4ef0-8f33-ee625d8435ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966367207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3966367207
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2672392169
Short name T764
Test name
Test status
Simulation time 324896535039 ps
CPU time 211.65 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:09:20 PM PDT 24
Peak memory 201816 kb
Host smart-254877b3-a815-47ec-9308-d1fc5abfc18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672392169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2672392169
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2485191257
Short name T620
Test name
Test status
Simulation time 486232262370 ps
CPU time 631.13 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:16:23 PM PDT 24
Peak memory 201812 kb
Host smart-51300cad-db2c-4b71-a269-adfbc9767de6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485191257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2485191257
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3690447728
Short name T165
Test name
Test status
Simulation time 496818495132 ps
CPU time 283.23 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:10:33 PM PDT 24
Peak memory 201820 kb
Host smart-8d359cd2-669b-407c-9d74-715b7880c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690447728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3690447728
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1951092729
Short name T679
Test name
Test status
Simulation time 165491621361 ps
CPU time 92.68 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:07:19 PM PDT 24
Peak memory 201804 kb
Host smart-c3ef81a2-c0b4-4d7e-9f36-5fc88bd1bfff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951092729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1951092729
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2284996099
Short name T34
Test name
Test status
Simulation time 165045040992 ps
CPU time 99.09 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:07:28 PM PDT 24
Peak memory 201820 kb
Host smart-cd8696e9-c92c-43f0-a3c7-302b7bcbb358
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284996099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2284996099
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2816561266
Short name T131
Test name
Test status
Simulation time 191975835522 ps
CPU time 24.48 seconds
Started May 16 02:05:49 PM PDT 24
Finished May 16 02:06:17 PM PDT 24
Peak memory 201784 kb
Host smart-28529b36-349b-4b13-8b48-199821dd9fa2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816561266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2816561266
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3394567683
Short name T46
Test name
Test status
Simulation time 126751837986 ps
CPU time 493.42 seconds
Started May 16 02:05:48 PM PDT 24
Finished May 16 02:14:05 PM PDT 24
Peak memory 202124 kb
Host smart-68b584a0-ef2b-47f9-9729-f4250acc616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394567683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3394567683
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2867270085
Short name T356
Test name
Test status
Simulation time 23759033275 ps
CPU time 13.92 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:06:05 PM PDT 24
Peak memory 201544 kb
Host smart-f67f4872-a9d6-453a-bb06-d522a73fb065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867270085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2867270085
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2843075763
Short name T800
Test name
Test status
Simulation time 3062593634 ps
CPU time 2.43 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:05:53 PM PDT 24
Peak memory 201580 kb
Host smart-553a04b2-23cf-464d-8c5f-4603b2e5fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843075763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2843075763
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3333814183
Short name T65
Test name
Test status
Simulation time 8714119806 ps
CPU time 19.06 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:06:08 PM PDT 24
Peak memory 218416 kb
Host smart-93042804-7adf-4982-8503-e73b8a3a5ed3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333814183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3333814183
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1418049920
Short name T708
Test name
Test status
Simulation time 5925713552 ps
CPU time 3.67 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:05:51 PM PDT 24
Peak memory 201608 kb
Host smart-2bac1469-fa29-4ad7-95d1-1ad92a8b7f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418049920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1418049920
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2081728972
Short name T190
Test name
Test status
Simulation time 448977976801 ps
CPU time 533.03 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:14:44 PM PDT 24
Peak memory 202224 kb
Host smart-1afeb140-85cb-4f56-8d1a-f66439daf95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081728972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2081728972
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1085755467
Short name T24
Test name
Test status
Simulation time 52280378346 ps
CPU time 108.22 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:07:39 PM PDT 24
Peak memory 210536 kb
Host smart-355af6c2-5db3-4c17-86cc-466b433ac062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085755467 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1085755467
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2965496540
Short name T70
Test name
Test status
Simulation time 485122913 ps
CPU time 0.88 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:12:48 PM PDT 24
Peak memory 201536 kb
Host smart-86bab68a-7252-48e2-a617-c0fddcdb4358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965496540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2965496540
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2898678531
Short name T247
Test name
Test status
Simulation time 172436414515 ps
CPU time 62.83 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:13:50 PM PDT 24
Peak memory 201808 kb
Host smart-38d8e421-8f91-4446-985f-23e904e2fcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898678531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2898678531
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2994971192
Short name T691
Test name
Test status
Simulation time 490315158805 ps
CPU time 1116.61 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:30:59 PM PDT 24
Peak memory 201732 kb
Host smart-f62423dc-a333-4d20-9915-49d07df30f7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994971192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2994971192
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1977209608
Short name T705
Test name
Test status
Simulation time 163800664478 ps
CPU time 107.64 seconds
Started May 16 02:12:21 PM PDT 24
Finished May 16 02:14:10 PM PDT 24
Peak memory 201804 kb
Host smart-c75b2c8c-bb3f-4e11-ac4f-628704a276e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977209608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1977209608
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2561571654
Short name T633
Test name
Test status
Simulation time 486101188487 ps
CPU time 312.37 seconds
Started May 16 02:12:19 PM PDT 24
Finished May 16 02:17:33 PM PDT 24
Peak memory 201740 kb
Host smart-0e5847ed-eaed-4330-8991-9c8eda5d1eb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561571654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2561571654
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.517839443
Short name T280
Test name
Test status
Simulation time 398548069225 ps
CPU time 902.9 seconds
Started May 16 02:12:32 PM PDT 24
Finished May 16 02:27:37 PM PDT 24
Peak memory 201852 kb
Host smart-02a5a5e3-4024-4196-977f-aa57485d1836
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517839443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.517839443
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.76015827
Short name T722
Test name
Test status
Simulation time 194922524887 ps
CPU time 433.94 seconds
Started May 16 02:12:44 PM PDT 24
Finished May 16 02:20:00 PM PDT 24
Peak memory 201780 kb
Host smart-2d5200bb-42d5-43e5-b3b9-c08d09103528
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76015827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.a
dc_ctrl_filters_wakeup_fixed.76015827
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2573623509
Short name T423
Test name
Test status
Simulation time 80558080174 ps
CPU time 371.86 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:18:58 PM PDT 24
Peak memory 202128 kb
Host smart-23be9084-a3a0-4a3f-a6d2-eff7a7e3057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573623509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2573623509
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1633524821
Short name T637
Test name
Test status
Simulation time 30274883660 ps
CPU time 18.11 seconds
Started May 16 02:12:44 PM PDT 24
Finished May 16 02:13:04 PM PDT 24
Peak memory 201656 kb
Host smart-7beeab36-7c62-4738-ab90-8b31a8f2b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633524821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1633524821
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.201911046
Short name T627
Test name
Test status
Simulation time 3197339120 ps
CPU time 2.53 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:12:49 PM PDT 24
Peak memory 201580 kb
Host smart-9cde695c-f75e-4105-a06c-b63973a9e3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201911046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.201911046
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1970629139
Short name T476
Test name
Test status
Simulation time 6101839548 ps
CPU time 3.54 seconds
Started May 16 02:12:20 PM PDT 24
Finished May 16 02:12:25 PM PDT 24
Peak memory 201620 kb
Host smart-e64b3f38-93e2-47aa-b74c-4278caffbb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970629139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1970629139
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3311690495
Short name T261
Test name
Test status
Simulation time 340864099254 ps
CPU time 749.64 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:25:16 PM PDT 24
Peak memory 201924 kb
Host smart-f2e11eca-0457-4878-bc9c-bd156b76abd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311690495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3311690495
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2424781291
Short name T41
Test name
Test status
Simulation time 19684748684 ps
CPU time 60.09 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:13:47 PM PDT 24
Peak memory 210472 kb
Host smart-7da7df56-d36d-4433-8458-2cd441ee467a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424781291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2424781291
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2622590401
Short name T16
Test name
Test status
Simulation time 560491212 ps
CPU time 0.72 seconds
Started May 16 02:13:11 PM PDT 24
Finished May 16 02:13:13 PM PDT 24
Peak memory 201532 kb
Host smart-f0302df4-54e9-40b6-93ca-b9f919ff7ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622590401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2622590401
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1822039284
Short name T388
Test name
Test status
Simulation time 487115911049 ps
CPU time 301.18 seconds
Started May 16 02:12:46 PM PDT 24
Finished May 16 02:17:48 PM PDT 24
Peak memory 201848 kb
Host smart-ddfcf4e5-ce33-403e-b612-52f1d327c713
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822039284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1822039284
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1570438825
Short name T425
Test name
Test status
Simulation time 500099769467 ps
CPU time 509.88 seconds
Started May 16 02:12:46 PM PDT 24
Finished May 16 02:21:17 PM PDT 24
Peak memory 201808 kb
Host smart-3e4efeaf-9de6-43b7-a89e-a419579db5af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570438825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1570438825
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4207098025
Short name T467
Test name
Test status
Simulation time 627398374557 ps
CPU time 396.88 seconds
Started May 16 02:12:55 PM PDT 24
Finished May 16 02:19:35 PM PDT 24
Peak memory 201768 kb
Host smart-439d1308-e02b-4692-9b3d-b353242cd3a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207098025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4207098025
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2097238789
Short name T574
Test name
Test status
Simulation time 68822205643 ps
CPU time 373.67 seconds
Started May 16 02:12:55 PM PDT 24
Finished May 16 02:19:12 PM PDT 24
Peak memory 202088 kb
Host smart-3d9b8643-fcdf-43da-a22f-de4a3c1a0502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097238789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2097238789
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.4116494433
Short name T490
Test name
Test status
Simulation time 42712124713 ps
CPU time 25.61 seconds
Started May 16 02:12:55 PM PDT 24
Finished May 16 02:13:24 PM PDT 24
Peak memory 201660 kb
Host smart-2337218f-c459-43b1-bb8a-83c1abd1d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116494433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.4116494433
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3938725474
Short name T726
Test name
Test status
Simulation time 4725937753 ps
CPU time 3.42 seconds
Started May 16 02:12:54 PM PDT 24
Finished May 16 02:13:01 PM PDT 24
Peak memory 201668 kb
Host smart-946ab556-dab6-4c71-94a4-afd18711c8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938725474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3938725474
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2598226053
Short name T441
Test name
Test status
Simulation time 5925913750 ps
CPU time 14.24 seconds
Started May 16 02:12:45 PM PDT 24
Finished May 16 02:13:01 PM PDT 24
Peak memory 201636 kb
Host smart-85f82692-1df6-4526-a0a4-4e053c7b3fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598226053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2598226053
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3377473394
Short name T541
Test name
Test status
Simulation time 135853361016 ps
CPU time 332.79 seconds
Started May 16 02:12:54 PM PDT 24
Finished May 16 02:18:30 PM PDT 24
Peak memory 202132 kb
Host smart-51524ac0-144d-4736-a9e6-6430fa41c8d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377473394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3377473394
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2267321712
Short name T182
Test name
Test status
Simulation time 153406117122 ps
CPU time 97.84 seconds
Started May 16 02:12:53 PM PDT 24
Finished May 16 02:14:33 PM PDT 24
Peak memory 210500 kb
Host smart-2137972a-f8ee-4c2a-b8f6-8549e0372119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267321712 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2267321712
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1361059783
Short name T650
Test name
Test status
Simulation time 361590188 ps
CPU time 0.85 seconds
Started May 16 02:13:09 PM PDT 24
Finished May 16 02:13:12 PM PDT 24
Peak memory 201512 kb
Host smart-0c691a94-cc65-4a50-b7d5-d0e2c6ff0524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361059783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1361059783
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3752163501
Short name T509
Test name
Test status
Simulation time 348327231524 ps
CPU time 797.57 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:26:28 PM PDT 24
Peak memory 201836 kb
Host smart-f8f2fba7-5c69-4395-8d0c-bc4aafe4f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752163501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3752163501
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.301981678
Short name T725
Test name
Test status
Simulation time 165832594377 ps
CPU time 98.09 seconds
Started May 16 02:13:09 PM PDT 24
Finished May 16 02:14:50 PM PDT 24
Peak memory 201788 kb
Host smart-1b4f37a3-95b8-44ee-b6fd-5b7dbe13d262
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=301981678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.301981678
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3297631447
Short name T749
Test name
Test status
Simulation time 491602299882 ps
CPU time 1264.54 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:34:14 PM PDT 24
Peak memory 201792 kb
Host smart-dd4c0f1d-aa5c-4d41-842d-6e28239c9749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297631447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3297631447
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.731163232
Short name T720
Test name
Test status
Simulation time 159493458194 ps
CPU time 351.08 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:18:58 PM PDT 24
Peak memory 201840 kb
Host smart-25318182-9acf-4792-9888-7bed548a73bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=731163232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.731163232
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2031952205
Short name T715
Test name
Test status
Simulation time 183165325293 ps
CPU time 441.58 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:20:28 PM PDT 24
Peak memory 201976 kb
Host smart-d539abc8-44c7-4029-906e-e510d71950c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031952205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2031952205
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1826655021
Short name T472
Test name
Test status
Simulation time 200624138091 ps
CPU time 474.27 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:21:04 PM PDT 24
Peak memory 201840 kb
Host smart-50840f05-46ff-4c9d-b355-151859d95ea8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826655021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1826655021
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1305667578
Short name T192
Test name
Test status
Simulation time 85118564054 ps
CPU time 431.55 seconds
Started May 16 02:13:12 PM PDT 24
Finished May 16 02:20:25 PM PDT 24
Peak memory 202108 kb
Host smart-8d5777a8-4a4c-4cfb-b42d-f131b5e7037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305667578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1305667578
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1322204181
Short name T367
Test name
Test status
Simulation time 29732858328 ps
CPU time 33.67 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:13:43 PM PDT 24
Peak memory 201632 kb
Host smart-db5db090-954f-4bb5-9b4b-3b15c8f87337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322204181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1322204181
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1780014680
Short name T381
Test name
Test status
Simulation time 3725453037 ps
CPU time 1.53 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:13:08 PM PDT 24
Peak memory 201588 kb
Host smart-c0743d5d-5cba-4d49-b6a5-5765f81659e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780014680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1780014680
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2951311036
Short name T366
Test name
Test status
Simulation time 6076025797 ps
CPU time 8.53 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:13:18 PM PDT 24
Peak memory 201552 kb
Host smart-0d7ce6f8-2558-429e-89ce-3fa4879934a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951311036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2951311036
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1664505349
Short name T26
Test name
Test status
Simulation time 291488541388 ps
CPU time 245.27 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:17:15 PM PDT 24
Peak memory 210604 kb
Host smart-c80af49f-1121-4b87-bbf5-58678e3faa62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664505349 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1664505349
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3043392022
Short name T732
Test name
Test status
Simulation time 515496134 ps
CPU time 0.79 seconds
Started May 16 02:13:10 PM PDT 24
Finished May 16 02:13:13 PM PDT 24
Peak memory 201532 kb
Host smart-75b3a11b-be17-431a-871e-df443279fbaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043392022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3043392022
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.220781717
Short name T136
Test name
Test status
Simulation time 191148251817 ps
CPU time 42.62 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:13:49 PM PDT 24
Peak memory 201896 kb
Host smart-cd274776-022b-44c4-b9b9-22a121a77d5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220781717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.220781717
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2457381
Short name T597
Test name
Test status
Simulation time 331914531315 ps
CPU time 203.74 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:16:30 PM PDT 24
Peak memory 201852 kb
Host smart-eeddd1f1-3f16-4232-a5e7-64f06647464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2457381
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1336784336
Short name T146
Test name
Test status
Simulation time 488041477405 ps
CPU time 315.26 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:18:26 PM PDT 24
Peak memory 201840 kb
Host smart-ca9cf527-5b03-40c1-97ca-8527da412a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336784336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1336784336
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1504167261
Short name T371
Test name
Test status
Simulation time 328052925530 ps
CPU time 229.83 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:16:55 PM PDT 24
Peak memory 201832 kb
Host smart-271152f8-78af-4865-9d38-cc9b26e86c85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504167261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1504167261
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.625756809
Short name T765
Test name
Test status
Simulation time 474874020260 ps
CPU time 324.63 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:18:35 PM PDT 24
Peak memory 201868 kb
Host smart-f424f26d-8643-4327-93db-4aafa9880a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625756809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.625756809
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1276815562
Short name T730
Test name
Test status
Simulation time 165823346400 ps
CPU time 409.44 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:19:56 PM PDT 24
Peak memory 201776 kb
Host smart-143c03f8-3280-4ff7-88b5-d9d3ef3b5af8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276815562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1276815562
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1742773532
Short name T736
Test name
Test status
Simulation time 594092212241 ps
CPU time 654.68 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:24:05 PM PDT 24
Peak memory 200920 kb
Host smart-97e3b51d-638e-4738-bac1-a5e7bc445cd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742773532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1742773532
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1748294913
Short name T781
Test name
Test status
Simulation time 196134839542 ps
CPU time 504.6 seconds
Started May 16 02:13:04 PM PDT 24
Finished May 16 02:21:29 PM PDT 24
Peak memory 201788 kb
Host smart-560a6c42-42a1-4f78-a312-793f4d84e7df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748294913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1748294913
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3290738360
Short name T513
Test name
Test status
Simulation time 124215162706 ps
CPU time 463.46 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:20:53 PM PDT 24
Peak memory 202120 kb
Host smart-0d35bb28-52f9-4999-aa4b-4258e95a9553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290738360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3290738360
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3202260115
Short name T622
Test name
Test status
Simulation time 34277424899 ps
CPU time 19.01 seconds
Started May 16 02:13:11 PM PDT 24
Finished May 16 02:13:32 PM PDT 24
Peak memory 201656 kb
Host smart-9a49de2d-45d7-448a-81bf-7d0ddedd513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202260115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3202260115
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2440082153
Short name T483
Test name
Test status
Simulation time 4363082604 ps
CPU time 3.21 seconds
Started May 16 02:13:09 PM PDT 24
Finished May 16 02:13:15 PM PDT 24
Peak memory 201636 kb
Host smart-781250ea-4b43-456b-a85e-96b2a016330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440082153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2440082153
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3736443776
Short name T554
Test name
Test status
Simulation time 5958735970 ps
CPU time 7.6 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:13:19 PM PDT 24
Peak memory 201556 kb
Host smart-de2a22a1-6890-4e45-aa5d-d2e8e95b5176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736443776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3736443776
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2304007594
Short name T718
Test name
Test status
Simulation time 548821497126 ps
CPU time 613.86 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:23:20 PM PDT 24
Peak memory 201836 kb
Host smart-21404b8c-0a24-4367-a5ef-d2bfbaba6348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304007594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2304007594
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.740620588
Short name T549
Test name
Test status
Simulation time 169385276996 ps
CPU time 160.79 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:15:50 PM PDT 24
Peak memory 217740 kb
Host smart-b6b718b1-955f-4154-9b97-17eeb0ec001c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740620588 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.740620588
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.916878107
Short name T538
Test name
Test status
Simulation time 521010746 ps
CPU time 1.83 seconds
Started May 16 02:13:18 PM PDT 24
Finished May 16 02:13:21 PM PDT 24
Peak memory 201436 kb
Host smart-facd74df-17cf-49a7-96f4-01ae89fa244d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916878107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.916878107
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1090404004
Short name T664
Test name
Test status
Simulation time 368296277299 ps
CPU time 357.87 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:19:09 PM PDT 24
Peak memory 201848 kb
Host smart-c4839a80-5640-410f-9c51-c9466c21c0fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090404004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1090404004
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1746172839
Short name T499
Test name
Test status
Simulation time 163103164657 ps
CPU time 59.19 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:14:06 PM PDT 24
Peak memory 201824 kb
Host smart-c00ae445-12a4-4754-a2c2-4baf11559659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746172839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1746172839
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3635407302
Short name T336
Test name
Test status
Simulation time 166485345283 ps
CPU time 95.89 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:14:46 PM PDT 24
Peak memory 201836 kb
Host smart-9cc910da-b4bf-496a-a64a-d271120f4643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635407302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3635407302
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4054926097
Short name T675
Test name
Test status
Simulation time 509049357934 ps
CPU time 201.3 seconds
Started May 16 02:13:05 PM PDT 24
Finished May 16 02:16:27 PM PDT 24
Peak memory 201836 kb
Host smart-7c27665e-cab6-4868-afe3-66b227a271a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054926097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.4054926097
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1334500544
Short name T176
Test name
Test status
Simulation time 331873668005 ps
CPU time 105.97 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:14:56 PM PDT 24
Peak memory 201848 kb
Host smart-8615b232-7c7c-45f8-834c-5d9d7b9b23f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334500544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1334500544
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3989041568
Short name T91
Test name
Test status
Simulation time 322506484917 ps
CPU time 198.25 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:16:28 PM PDT 24
Peak memory 201748 kb
Host smart-060b3af0-425a-4e7c-acaf-adb8db7c5edc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989041568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3989041568
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2279502904
Short name T232
Test name
Test status
Simulation time 173601859247 ps
CPU time 105.18 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:14:55 PM PDT 24
Peak memory 201084 kb
Host smart-1952a869-04a0-4d23-b8dc-90e1068ac524
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279502904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2279502904
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3752966746
Short name T603
Test name
Test status
Simulation time 586917037360 ps
CPU time 1097.14 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:31:28 PM PDT 24
Peak memory 201852 kb
Host smart-494e5e97-838b-4a51-9f4f-03b25cec2712
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752966746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3752966746
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1840641176
Short name T638
Test name
Test status
Simulation time 130043361162 ps
CPU time 673.55 seconds
Started May 16 02:13:07 PM PDT 24
Finished May 16 02:24:23 PM PDT 24
Peak memory 202160 kb
Host smart-823764c5-f1cd-4db9-8bfa-29027d5a3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840641176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1840641176
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3036426317
Short name T438
Test name
Test status
Simulation time 39053206266 ps
CPU time 85.68 seconds
Started May 16 02:13:06 PM PDT 24
Finished May 16 02:14:34 PM PDT 24
Peak memory 201636 kb
Host smart-e74f7cc1-df01-4ab2-905e-59a09f7aedb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036426317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3036426317
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3525801547
Short name T580
Test name
Test status
Simulation time 3886207788 ps
CPU time 1.88 seconds
Started May 16 02:13:08 PM PDT 24
Finished May 16 02:13:12 PM PDT 24
Peak memory 201544 kb
Host smart-f96b68e0-ddea-461e-aa40-71f10905d6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525801547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3525801547
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3584337280
Short name T523
Test name
Test status
Simulation time 6047152616 ps
CPU time 7.43 seconds
Started May 16 02:13:09 PM PDT 24
Finished May 16 02:13:19 PM PDT 24
Peak memory 201644 kb
Host smart-e4252eb3-80d7-4bbc-aa6c-27cae2599a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584337280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3584337280
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1165647646
Short name T331
Test name
Test status
Simulation time 193614785639 ps
CPU time 81.83 seconds
Started May 16 02:13:20 PM PDT 24
Finished May 16 02:14:42 PM PDT 24
Peak memory 201848 kb
Host smart-8602898c-2482-401c-97d2-af74b574d7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165647646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1165647646
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.340138060
Short name T360
Test name
Test status
Simulation time 503275224 ps
CPU time 1.81 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:13:43 PM PDT 24
Peak memory 201536 kb
Host smart-352f6681-ddd0-482f-8caf-8fdf2e2a1ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340138060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.340138060
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4253764432
Short name T278
Test name
Test status
Simulation time 324980275891 ps
CPU time 400.73 seconds
Started May 16 02:13:45 PM PDT 24
Finished May 16 02:20:28 PM PDT 24
Peak memory 201796 kb
Host smart-57697d3f-4a18-45a9-9460-2ddc633db07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253764432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4253764432
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2604749187
Short name T385
Test name
Test status
Simulation time 168161340374 ps
CPU time 393.21 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:20:14 PM PDT 24
Peak memory 201788 kb
Host smart-8c834a37-a042-4917-8964-7ea9bae12387
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604749187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2604749187
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1927494900
Short name T760
Test name
Test status
Simulation time 159050824326 ps
CPU time 385.74 seconds
Started May 16 02:13:18 PM PDT 24
Finished May 16 02:19:44 PM PDT 24
Peak memory 201876 kb
Host smart-2a84dec2-0518-467c-9c7b-10089b865aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927494900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1927494900
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1744874438
Short name T636
Test name
Test status
Simulation time 323004965812 ps
CPU time 784.94 seconds
Started May 16 02:13:22 PM PDT 24
Finished May 16 02:26:27 PM PDT 24
Peak memory 201856 kb
Host smart-12cf20f4-9372-414d-88e7-f1b7690a69e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744874438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1744874438
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3828997972
Short name T322
Test name
Test status
Simulation time 544641613612 ps
CPU time 251.24 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:17:59 PM PDT 24
Peak memory 201900 kb
Host smart-0410e6b2-710b-4e54-9756-e1ba5da71187
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828997972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3828997972
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.544944792
Short name T568
Test name
Test status
Simulation time 206616507594 ps
CPU time 115.52 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:15:43 PM PDT 24
Peak memory 201804 kb
Host smart-bcc8a677-00bf-48c5-96dc-a03a2dbf8b73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544944792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.544944792
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2334458694
Short name T414
Test name
Test status
Simulation time 90397814705 ps
CPU time 274.28 seconds
Started May 16 02:13:47 PM PDT 24
Finished May 16 02:18:23 PM PDT 24
Peak memory 202180 kb
Host smart-544b3f19-f179-48fa-81be-dbebc61cb975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334458694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2334458694
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3347519539
Short name T697
Test name
Test status
Simulation time 28703507437 ps
CPU time 13.89 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:13:55 PM PDT 24
Peak memory 201664 kb
Host smart-c942da89-b805-4b41-b4ab-f79482868f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347519539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3347519539
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2901823454
Short name T450
Test name
Test status
Simulation time 4598453070 ps
CPU time 3.43 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:13:51 PM PDT 24
Peak memory 201680 kb
Host smart-d1cec156-8221-45c6-867a-86cc15a7687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901823454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2901823454
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2904694923
Short name T643
Test name
Test status
Simulation time 6185603896 ps
CPU time 1.73 seconds
Started May 16 02:13:19 PM PDT 24
Finished May 16 02:13:21 PM PDT 24
Peak memory 201608 kb
Host smart-979a2d14-53bd-4ab9-828a-a178b517ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904694923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2904694923
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2820675329
Short name T19
Test name
Test status
Simulation time 43983808257 ps
CPU time 118.09 seconds
Started May 16 02:13:45 PM PDT 24
Finished May 16 02:15:45 PM PDT 24
Peak memory 210488 kb
Host smart-0dc429dd-a64d-488e-9a98-252486203116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820675329 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2820675329
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3190819124
Short name T487
Test name
Test status
Simulation time 284941306 ps
CPU time 1.32 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:13:43 PM PDT 24
Peak memory 201476 kb
Host smart-b08b5994-889d-430e-89ec-bc129a0a9a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190819124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3190819124
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.505947285
Short name T223
Test name
Test status
Simulation time 344135746958 ps
CPU time 431.02 seconds
Started May 16 02:13:45 PM PDT 24
Finished May 16 02:20:58 PM PDT 24
Peak memory 201832 kb
Host smart-58bdb947-6df0-41eb-be51-28e5aa7390e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505947285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.505947285
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3449199347
Short name T274
Test name
Test status
Simulation time 527603188324 ps
CPU time 752.96 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:26:14 PM PDT 24
Peak memory 201812 kb
Host smart-61fea369-c6e0-44fe-a5d8-ac1d305c5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449199347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3449199347
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3999997368
Short name T734
Test name
Test status
Simulation time 164385434251 ps
CPU time 406.35 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:20:34 PM PDT 24
Peak memory 201824 kb
Host smart-118072a8-f693-4e33-8cbf-c4b443abaee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999997368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3999997368
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3845642333
Short name T798
Test name
Test status
Simulation time 330968480259 ps
CPU time 108.46 seconds
Started May 16 02:13:47 PM PDT 24
Finished May 16 02:15:37 PM PDT 24
Peak memory 201812 kb
Host smart-c26b2530-2a95-4545-b8e2-91e943d6dfdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845642333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3845642333
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4105618363
Short name T323
Test name
Test status
Simulation time 493214788805 ps
CPU time 184.96 seconds
Started May 16 02:13:48 PM PDT 24
Finished May 16 02:16:54 PM PDT 24
Peak memory 201716 kb
Host smart-294d6e92-f4e7-459e-b793-4e137930f1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105618363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4105618363
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.434445456
Short name T375
Test name
Test status
Simulation time 166414388127 ps
CPU time 79.56 seconds
Started May 16 02:13:47 PM PDT 24
Finished May 16 02:15:08 PM PDT 24
Peak memory 201820 kb
Host smart-0ad354a7-80d2-48b7-8d7a-ce75b5a88ba9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=434445456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.434445456
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.496802069
Short name T97
Test name
Test status
Simulation time 551445579009 ps
CPU time 297.69 seconds
Started May 16 02:13:41 PM PDT 24
Finished May 16 02:18:40 PM PDT 24
Peak memory 201884 kb
Host smart-f5d7fb95-7dba-4857-8370-bbf2146e3868
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496802069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.496802069
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3794838355
Short name T768
Test name
Test status
Simulation time 199442143792 ps
CPU time 431.51 seconds
Started May 16 02:13:39 PM PDT 24
Finished May 16 02:20:52 PM PDT 24
Peak memory 201728 kb
Host smart-a0144bf7-856f-4542-a7eb-c14d073f3e4f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794838355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3794838355
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3880335268
Short name T670
Test name
Test status
Simulation time 124598911240 ps
CPU time 651.32 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:24:33 PM PDT 24
Peak memory 202160 kb
Host smart-685af26f-690c-4b1f-b378-a68cd3bd2c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880335268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3880335268
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.898593402
Short name T522
Test name
Test status
Simulation time 40256210386 ps
CPU time 20.67 seconds
Started May 16 02:13:44 PM PDT 24
Finished May 16 02:14:06 PM PDT 24
Peak memory 201628 kb
Host smart-faaca4b8-2ce3-4d23-8ad6-5f64fd808f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898593402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.898593402
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4132347530
Short name T797
Test name
Test status
Simulation time 5179621899 ps
CPU time 7.18 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:13:49 PM PDT 24
Peak memory 201668 kb
Host smart-142a3a78-75c7-4d22-aa5d-18ba86b8bf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132347530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4132347530
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3055716871
Short name T647
Test name
Test status
Simulation time 5637355982 ps
CPU time 15.4 seconds
Started May 16 02:13:47 PM PDT 24
Finished May 16 02:14:04 PM PDT 24
Peak memory 201636 kb
Host smart-6bc648c1-7816-4316-929c-27fdbc41b7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055716871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3055716871
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2568743277
Short name T287
Test name
Test status
Simulation time 332247038605 ps
CPU time 201.61 seconds
Started May 16 02:13:41 PM PDT 24
Finished May 16 02:17:04 PM PDT 24
Peak memory 201872 kb
Host smart-a7d113a7-cc3a-4a59-b971-027dad4afc8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568743277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2568743277
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2632345717
Short name T447
Test name
Test status
Simulation time 13866165685 ps
CPU time 59.57 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:14:47 PM PDT 24
Peak memory 210464 kb
Host smart-08d2de95-590c-477c-a02d-817447cb7382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632345717 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2632345717
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2482095397
Short name T543
Test name
Test status
Simulation time 361344713 ps
CPU time 0.8 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:13:55 PM PDT 24
Peak memory 201516 kb
Host smart-f042c638-41b6-4f86-9456-8671fdbe8439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482095397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2482095397
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3672967794
Short name T311
Test name
Test status
Simulation time 480341907211 ps
CPU time 511.67 seconds
Started May 16 02:13:47 PM PDT 24
Finished May 16 02:22:20 PM PDT 24
Peak memory 201848 kb
Host smart-403fc774-ecbb-4079-a1c7-caa18d21b410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672967794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3672967794
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.499259857
Short name T709
Test name
Test status
Simulation time 325192481602 ps
CPU time 710.97 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:25:45 PM PDT 24
Peak memory 201780 kb
Host smart-c0530346-1055-4726-b2a8-a8dca8864b64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499259857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.499259857
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1557549506
Short name T199
Test name
Test status
Simulation time 169085966155 ps
CPU time 101.06 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:15:29 PM PDT 24
Peak memory 201828 kb
Host smart-446195a0-6e80-4036-8934-c2f0939f1a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557549506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1557549506
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1587729177
Short name T635
Test name
Test status
Simulation time 491209135789 ps
CPU time 297.57 seconds
Started May 16 02:13:46 PM PDT 24
Finished May 16 02:18:46 PM PDT 24
Peak memory 201760 kb
Host smart-4d0fc4d3-fd95-4368-9d7e-13ffac5be5f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587729177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1587729177
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3560849873
Short name T618
Test name
Test status
Simulation time 357702952460 ps
CPU time 223.66 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:17:37 PM PDT 24
Peak memory 201832 kb
Host smart-63364a36-258f-4038-9d07-87380fdcaa39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560849873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3560849873
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3311130708
Short name T177
Test name
Test status
Simulation time 588218539318 ps
CPU time 351.59 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:19:45 PM PDT 24
Peak memory 201708 kb
Host smart-148718d1-eb66-449e-9dce-74fd7dc7d850
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311130708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3311130708
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.375331132
Short name T613
Test name
Test status
Simulation time 107468952755 ps
CPU time 617.7 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:24:09 PM PDT 24
Peak memory 202080 kb
Host smart-3b54cb7b-fdb6-4af6-b859-6584109f5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375331132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.375331132
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3111036147
Short name T424
Test name
Test status
Simulation time 23352608880 ps
CPU time 27.19 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:14:21 PM PDT 24
Peak memory 201632 kb
Host smart-d814999b-6f66-4963-b237-632e93a73519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111036147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3111036147
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2663204883
Short name T694
Test name
Test status
Simulation time 3695340200 ps
CPU time 1.79 seconds
Started May 16 02:13:49 PM PDT 24
Finished May 16 02:13:52 PM PDT 24
Peak memory 201544 kb
Host smart-0a1a0547-bd23-47e3-8faa-408ed92cbac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663204883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2663204883
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3327206971
Short name T628
Test name
Test status
Simulation time 5964484081 ps
CPU time 14.67 seconds
Started May 16 02:13:40 PM PDT 24
Finished May 16 02:13:56 PM PDT 24
Peak memory 201676 kb
Host smart-ef06115b-7714-4b5b-8909-eec9759a12e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327206971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3327206971
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.129259396
Short name T263
Test name
Test status
Simulation time 552560412644 ps
CPU time 1381.24 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:36:55 PM PDT 24
Peak memory 201792 kb
Host smart-a47798e2-1650-4961-91b3-dd0849c06e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129259396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
129259396
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1975056918
Short name T729
Test name
Test status
Simulation time 219503252322 ps
CPU time 152.09 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:16:25 PM PDT 24
Peak memory 210340 kb
Host smart-d5ff4c57-8591-4653-beb0-c5a53822d4e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975056918 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1975056918
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3130941166
Short name T451
Test name
Test status
Simulation time 438899258 ps
CPU time 1.65 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:13:55 PM PDT 24
Peak memory 201516 kb
Host smart-e40022ed-9b55-46a9-8d43-46a34663fdf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130941166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3130941166
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3455627630
Short name T654
Test name
Test status
Simulation time 363395386089 ps
CPU time 818.24 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 201832 kb
Host smart-1e084e26-d8a6-4e68-82e3-7daf9c4b0bde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455627630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3455627630
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.896842969
Short name T229
Test name
Test status
Simulation time 488330469628 ps
CPU time 291.08 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:18:42 PM PDT 24
Peak memory 201920 kb
Host smart-4dd1f275-b61f-4129-8ac7-7b1452284007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896842969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.896842969
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3099362928
Short name T769
Test name
Test status
Simulation time 164287672354 ps
CPU time 415.97 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:20:48 PM PDT 24
Peak memory 201816 kb
Host smart-7b96fcbb-bfd4-492c-8e4c-632932bd23c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099362928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3099362928
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.102147175
Short name T160
Test name
Test status
Simulation time 494576252622 ps
CPU time 284.77 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:18:36 PM PDT 24
Peak memory 201816 kb
Host smart-1572c08d-8eca-4036-9ba7-c8890dcaefbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102147175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.102147175
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2245529954
Short name T363
Test name
Test status
Simulation time 327550308930 ps
CPU time 676.1 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:25:09 PM PDT 24
Peak memory 201676 kb
Host smart-f4b97c2c-0353-4c5a-86c2-2aca1dbe4066
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245529954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2245529954
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2541480661
Short name T677
Test name
Test status
Simulation time 192347415653 ps
CPU time 414.11 seconds
Started May 16 02:13:53 PM PDT 24
Finished May 16 02:20:48 PM PDT 24
Peak memory 201800 kb
Host smart-6c6d1386-0e5b-41a5-8929-8d2e82a69c29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541480661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2541480661
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3262857157
Short name T416
Test name
Test status
Simulation time 199336464524 ps
CPU time 468.93 seconds
Started May 16 02:13:50 PM PDT 24
Finished May 16 02:21:39 PM PDT 24
Peak memory 201800 kb
Host smart-9f1a986d-d0aa-49b1-ae70-6f1937a56286
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262857157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3262857157
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.582473283
Short name T351
Test name
Test status
Simulation time 78591251644 ps
CPU time 436.47 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:21:10 PM PDT 24
Peak memory 202096 kb
Host smart-e3baacc2-8423-47cb-9883-e3031f6c15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582473283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.582473283
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3826234469
Short name T558
Test name
Test status
Simulation time 43484736268 ps
CPU time 27.19 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:14:21 PM PDT 24
Peak memory 201676 kb
Host smart-5396c052-f6ad-4e61-a321-8373cbb43633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826234469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3826234469
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2475727639
Short name T584
Test name
Test status
Simulation time 3064517749 ps
CPU time 2.45 seconds
Started May 16 02:13:53 PM PDT 24
Finished May 16 02:13:57 PM PDT 24
Peak memory 201512 kb
Host smart-b786df7e-aac6-4872-a6be-95d669aa4beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475727639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2475727639
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1469038538
Short name T790
Test name
Test status
Simulation time 5832513031 ps
CPU time 13.17 seconds
Started May 16 02:13:51 PM PDT 24
Finished May 16 02:14:06 PM PDT 24
Peak memory 201660 kb
Host smart-17beb75f-183f-4a30-9016-c318ccffee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469038538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1469038538
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4249227043
Short name T796
Test name
Test status
Simulation time 63202790554 ps
CPU time 207.88 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:17:22 PM PDT 24
Peak memory 210508 kb
Host smart-7d188cd8-c5a1-437c-88a5-0a898e746612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249227043 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4249227043
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2586994860
Short name T457
Test name
Test status
Simulation time 317654929 ps
CPU time 0.86 seconds
Started May 16 02:14:03 PM PDT 24
Finished May 16 02:14:05 PM PDT 24
Peak memory 201476 kb
Host smart-03ed2c28-0b60-4334-a727-0cb9398dced1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586994860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2586994860
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.740852338
Short name T556
Test name
Test status
Simulation time 340049761864 ps
CPU time 206.36 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:17:30 PM PDT 24
Peak memory 201892 kb
Host smart-d6772798-e041-4523-8c64-51acb81fc70b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740852338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.740852338
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3646059042
Short name T270
Test name
Test status
Simulation time 574218746631 ps
CPU time 324.35 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:19:28 PM PDT 24
Peak memory 201848 kb
Host smart-f5f31306-239f-4280-b8e3-e3f57f460bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646059042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3646059042
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2184838356
Short name T145
Test name
Test status
Simulation time 324650791481 ps
CPU time 422.81 seconds
Started May 16 02:14:00 PM PDT 24
Finished May 16 02:21:04 PM PDT 24
Peak memory 201804 kb
Host smart-805b7acf-f897-436f-a81c-35bfdcc485ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184838356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2184838356
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3160445377
Short name T391
Test name
Test status
Simulation time 322825985194 ps
CPU time 740.62 seconds
Started May 16 02:14:01 PM PDT 24
Finished May 16 02:26:23 PM PDT 24
Peak memory 201820 kb
Host smart-08a37ac2-fae0-4db4-ad66-19cceadcf0c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160445377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3160445377
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.895047574
Short name T463
Test name
Test status
Simulation time 167674833990 ps
CPU time 185.16 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:17:08 PM PDT 24
Peak memory 201796 kb
Host smart-40c05684-5a9b-4e1b-b854-a06378ddadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895047574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.895047574
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1562048081
Short name T398
Test name
Test status
Simulation time 495946384956 ps
CPU time 304.99 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:19:09 PM PDT 24
Peak memory 201788 kb
Host smart-da8a6a54-a053-4b6d-894b-829f4d3ab8e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562048081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1562048081
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2188356913
Short name T225
Test name
Test status
Simulation time 628586633746 ps
CPU time 740.04 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:26:23 PM PDT 24
Peak memory 201880 kb
Host smart-5337a703-73c0-45b9-bf63-07e1ba228722
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188356913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2188356913
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1747223890
Short name T90
Test name
Test status
Simulation time 206822817746 ps
CPU time 233.87 seconds
Started May 16 02:14:03 PM PDT 24
Finished May 16 02:17:58 PM PDT 24
Peak memory 201824 kb
Host smart-17457ab9-1125-4770-99a1-6e381ee312e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747223890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1747223890
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1590482614
Short name T412
Test name
Test status
Simulation time 63936463740 ps
CPU time 242.13 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:18:06 PM PDT 24
Peak memory 202120 kb
Host smart-49715ed6-bcd9-4b0e-b73d-a6b00c02d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590482614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1590482614
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3459907713
Short name T508
Test name
Test status
Simulation time 39371961958 ps
CPU time 15.46 seconds
Started May 16 02:14:03 PM PDT 24
Finished May 16 02:14:20 PM PDT 24
Peak memory 201640 kb
Host smart-48c5ecda-5e40-4b68-a2c6-15ff748c8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459907713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3459907713
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2401316673
Short name T515
Test name
Test status
Simulation time 4948547381 ps
CPU time 13.05 seconds
Started May 16 02:14:00 PM PDT 24
Finished May 16 02:14:14 PM PDT 24
Peak memory 201660 kb
Host smart-99630555-c213-4701-8ebf-df1a81653e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401316673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2401316673
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1296586568
Short name T407
Test name
Test status
Simulation time 5672116960 ps
CPU time 13.63 seconds
Started May 16 02:13:52 PM PDT 24
Finished May 16 02:14:08 PM PDT 24
Peak memory 201660 kb
Host smart-070a697f-1347-4405-93ad-f2f9bbc92e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296586568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1296586568
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2600194560
Short name T159
Test name
Test status
Simulation time 326668073619 ps
CPU time 264.01 seconds
Started May 16 02:14:00 PM PDT 24
Finished May 16 02:18:25 PM PDT 24
Peak memory 201832 kb
Host smart-39c508ee-2af5-477b-882a-02a7ea7f0a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600194560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2600194560
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2400625105
Short name T38
Test name
Test status
Simulation time 83946835763 ps
CPU time 195.16 seconds
Started May 16 02:14:02 PM PDT 24
Finished May 16 02:17:18 PM PDT 24
Peak memory 218028 kb
Host smart-39a197ee-da4f-48a9-a9a7-56379373b78d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400625105 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2400625105
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1224361654
Short name T405
Test name
Test status
Simulation time 416377016 ps
CPU time 1.53 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:06:00 PM PDT 24
Peak memory 201404 kb
Host smart-f23bf528-2e2b-4e9f-890d-24bbe38742c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224361654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1224361654
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.459471658
Short name T700
Test name
Test status
Simulation time 163082826335 ps
CPU time 369.03 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:11:59 PM PDT 24
Peak memory 201852 kb
Host smart-1d989a60-eb21-4b3f-8935-6625f47909e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459471658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.459471658
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2056002869
Short name T313
Test name
Test status
Simulation time 487382121880 ps
CPU time 918.09 seconds
Started May 16 02:05:44 PM PDT 24
Finished May 16 02:21:06 PM PDT 24
Peak memory 201808 kb
Host smart-923fea66-731e-493e-869b-6794c00d0840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056002869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2056002869
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3725111027
Short name T492
Test name
Test status
Simulation time 491825657279 ps
CPU time 1093.36 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:24:04 PM PDT 24
Peak memory 201844 kb
Host smart-7e862361-26ab-406b-861c-9f17279c2955
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725111027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3725111027
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1085364463
Short name T545
Test name
Test status
Simulation time 325142566322 ps
CPU time 303.43 seconds
Started May 16 02:05:45 PM PDT 24
Finished May 16 02:10:53 PM PDT 24
Peak memory 201780 kb
Host smart-2496bcb4-2ed8-4f3d-87f9-4a787bc5b0a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085364463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1085364463
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3933434990
Short name T640
Test name
Test status
Simulation time 202185196524 ps
CPU time 244 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:09:55 PM PDT 24
Peak memory 201892 kb
Host smart-6fbecc26-5c7e-4237-bf88-3e7fe1b45951
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933434990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3933434990
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1246244741
Short name T417
Test name
Test status
Simulation time 209153423942 ps
CPU time 64.22 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:06:55 PM PDT 24
Peak memory 201852 kb
Host smart-d1fa0feb-02b2-4825-8308-7f803ad5d6e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246244741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1246244741
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2008162712
Short name T698
Test name
Test status
Simulation time 68086037269 ps
CPU time 249.99 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:10:00 PM PDT 24
Peak memory 202172 kb
Host smart-abff1538-8cfb-49e3-99b8-2da8f84ffe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008162712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2008162712
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2881236420
Short name T575
Test name
Test status
Simulation time 44725503157 ps
CPU time 100.11 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:07:31 PM PDT 24
Peak memory 201624 kb
Host smart-38a3dbe5-7917-4367-bd5a-deb521a2b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881236420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2881236420
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2932779504
Short name T370
Test name
Test status
Simulation time 2856951326 ps
CPU time 7.13 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:05:58 PM PDT 24
Peak memory 201520 kb
Host smart-ecc6eee9-72a3-4757-ad1b-fe06b5d1fbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932779504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2932779504
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1858222713
Short name T782
Test name
Test status
Simulation time 5914876870 ps
CPU time 15.82 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:06:06 PM PDT 24
Peak memory 201672 kb
Host smart-169be98e-bb21-4648-9263-70b5f5875dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858222713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1858222713
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.4293411337
Short name T339
Test name
Test status
Simulation time 512884694386 ps
CPU time 179.16 seconds
Started May 16 02:05:47 PM PDT 24
Finished May 16 02:08:50 PM PDT 24
Peak memory 201904 kb
Host smart-4472b04a-aa00-49f5-bb25-b1c92d4d1761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293411337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
4293411337
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4216977341
Short name T253
Test name
Test status
Simulation time 70778445593 ps
CPU time 163.33 seconds
Started May 16 02:05:46 PM PDT 24
Finished May 16 02:08:34 PM PDT 24
Peak memory 201972 kb
Host smart-f8f0d51e-fd78-4dda-8bbe-5c770c26dd82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216977341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4216977341
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.526427675
Short name T666
Test name
Test status
Simulation time 368720132 ps
CPU time 1.48 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:06:03 PM PDT 24
Peak memory 201512 kb
Host smart-18060519-0432-4cc0-b454-be14c4a6bd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526427675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.526427675
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3073444877
Short name T669
Test name
Test status
Simulation time 536308554631 ps
CPU time 233.28 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:09:53 PM PDT 24
Peak memory 201920 kb
Host smart-ebce9048-30ae-4ef0-817a-9dc0a11ed44a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073444877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3073444877
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.927919485
Short name T559
Test name
Test status
Simulation time 338004681240 ps
CPU time 797.18 seconds
Started May 16 02:06:00 PM PDT 24
Finished May 16 02:19:20 PM PDT 24
Peak memory 201852 kb
Host smart-c29f95f4-68c7-4058-b284-5e40ec2727a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927919485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.927919485
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2500855592
Short name T260
Test name
Test status
Simulation time 322019913725 ps
CPU time 206.15 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:09:26 PM PDT 24
Peak memory 201840 kb
Host smart-2032fc5b-5a96-4be1-b3f2-555651cd5511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500855592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2500855592
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3445338769
Short name T496
Test name
Test status
Simulation time 488401938829 ps
CPU time 329.54 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:11:32 PM PDT 24
Peak memory 201796 kb
Host smart-e4bbf5fd-d845-412e-a4db-641874baabc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445338769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3445338769
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1190520772
Short name T684
Test name
Test status
Simulation time 323393731490 ps
CPU time 197.26 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:09:19 PM PDT 24
Peak memory 201796 kb
Host smart-3efdc83e-b67e-4c85-95bd-a98ab80aa957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190520772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1190520772
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.185200815
Short name T464
Test name
Test status
Simulation time 326160467910 ps
CPU time 365.17 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:12:06 PM PDT 24
Peak memory 201800 kb
Host smart-e5ec6d5f-9851-46cd-9748-5985350adbb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=185200815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.185200815
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3954843759
Short name T284
Test name
Test status
Simulation time 427377324320 ps
CPU time 55.03 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:06:55 PM PDT 24
Peak memory 201856 kb
Host smart-477ff126-14a3-4ef2-9ead-6ca9741b7695
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954843759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3954843759
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1049995116
Short name T413
Test name
Test status
Simulation time 405071543114 ps
CPU time 229.63 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:09:52 PM PDT 24
Peak memory 201772 kb
Host smart-a7b23e1f-4a75-4eb9-be9c-0270f6c74542
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049995116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1049995116
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.485728961
Short name T516
Test name
Test status
Simulation time 132999525796 ps
CPU time 478.38 seconds
Started May 16 02:06:00 PM PDT 24
Finished May 16 02:14:01 PM PDT 24
Peak memory 202160 kb
Host smart-f9c198f5-909e-4fcd-a0fa-f45066653926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485728961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.485728961
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4182979321
Short name T752
Test name
Test status
Simulation time 44433111399 ps
CPU time 106.69 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:07:45 PM PDT 24
Peak memory 201636 kb
Host smart-3a0f00e5-3291-4988-a702-d8448ee77060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182979321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4182979321
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.771452274
Short name T5
Test name
Test status
Simulation time 3281970807 ps
CPU time 2.68 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:06:03 PM PDT 24
Peak memory 201576 kb
Host smart-dba6b361-8b9f-4486-8c60-3ae29210a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771452274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.771452274
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2027456603
Short name T761
Test name
Test status
Simulation time 5823103499 ps
CPU time 13.83 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:06:14 PM PDT 24
Peak memory 201672 kb
Host smart-1ec87da1-4548-4c1c-9166-0e735215ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027456603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2027456603
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3848558543
Short name T561
Test name
Test status
Simulation time 175415893764 ps
CPU time 425.62 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:13:05 PM PDT 24
Peak memory 201844 kb
Host smart-11d45da5-ed84-4421-b386-ea23f22d992d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848558543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3848558543
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2882076447
Short name T766
Test name
Test status
Simulation time 346853972341 ps
CPU time 285.74 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:10:48 PM PDT 24
Peak memory 210424 kb
Host smart-657f63d7-a239-4021-9e21-be573a23e5c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882076447 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2882076447
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2007495641
Short name T605
Test name
Test status
Simulation time 323874782 ps
CPU time 1.39 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:06:03 PM PDT 24
Peak memory 201508 kb
Host smart-b75fbd3e-9725-4aec-b5de-030d702ff027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007495641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2007495641
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3327410602
Short name T222
Test name
Test status
Simulation time 341027567315 ps
CPU time 220.64 seconds
Started May 16 02:06:00 PM PDT 24
Finished May 16 02:09:44 PM PDT 24
Peak memory 201932 kb
Host smart-3ef0fac3-fda3-4fec-8388-fe918f4fd3aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327410602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3327410602
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3285770840
Short name T778
Test name
Test status
Simulation time 165420262902 ps
CPU time 99.86 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:07:39 PM PDT 24
Peak memory 201780 kb
Host smart-599744ff-ce91-4972-a103-631328edd034
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285770840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3285770840
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.602833793
Short name T217
Test name
Test status
Simulation time 498348815406 ps
CPU time 317.89 seconds
Started May 16 02:06:00 PM PDT 24
Finished May 16 02:11:21 PM PDT 24
Peak memory 201804 kb
Host smart-0c170c88-8692-4292-889d-c6ba66a9d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602833793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.602833793
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4199143187
Short name T525
Test name
Test status
Simulation time 159752054179 ps
CPU time 184.37 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:09:06 PM PDT 24
Peak memory 201896 kb
Host smart-daf4c50c-0fad-4ff7-9f67-dc0056910835
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199143187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4199143187
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1398478979
Short name T527
Test name
Test status
Simulation time 332371380825 ps
CPU time 403.45 seconds
Started May 16 02:06:00 PM PDT 24
Finished May 16 02:12:46 PM PDT 24
Peak memory 201940 kb
Host smart-421ec8be-abc1-4541-9284-ef45b32a38e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398478979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1398478979
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2556747277
Short name T604
Test name
Test status
Simulation time 595806435027 ps
CPU time 723.48 seconds
Started May 16 02:05:55 PM PDT 24
Finished May 16 02:18:00 PM PDT 24
Peak memory 201812 kb
Host smart-dbba6478-bb10-4511-952e-3e99d788294e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556747277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2556747277
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2716176885
Short name T191
Test name
Test status
Simulation time 77945516360 ps
CPU time 323.85 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:11:25 PM PDT 24
Peak memory 202216 kb
Host smart-66b7e3cc-d85f-4db0-b601-45138b4153b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716176885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2716176885
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3074056317
Short name T724
Test name
Test status
Simulation time 39119832973 ps
CPU time 24.63 seconds
Started May 16 02:05:57 PM PDT 24
Finished May 16 02:06:24 PM PDT 24
Peak memory 201636 kb
Host smart-ec8a3ceb-b1e1-4c2d-b8db-80dfadea77a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074056317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3074056317
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3914790229
Short name T743
Test name
Test status
Simulation time 4848015618 ps
CPU time 6.55 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:06:08 PM PDT 24
Peak memory 201620 kb
Host smart-695481e3-4cdb-493a-bad6-bb3146562c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914790229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3914790229
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2415998403
Short name T685
Test name
Test status
Simulation time 5839094524 ps
CPU time 4.04 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:06:06 PM PDT 24
Peak memory 201612 kb
Host smart-6a814042-ac13-41e5-8015-7a2a08251505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415998403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2415998403
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2521999579
Short name T321
Test name
Test status
Simulation time 345425487539 ps
CPU time 406.38 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:12:48 PM PDT 24
Peak memory 218312 kb
Host smart-9534a126-9957-45de-8a9b-092dba61f345
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521999579 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2521999579
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3613996994
Short name T518
Test name
Test status
Simulation time 412079534 ps
CPU time 1.57 seconds
Started May 16 02:06:09 PM PDT 24
Finished May 16 02:06:14 PM PDT 24
Peak memory 201512 kb
Host smart-953453fc-1ca4-4cba-96fe-ecb86ba42f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613996994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3613996994
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1226629589
Short name T307
Test name
Test status
Simulation time 168920114667 ps
CPU time 104.88 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:07:47 PM PDT 24
Peak memory 201896 kb
Host smart-e4dbeee8-ba99-4a13-9250-5db3b71bae15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226629589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1226629589
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.835165443
Short name T12
Test name
Test status
Simulation time 162396187391 ps
CPU time 295.26 seconds
Started May 16 02:06:00 PM PDT 24
Finished May 16 02:10:58 PM PDT 24
Peak memory 201820 kb
Host smart-dda908e0-6cdd-4b94-9346-91bb2fec062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835165443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.835165443
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1390960520
Short name T138
Test name
Test status
Simulation time 493601040063 ps
CPU time 1160.65 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:25:18 PM PDT 24
Peak memory 201820 kb
Host smart-a4597789-3f95-4152-802a-37f62052eb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390960520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1390960520
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.13995565
Short name T386
Test name
Test status
Simulation time 322095138313 ps
CPU time 326.74 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:11:25 PM PDT 24
Peak memory 201696 kb
Host smart-41109fc3-296a-4552-bb87-22af825d4482
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_
fixed.13995565
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2819309728
Short name T611
Test name
Test status
Simulation time 329125238020 ps
CPU time 46.95 seconds
Started May 16 02:05:59 PM PDT 24
Finished May 16 02:06:49 PM PDT 24
Peak memory 201920 kb
Host smart-1689632e-0b2a-46c0-a20a-fc6b87b46ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819309728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2819309728
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4120103203
Short name T753
Test name
Test status
Simulation time 333733816070 ps
CPU time 218.89 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:09:36 PM PDT 24
Peak memory 201824 kb
Host smart-91d96003-3832-40e1-b937-afc25f73114a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120103203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.4120103203
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3522225266
Short name T437
Test name
Test status
Simulation time 589151093180 ps
CPU time 1413.28 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:29:32 PM PDT 24
Peak memory 201732 kb
Host smart-93a81d6b-5e01-4b6b-8751-0f615b0f190a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522225266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3522225266
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3283422681
Short name T723
Test name
Test status
Simulation time 45442379038 ps
CPU time 17.72 seconds
Started May 16 02:05:56 PM PDT 24
Finished May 16 02:06:15 PM PDT 24
Peak memory 201600 kb
Host smart-3e9abc59-e80b-49fb-88a8-e501c1f16aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283422681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3283422681
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2729599381
Short name T459
Test name
Test status
Simulation time 2921116882 ps
CPU time 7.6 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:06:08 PM PDT 24
Peak memory 201588 kb
Host smart-e7115cfd-223a-4655-812f-3e53e7d9071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729599381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2729599381
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4174624728
Short name T155
Test name
Test status
Simulation time 5609569742 ps
CPU time 1.71 seconds
Started May 16 02:05:58 PM PDT 24
Finished May 16 02:06:03 PM PDT 24
Peak memory 201672 kb
Host smart-f01b868b-4694-44ab-9bdd-03b4ce575638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174624728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4174624728
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2317197290
Short name T439
Test name
Test status
Simulation time 372862146908 ps
CPU time 250.83 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:10:20 PM PDT 24
Peak memory 201828 kb
Host smart-4d516ca5-4fe1-4548-b632-735502b5901e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317197290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2317197290
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1575898629
Short name T262
Test name
Test status
Simulation time 172347755076 ps
CPU time 183.29 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:09:17 PM PDT 24
Peak memory 210152 kb
Host smart-9dc014aa-6179-43d2-9bc3-8aac56c7c8d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575898629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1575898629
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2844208917
Short name T517
Test name
Test status
Simulation time 316974725 ps
CPU time 1.37 seconds
Started May 16 02:06:08 PM PDT 24
Finished May 16 02:06:13 PM PDT 24
Peak memory 201536 kb
Host smart-875feb0a-174f-4460-8a98-ac9d45bafc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844208917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2844208917
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1098926049
Short name T589
Test name
Test status
Simulation time 163108345904 ps
CPU time 96.47 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:07:51 PM PDT 24
Peak memory 201764 kb
Host smart-bcafbb8d-79ba-4403-a932-39b93155709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098926049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1098926049
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.722960228
Short name T582
Test name
Test status
Simulation time 492748684397 ps
CPU time 628.36 seconds
Started May 16 02:06:09 PM PDT 24
Finished May 16 02:16:41 PM PDT 24
Peak memory 201816 kb
Host smart-853e4279-1d65-41dd-9d91-5d9d4cde8946
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=722960228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.722960228
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1296710401
Short name T301
Test name
Test status
Simulation time 334503429326 ps
CPU time 206.61 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:09:41 PM PDT 24
Peak memory 201808 kb
Host smart-847d3dd3-bc1c-41c0-a65d-7a132718953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296710401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1296710401
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4014030146
Short name T396
Test name
Test status
Simulation time 168381356242 ps
CPU time 392.42 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:12:46 PM PDT 24
Peak memory 201832 kb
Host smart-be07d95b-3bb2-4e15-a9ab-9155f6f2a2aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014030146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4014030146
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1208749946
Short name T242
Test name
Test status
Simulation time 334274886870 ps
CPU time 201.9 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:09:32 PM PDT 24
Peak memory 201852 kb
Host smart-45901cbe-7e73-4847-a5ba-e885e0764dea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208749946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1208749946
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.277571211
Short name T150
Test name
Test status
Simulation time 401517406034 ps
CPU time 66.47 seconds
Started May 16 02:06:06 PM PDT 24
Finished May 16 02:07:16 PM PDT 24
Peak memory 201776 kb
Host smart-4bc74f2e-f22e-4096-8f3d-0eb8efc09b1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277571211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.277571211
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4166886926
Short name T755
Test name
Test status
Simulation time 72200219779 ps
CPU time 294.98 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:11:05 PM PDT 24
Peak memory 202148 kb
Host smart-9e023587-eafc-42f6-9c6d-16fe9e06822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166886926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4166886926
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3628645220
Short name T531
Test name
Test status
Simulation time 38592860312 ps
CPU time 81.73 seconds
Started May 16 02:06:07 PM PDT 24
Finished May 16 02:07:32 PM PDT 24
Peak memory 201624 kb
Host smart-900e5e6e-23fe-4c40-b80b-3db5a5066a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628645220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3628645220
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2637715741
Short name T442
Test name
Test status
Simulation time 5156632947 ps
CPU time 11.4 seconds
Started May 16 02:06:11 PM PDT 24
Finished May 16 02:06:25 PM PDT 24
Peak memory 201516 kb
Host smart-83ecf2fc-e0ae-4c53-b2b7-435ba9fc6408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637715741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2637715741
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1739336324
Short name T501
Test name
Test status
Simulation time 5499979931 ps
CPU time 3.94 seconds
Started May 16 02:06:08 PM PDT 24
Finished May 16 02:06:16 PM PDT 24
Peak memory 201620 kb
Host smart-989f7000-dc66-41bc-a646-89301f175aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739336324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1739336324
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1900058092
Short name T617
Test name
Test status
Simulation time 325415753792 ps
CPU time 48.34 seconds
Started May 16 02:06:08 PM PDT 24
Finished May 16 02:07:00 PM PDT 24
Peak memory 201884 kb
Host smart-36d185a2-9b0e-466b-8d40-de3f4ab3c782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900058092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1900058092
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3558210916
Short name T210
Test name
Test status
Simulation time 34590856441 ps
CPU time 98.5 seconds
Started May 16 02:06:10 PM PDT 24
Finished May 16 02:07:53 PM PDT 24
Peak memory 210464 kb
Host smart-d10640fa-ede4-4c2d-a2e4-44d3b2debe3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558210916 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3558210916
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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