Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6585	1			T2	10		T7	43		T11	54
testmodes[AdcCtrlTestmodeNormal]	5323	1			T2	10		T3	2		T4	2
testmodes[AdcCtrlTestmodeLowpower]	5599	1			T1	12		T3	1		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3502	1			T2	4		T7	18		T11	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1664	1			T2	5		T7	20		T11	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1294	1			T7	5		T11	19		T15	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1697	1			T2	6		T7	20		T11	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1956	1			T2	4		T4	1		T7	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1346	1			T3	1		T7	4		T11	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1272	1			T7	5		T11	17		T15	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1376	1			T3	1		T7	4		T11	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2702	1			T1	11		T5	1		T7	15