Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22250

1

T1

12

T2

20

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3730

1

T3

38

T7

2

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19808

1

T1

12

T2

20

T3

40

auto[1]

6172

1

T3

24

T4

2

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T243	15		-	-		-	-
values[0]	50	1			T161	1		T244	16		T245	18
values[1]	689	1			T5	22		T12	2		T36	27
values[2]	874	1			T3	26		T5	23		T13	3
values[3]	667	1			T3	14		T29	7		T128	1
values[4]	3091	1			T4	2		T6	9		T10	15
values[5]	677	1			T7	5		T28	37		T129	18
values[6]	560	1			T128	1		T137	4		T134	22
values[7]	949	1			T7	2		T29	19		T137	13
values[8]	737	1			T7	4		T16	1		T138	6
values[9]	1113	1			T3	24		T9	2		T136	25
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1044	1			T5	22		T12	2		T36	27
values[1]	797	1			T3	40		T5	23		T13	3
values[2]	591	1			T29	7		T130	5		T131	20
values[3]	3034	1			T4	2		T6	9		T10	15
values[4]	697	1			T7	5		T137	4		T38	2
values[5]	781	1			T7	2		T128	1		T139	15
values[6]	773	1			T29	19		T137	13		T246	1
values[7]	633	1			T7	4		T16	1		T137	4
values[8]	888	1			T3	24		T9	2		T136	11
values[9]	183	1			T136	14		T140	13		T247	25
minimum	16559	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	11		T12	1		T36	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T12	1		T37	1		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	14		T5	14		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	6		T13	3		T248	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	6		T229	3		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	1		T131	20		T132	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T4	2		T6	1		T10	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	1		T129	10		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	3		T137	1		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T38	2		T40	7		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T139	4		T134	11		T213	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	2		T128	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T246	1		T220	12		T215	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T29	17		T137	1		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	2		T137	1		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T138	6		T131	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	1		T136	1		T129	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	12		T9	1		T247	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T247	14		T243	1		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T136	1		T140	1		T251	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16428	1			T1	12		T2	20		T7	99
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T36	14		T252	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T37	1		T148	11		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	12		T5	9		T220	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	8		T248	12		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	1		T229	1		T254	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T130	4		T189	1		T255	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T6	8		T28	20		T31	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T129	8		T130	9		T132	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	2		T137	3		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	7		T133	18		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T139	11		T134	11		T213	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	1		T189	1		T214	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T220	17		T215	16		T256	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T29	2		T137	12		T140	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	2		T137	3		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T257	13		T258	8		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T136	10		T129	14		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	12		T247	11		T171	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T247	11		T243	14		T250	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T136	13		T140	12		T259	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T245	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T161	1		T244	1		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	11		T12	1		T36	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	1		T37	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	14		T5	14		T131	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	3		T248	14		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T29	6		T128	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	6		T131	20		T132	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T4	2		T6	1		T10	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T24	1		T130	2		T132	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	3		T28	17		T139	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T129	10		T38	2		T40	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T137	1		T134	11		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T128	1		T214	1		T261	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T246	1		T139	4		T215	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T7	2		T29	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	2		T220	12		T189	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	1		T138	6		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T9	1		T136	1		T129	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T3	12		T9	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T243	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T245	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T244	15		T260	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	11		T36	14		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	1		T148	11		T253	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	12		T5	9		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T248	12		T160	2		T142	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	1		T254	18		T262	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	8		T255	22		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T6	8		T31	7		T71	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T130	13		T132	6		T187	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	2		T28	20		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T129	8		T40	7		T133	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T137	3		T134	11		T214	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T214	15		T261	7		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T139	11		T215	16		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	2		T137	12		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	2		T220	17		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T263	6		T257	13		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T136	10		T129	14		T137	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	12		T136	13		T140	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	12		T12	1		T36	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T12	1		T37	2		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	13		T5	10		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	9		T13	2		T248	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	2		T229	3		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	5		T131	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T4	2		T6	9		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T24	1		T129	9		T130	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	3		T137	4		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	2		T40	10		T133	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T139	12		T134	13		T213	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	2		T128	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T246	1		T220	18		T215	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	3		T137	13		T140	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	4		T137	4		T189	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T16	1		T138	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T9	1		T136	11		T129	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	13		T9	1		T247	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T247	12		T243	15		T250	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T136	14		T140	13		T251	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16559	1			T1	12		T2	20		T7	104
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	10		T36	10		T252	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T253	8		T142	15		T264	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	13		T5	13		T131	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T13	1		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T29	5		T229	1		T254	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T131	19		T132	7		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T10	14		T25	18		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T129	9		T132	2		T187	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	2		T42	2		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	4		T133	14		T256	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T139	3		T134	9		T213	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	1		T150	2		T263	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T220	11		T215	18		T256	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	16		T265	11		T263	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T197	11		T153	13		T266	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	5		T131	12		T257	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T129	13		T138	17		T256	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	11		T247	10		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T247	13		T267	2		T268	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T251	12		T21	11		T269	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T243	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T245	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T161	1		T244	16		T260	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	12		T12	1		T36	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T37	2		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	13		T5	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	2		T248	13		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T29	2		T128	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	9		T131	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T4	2		T6	9		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T24	1		T130	15		T132	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	3		T28	21		T139	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	9		T38	2		T40	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T137	4		T134	13		T214	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	1		T214	16		T261	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T246	1		T139	12		T215	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	2		T29	3		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	4		T220	18		T189	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	1		T138	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T9	1		T136	11		T129	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	13		T9	1		T136	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T245	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	10		T36	10		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T253	8		T257	10		T180	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	13		T5	13		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T248	13		T142	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	5		T254	18		T262	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	5		T131	19		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T10	14		T25	18		T31	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T132	2		T187	2		T189	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	2		T28	16		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T129	9		T40	4		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T134	9		T143	2		T270	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T261	2		T266	9		T271	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T139	3		T215	18		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T29	16		T42	1		T265	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T220	11		T197	11		T257	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T138	5		T131	12		T263	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T129	13		T138	17		T247	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	11		T247	10		T142	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22040

1

T1

12

T2

20

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3940

1

T3

24

T5

22

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19721

1

T1

12

T2

20

T5

22

auto[1]

6259

1

T3

64

T4

2

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	150	1			T9	1		T150	14		T182	1
values[1]	816	1			T3	14		T5	23		T136	14
values[2]	774	1			T7	4		T28	37		T16	5
values[3]	902	1			T3	24		T39	2		T247	47
values[4]	814	1			T3	26		T129	18		T42	3
values[5]	600	1			T9	1		T31	17		T128	1
values[6]	819	1			T7	5		T12	1		T136	11
values[7]	598	1			T5	22		T12	1		T37	2
values[8]	2968	1			T4	2		T6	9		T10	15
values[9]	981	1			T7	2		T13	3		T24	1
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T3	14		T5	23		T28	37
values[1]	903	1			T7	4		T16	4		T130	15
values[2]	798	1			T3	24		T129	18		T39	2
values[3]	726	1			T3	26		T31	17		T128	1
values[4]	709	1			T9	1		T12	1		T138	6
values[5]	779	1			T7	5		T136	11		T138	18
values[6]	2777	1			T4	2		T5	22		T6	9
values[7]	768	1			T29	19		T137	4		T131	13
values[8]	936	1			T7	2		T9	1		T13	3
values[9]	48	1			T142	15		T154	8		T34	1
minimum	16761	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	6		T5	14		T28	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T136	1		T16	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T16	3		T130	2		T131	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	2		T131	20		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	2		T247	25		T272	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	12		T129	10		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	14		T31	10		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T265	12		T248	14		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	1		T138	6		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	1		T220	12		T247	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T136	1		T138	18		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	3		T148	1		T197	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T4	2		T6	1		T10	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	11		T37	1		T133	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T137	1		T189	5		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	17		T131	13		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	3		T24	1		T36	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T7	2		T9	1		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T273	8		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T142	15		T154	8		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16493	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T180	10		T144	17		T274	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	8		T5	9		T28	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T136	13		T137	3		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	1		T130	13		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	2		T140	14		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T247	22		T272	16		T32	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	12		T129	8		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	12		T31	7		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T265	11		T248	12		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T172	10		T174	11		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T220	9		T247	11		T275	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	10		T220	17		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	2		T148	11		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T6	8		T71	11		T73	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	11		T37	1		T133	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T137	3		T189	1		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T29	2		T187	6		T139	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T36	14		T129	14		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	1		T40	7		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T276	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T277	11		T96	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T150	3		T182	1		T278	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T9	1		T279	7		T154	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	6		T5	14		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T136	1		T137	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T28	17		T16	3		T130	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	2		T16	1		T131	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T39	2		T247	25		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	12		T150	13		T252	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	14		T42	2		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T129	10		T265	12		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T31	10		T128	1		T180	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T220	12		T142	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	1		T136	1		T138	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	3		T148	1		T197	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	1		T138	18		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	11		T37	1		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T4	2		T6	1		T10	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T29	17		T131	13		T187	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	3		T24	1		T36	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T7	2		T29	6		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T150	11		T280	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T279	2		T105	4		T90	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	8		T5	9		T137	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T136	13		T137	3		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T28	20		T16	1		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	2		T140	14		T242	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T247	22		T272	16		T264	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	12		T150	11		T252	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	12		T42	1		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	8		T265	11		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T31	7		T174	11		T281	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T220	9		T142	16		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T136	10		T220	17		T272	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	2		T148	11		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T189	1		T262	4		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	11		T37	1		T133	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T6	8		T71	11		T73	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	2		T187	6		T139	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	14		T129	14		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	1		T40	7		T160	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2