Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19894

1

T1

12

T2

20

T3

50

auto[ADC_CTRL_FILTER_COND_OUT]

6086

1

T3

14

T4

2

T5

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19851

1

T1

12

T2

20

T3

38

auto[1]

6129

1

T3

26

T4

2

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	202	1			T7	2		T129	28		T137	4
values[0]	24	1			T309	17		T310	7		-	-
values[1]	865	1			T3	14		T9	1		T128	1
values[2]	701	1			T31	17		T36	27		T131	15
values[3]	852	1			T28	37		T29	19		T37	2
values[4]	591	1			T13	3		T136	14		T16	4
values[5]	509	1			T5	22		T12	1		T137	4
values[6]	685	1			T7	5		T136	11		T128	1
values[7]	913	1			T12	1		T130	10		T38	2
values[8]	776	1			T3	24		T7	4		T9	1
values[9]	3304	1			T3	26		T4	2		T5	23
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	805	1			T3	14		T9	1		T36	27
values[1]	2885	1			T4	2		T6	9		T10	15
values[2]	806	1			T13	3		T28	37		T29	19
values[3]	623	1			T138	6		T42	3		T197	22
values[4]	524	1			T5	22		T12	1		T137	17
values[5]	738	1			T7	5		T136	11		T128	1
values[6]	905	1			T9	1		T12	1		T38	2
values[7]	783	1			T3	24		T7	4		T29	7
values[8]	986	1			T3	26		T5	23		T7	2
values[9]	101	1			T249	1		T306	6		T293	3
minimum	16824	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	1		T128	1		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	6		T36	13		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T131	15		T229	3		T252	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1566	1			T4	2		T6	1		T10	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	3		T28	17		T29	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	2		T16	3		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T42	2		T214	1		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	6		T197	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	11		T12	1		T272	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T137	2		T148	1		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T187	3		T253	9		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	3		T136	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T140	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T9	1		T38	2		T220	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	12		T7	2		T29	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	13		T265	12		T254	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	14		T137	1		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	14		T7	2		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T306	6		T293	2		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T249	1		T308	9		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16497	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T255	1		T343	1		T213	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	14		T189	1		T133	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	8		T36	14		T40	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T229	1		T252	12		T256	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	990	1			T6	8		T31	7		T71	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	20		T29	2		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T169	12		T189	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	1		T214	10		T255	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T197	10		T160	11		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	11		T272	1		T279	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T137	15		T148	11		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T187	6		T253	10		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	2		T136	10		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T140	9		T214	15		T171	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T220	17		T135	9		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	12		T7	2		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	12		T265	11		T254	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	12		T137	3		T132	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	9		T129	22		T130	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T293	1		T175	2		T314	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T308	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T255	5		T213	29		T344	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T137	1		T132	8		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T7	2		T129	14		T193	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T309	13		T310	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T128	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	6		T39	2		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T131	15		T252	7		T256	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T31	10		T36	13		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T28	17		T29	17		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T37	2		T169	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	3		T136	1		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	3		T197	12		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	11		T12	1		T42	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	1		T138	6		T258	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T187	3		T253	9		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	3		T136	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T130	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T38	2		T220	12		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	12		T7	2		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T139	13		T247	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T3	14		T132	3		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1671	1			T4	2		T5	14		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T137	3		T161	11		T234	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T129	14		T345	13		T337	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T309	4		T310	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	14		T189	1		T133	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	8		T40	7		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T252	12		T256	10		T262	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T31	7		T36	14		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T28	20		T29	2		T220	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T169	12		T140	12		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	13		T42	1		T214	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T197	10		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T5	11		T42	1		T285	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T137	3		T258	8		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T187	6		T253	10		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	2		T136	10		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T130	9		T214	15		T160	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T220	17		T135	9		T263	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	12		T7	2		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	12		T247	11		T254	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	12		T132	6		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1067	1			T5	9		T6	8		T71	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	1		T128	1		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	9		T36	17		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	1		T229	3		T252	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1335	1			T4	2		T6	9		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	2		T28	21		T29	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T37	1		T16	3		T169	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	2		T214	11		T255	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	1		T197	11		T160	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	12		T12	1		T272	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	17		T148	12		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T187	7		T253	11		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	3		T136	11		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T140	10		T214	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T9	1		T38	2		T220	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	13		T7	4		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T139	13		T265	12		T254	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T3	13		T137	4		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	10		T7	2		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T306	1		T293	3		T175	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T249	1		T308	11		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16594	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T255	6		T343	1		T213	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T131	19		T133	14		T256	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	5		T36	10		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	14		T229	1		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1221	1			T10	14		T25	18		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	1		T28	16		T29	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	1		T16	1		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T42	1		T285	6		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T138	5		T197	11		T270	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	10		T212	10		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	9		T258	8		T290	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T187	2		T253	8		T293	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	2		T138	17		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T254	5		T143	30		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T220	11		T247	14		T272	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	11		T29	5		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T139	12		T265	11		T254	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	13		T132	9		T264	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	13		T129	22		T139	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T306	5		T314	11		T346	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T308	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T144	5		T172	10		T221	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T213	29		T347	18		T344	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T137	4		T132	1		T161	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T7	2		T129	15		T193	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T309	5		T310	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T128	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	9		T39	2		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T131	1		T252	13		T256	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	11		T36	17		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	21		T29	3		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T37	1		T169	13		T140	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T136	14		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	3		T197	11		T160	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	12		T12	1		T42	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T137	4		T138	1		T258	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T187	7		T253	11		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	3		T136	11		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T130	10		T214	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T38	2		T220	18		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	13		T7	4		T29	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T139	13		T247	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T3	13		T132	7		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1422	1			T4	2		T5	10		T6	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T132	7		T306	5		T234	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T129	13		T348	12		T308	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T309	12		T310	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T131	19		T133	14		T256	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	5		T40	4		T142	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	14		T252	6		T256	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	6		T36	10		T165	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T28	16		T29	16		T220	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	1		T215	9		T284	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T13	1		T42	2		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	1		T197	11		T181	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T5	10		T42	1		T285	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T138	5		T258	8		T222	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T187	2		T253	8		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	2		T138	17		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T254	5		T143	28		T293	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T220	11		T263	5		T272	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	11		T29	5		T275	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	12		T247	14		T254	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	13		T132	2		T264	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1316	1			T5	13		T10	14		T25	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2