Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22262

1

T1

12

T2

20

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3718

1

T3

26

T7

6

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19526

1

T1

12

T2

20

T5

45

auto[1]

6454

1

T3

64

T4

2

T6

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	397	1			T7	2		T11	3		T15	2
values[0]	45	1			T270	13		T331	18		T349	14
values[1]	872	1			T38	2		T187	9		T220	21
values[2]	2953	1			T4	2		T6	9		T10	15
values[3]	748	1			T5	23		T12	1		T128	1
values[4]	822	1			T7	2		T12	1		T13	3
values[5]	751	1			T9	1		T29	7		T131	13
values[6]	679	1			T136	14		T130	5		T138	6
values[7]	683	1			T29	19		T36	27		T136	11
values[8]	689	1			T3	14		T5	22		T7	4
values[9]	1165	1			T3	50		T7	5		T9	1
minimum	16176	1			T1	12		T2	20		T7	102

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1152	1			T24	1		T28	37		T31	17
values[1]	2945	1			T4	2		T5	23		T6	9
values[2]	783	1			T13	3		T128	1		T129	46
values[3]	709	1			T7	2		T12	1		T29	7
values[4]	710	1			T9	1		T138	6		T131	13
values[5]	727	1			T29	19		T136	14		T16	4
values[6]	675	1			T36	27		T136	11		T169	13
values[7]	773	1			T3	14		T5	22		T7	4
values[8]	785	1			T3	50		T131	35		T289	1
values[9]	150	1			T7	5		T37	2		T142	8
minimum	16571	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T24	1		T31	10		T187	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T28	17		T220	12		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T4	2		T5	14		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T16	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	3		T128	1		T129	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T137	3		T246	1		T132	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T29	6		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	2		T128	1		T132	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	1		T160	1		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T138	6		T131	13		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T29	17		T136	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T130	1		T247	14		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T136	1		T169	1		T263	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T36	13		T139	13		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	6		T5	11		T138	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	2		T9	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	12		T131	35		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	14		T289	1		T248	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T7	3		T142	1		T173	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T37	1		T204	1		T350	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T270	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T31	7		T187	6		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T28	20		T220	9		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T5	9		T6	8		T71	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	11		T140	14		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T129	22		T130	9		T214	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T137	18		T197	10		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	1		T40	7		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	6		T214	15		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T160	2		T255	10		T285	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T220	17		T265	11		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	2		T136	13		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	4		T247	11		T257	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	10		T169	12		T263	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	14		T139	12		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	8		T5	11		T140	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	2		T140	12		T247	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	12		T160	14		T171	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	12		T248	12		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T7	2		T142	7		T173	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T37	1		T259	9		T307	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T7	2		T11	3		T15	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T22	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T331	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T270	13		T349	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T187	3		T189	2		T133	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T38	2		T220	12		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T4	2		T6	1		T10	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	17		T16	1		T139	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	14		T128	1		T129	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T137	2		T197	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T13	3		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	2		T128	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T29	6		T40	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T131	13		T132	3		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T136	1		T189	5		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	1		T138	6		T247	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T29	17		T136	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	13		T139	13		T150	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	6		T5	11		T138	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	2		T140	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T3	12		T7	3		T131	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T3	14		T9	1		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16045	1			T1	12		T2	20		T7	97
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T22	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T331	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T187	6		T189	1		T133	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T220	9		T42	1		T189	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T6	8		T31	7		T71	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T28	20		T139	11		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	9		T129	8		T214	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T137	6		T197	10		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T130	9		T42	1		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	12		T214	15		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	1		T40	7		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T132	6		T220	17		T265	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	13		T189	1		T255	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	4		T247	11		T292	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	2		T136	10		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T36	14		T139	12		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	8		T5	11		T160	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	2		T140	12		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T3	12		T7	2		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	12		T37	1		T247	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T24	1		T31	11		T187	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T28	21		T220	10		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T4	2		T5	10		T6	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T16	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	2		T128	1		T129	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T137	21		T246	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T29	2		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	2		T128	1		T132	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	1		T160	3		T255	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T138	1		T131	1		T220	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	3		T136	14		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T130	5		T247	12		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	11		T169	13		T263	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T36	17		T139	13		T135	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	9		T5	12		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	4		T9	1		T140	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	13		T131	2		T160	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	13		T289	1		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T7	3		T142	8		T173	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T37	2		T204	1		T350	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T31	6		T187	2		T133	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T28	16		T220	11		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T5	13		T10	14		T25	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T139	3		T247	14		T165	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T129	22		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	7		T197	11		T279	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	5		T40	4		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	2		T143	10		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T285	6		T153	13		T351	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T138	5		T131	12		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	16		T16	1		T189	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T247	13		T257	10		T212	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T263	4		T284	3		T306	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	10		T139	12		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	5		T5	10		T138	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T247	10		T150	12		T256	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	11		T131	33		T257	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	13		T248	13		T262	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T7	2		T173	9		T287	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T269	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T270	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T7	2		T11	3		T15	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T22	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T331	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T270	1		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T187	7		T189	3		T133	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T38	2		T220	10		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T4	2		T6	9		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	21		T16	1		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	10		T128	1		T129	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T137	8		T197	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T13	2		T130	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	2		T128	1		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T29	2		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T131	1		T132	7		T220	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T136	14		T189	4		T255	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T130	5		T138	1		T247	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	3		T136	11		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T36	17		T139	13		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	9		T5	12		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	4		T140	13		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T3	13		T7	3		T131	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	13		T9	1		T37	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16176	1			T1	12		T2	20		T7	102
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T22	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T331	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T270	12		T349	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T187	2		T133	14		T264	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T220	11		T42	1		T253	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T10	14		T25	18		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	16		T139	3		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	13		T129	9		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T197	11		T347	18		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T42	2		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T132	7		T215	9		T279	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	5		T40	4		T285	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T131	12		T132	2		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T189	2		T142	15		T256	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	5		T247	13		T257	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T29	16		T16	1		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T36	10		T139	12		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	5		T5	10		T138	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T275	13		T142	14		T256	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	11		T7	2		T131	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	13		T247	10		T248	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2