Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21667

1

T1

12

T2

20

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

4313

1

T3

40

T5

45

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19649

1

T1

12

T2

20

T5

45

auto[1]

6331

1

T3

64

T4

2

T6

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T128	1		T340	19		T326	8
values[0]	72	1			T37	2		T247	26		T337	13
values[1]	644	1			T31	17		T129	28		T130	10
values[2]	3095	1			T3	14		T4	2		T6	9
values[3]	718	1			T5	22		T7	4		T24	1
values[4]	754	1			T29	19		T16	4		T169	13
values[5]	766	1			T5	23		T136	14		T16	1
values[6]	663	1			T7	2		T9	1		T13	3
values[7]	776	1			T12	1		T136	11		T137	17
values[8]	662	1			T3	24		T9	1		T137	4
values[9]	1238	1			T3	26		T7	5		T12	1
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	952	1			T3	14		T31	17		T37	2
values[1]	2902	1			T4	2		T5	22		T6	9
values[2]	896	1			T128	1		T130	5		T132	9
values[3]	685	1			T24	1		T29	19		T136	14
values[4]	720	1			T5	23		T9	1		T131	15
values[5]	804	1			T7	2		T12	1		T13	3
values[6]	699	1			T136	11		T137	8		T38	2
values[7]	772	1			T3	50		T9	1		T138	18
values[8]	796	1			T7	5		T12	1		T28	37
values[9]	189	1			T29	7		T142	15		T32	2
minimum	16565	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T31	10		T129	14		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	6		T37	2		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T4	2		T6	1		T10	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	11		T7	2		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T130	1		T132	3		T187	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T128	1		T165	11		T338	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T24	1		T29	17		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T16	1		T169	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T131	15		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	14		T214	1		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	1		T131	20		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	2		T13	3		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T132	8		T189	5		T247	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	1		T137	2		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	12		T42	2		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	14		T9	1		T138	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T128	1		T197	12		T292	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T7	3		T12	1		T28	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T142	15		T32	1		T270	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T29	6		T293	2		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16431	1			T1	12		T2	20		T7	99
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T31	7		T129	14		T133	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	8		T130	9		T248	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T6	8		T71	11		T73	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	11		T7	2		T36	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T130	4		T132	6		T187	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T256	16		T257	13		T262	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T29	2		T136	13		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T169	12		T140	14		T255	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T220	9		T140	9		T204	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	9		T214	10		T150	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T135	9		T161	11		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T137	12		T189	1		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T189	1		T247	11		T229	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T136	10		T137	6		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	12		T42	1		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	12		T42	1		T265	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T197	10		T292	15		T282	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	2		T28	20		T129	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T32	1		T352	2		T329	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T29	1		T293	1		T175	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	5		T31	1		T37	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T128	1		T326	5		T206	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T340	19		T276	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T247	15		T93	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T37	2		T337	1		T245	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	10		T129	14		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T130	1		T246	1		T275	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T4	2		T6	1		T10	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T3	6		T37	1		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	1		T130	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	11		T7	2		T36	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	17		T16	3		T132	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T169	1		T39	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T136	1		T138	6		T131	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	14		T16	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T9	1		T131	20		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	2		T13	3		T150	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T132	8		T247	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T136	1		T137	2		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	12		T42	2		T189	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	1		T137	1		T138	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T197	12		T142	15		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	525	1			T3	14		T7	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T326	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T276	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T247	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T337	12		T245	9		T307	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	7		T129	14		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	9		T275	19		T338	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T6	8		T71	11		T73	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	8		T37	1		T134	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T130	4		T135	12		T272	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	11		T7	2		T36	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	2		T16	1		T132	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T169	12		T140	14		T255	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T136	13		T140	9		T293	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	9		T214	10		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T220	9		T135	9		T161	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T150	11		T215	11		T272	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T247	11		T212	6		T279	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T136	10		T137	15		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	12		T42	1		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T137	3		T265	11		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T197	10		T292	15		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T3	12		T7	2		T28	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T31	11		T129	15		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T3	9		T37	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T4	2		T6	9		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	12		T7	4		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T130	5		T132	7		T187	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T128	1		T165	1		T338	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T24	1		T29	3		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T16	1		T169	13		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T131	1		T220	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	10		T214	11		T150	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T131	1		T135	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	2		T13	2		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	1		T189	4		T247	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T136	11		T137	8		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	13		T42	2		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	13		T9	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T128	1		T197	11		T292	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T7	3		T12	1		T28	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T142	1		T32	2		T270	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T29	2		T293	2		T175	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16562	1			T1	12		T2	20		T7	104
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T31	6		T129	13		T133	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	5		T37	1		T248	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T10	14		T25	18		T223	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	10		T36	10		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T132	2		T187	2		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T165	10		T256	17		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	16		T16	1		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T284	3		T142	15		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T131	14		T220	11		T266	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	13		T150	2		T252	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T131	19		T264	10		T254	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T247	10		T272	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	7		T189	2		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T253	8		T256	12		T257	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T42	1		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	13		T138	17		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T197	11		T181	13		T282	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	2		T28	16		T129	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T142	14		T270	12		T295	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T29	5		T293	1		T341	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T328	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T128	1		T326	6		T206	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T340	1		T276	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	12		T93	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T37	1		T337	13		T245	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	11		T129	15		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T130	10		T246	1		T275	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T4	2		T6	9		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T3	9		T37	2		T134	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T24	1		T130	5		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	12		T7	4		T36	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T29	3		T16	3		T132	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T169	13		T39	1		T140	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	14		T138	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	10		T16	1		T214	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T131	1		T220	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	2		T13	2		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T132	1		T247	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T136	11		T137	17		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	13		T42	2		T189	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	1		T137	4		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T197	11		T142	1		T292	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	461	1			T3	13		T7	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T326	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T340	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T247	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T37	1		T245	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T31	6		T129	13		T133	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T275	13		T282	13		T146	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T10	14		T25	18		T223	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T3	5		T134	9		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T213	15		T143	10		T321	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	10		T36	10		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	16		T16	1		T132	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T284	3		T256	11		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T138	5		T131	14		T266	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	13		T252	6		T285	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	19		T220	11		T263	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	1		T150	2		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	7		T247	13		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T253	8		T247	10		T257	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	11		T42	1		T189	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T138	17		T265	11		T213	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T197	11		T142	14		T181	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	438	1			T3	13		T7	2		T28	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2