Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21998

1

T1

12

T2

20

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3982

1

T3

24

T5

22

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19654

1

T1

12

T2

20

T5

22

auto[1]

6326

1

T3

64

T4

2

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T154	8		T251	13		-	-
values[0]	21	1			T3	14		T221	2		T353	4
values[1]	855	1			T5	23		T136	14		T137	17
values[2]	713	1			T7	4		T28	37		T16	5
values[3]	883	1			T3	24		T130	10		T39	2
values[4]	857	1			T3	26		T129	18		T42	3
values[5]	607	1			T9	1		T31	17		T128	1
values[6]	737	1			T7	5		T12	1		T136	11
values[7]	708	1			T5	22		T12	1		T37	2
values[8]	2901	1			T4	2		T6	9		T10	15
values[9]	1119	1			T7	2		T9	1		T13	3
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	911	1			T3	14		T5	23		T28	37
values[1]	989	1			T7	4		T16	4		T130	15
values[2]	739	1			T3	24		T129	18		T39	2
values[3]	753	1			T3	26		T128	1		T42	3
values[4]	667	1			T9	1		T12	1		T31	17
values[5]	788	1			T7	5		T136	11		T138	18
values[6]	2856	1			T4	2		T5	22		T6	9
values[7]	679	1			T12	1		T29	19		T137	4
values[8]	833	1			T7	2		T13	3		T24	1
values[9]	173	1			T9	1		T29	7		T142	15
minimum	16592	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	6		T5	14		T28	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T16	1		T137	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T16	3		T130	2		T131	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	2		T131	20		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T129	10		T39	2		T252	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	12		T135	1		T263	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	14		T128	1		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T265	12		T248	14		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T138	6		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	1		T31	10		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	1		T138	18		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	3		T220	12		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T4	2		T6	1		T10	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T5	11		T37	1		T133	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T137	1		T187	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	17		T131	13		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	3		T24	1		T36	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	2		T202	1		T40	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T354	12		T278	1		T309	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T9	1		T29	6		T142	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16430	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T136	1		T144	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	8		T5	9		T28	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T137	3		T169	12		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T16	1		T130	13		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	2		T140	14		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	8		T252	12		T272	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	12		T135	12		T263	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	12		T42	1		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T265	11		T248	12		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T174	11		T234	2		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T31	7		T220	9		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T136	10		T189	1		T272	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	2		T220	17		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T6	8		T71	11		T73	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	11		T37	1		T133	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T137	3		T187	6		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T29	2		T139	12		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T36	14		T129	14		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	7		T160	2		T256	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T354	12		T309	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T29	1		T279	13		T173	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T136	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T251	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T154	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T3	6		T353	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	1		T348	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	14		T137	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T136	1		T137	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T28	17		T16	3		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	2		T16	1		T131	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T130	1		T39	2		T247	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	12		T140	1		T150	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	14		T129	10		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T265	12		T135	1		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T128	1		T138	6		T180	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	1		T31	10		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T136	1		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	3		T220	12		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T138	18		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	11		T37	1		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T4	2		T6	1		T10	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	17		T131	13		T139	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	3		T24	1		T36	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T7	2		T9	1		T29	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T3	8		T353	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T221	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	9		T137	12		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T136	13		T137	3		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	20		T16	1		T130	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	2		T242	6		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T130	9		T247	11		T272	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	12		T140	14		T150	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	12		T129	8		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T265	11		T135	12		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T268	1		T355	9		T329	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T31	7		T220	9		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	10		T272	1		T292	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	2		T220	17		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T189	1		T257	12		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	11		T37	1		T133	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T6	8		T71	11		T73	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T29	2		T139	12		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T36	14		T129	14		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T29	1		T40	7		T160	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	9		T5	10		T28	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T16	1		T137	4		T169	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T16	3		T130	15		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	4		T131	1		T140	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	9		T39	2		T252	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	13		T135	13		T263	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	13		T128	1		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T265	12		T248	13		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	1		T138	1		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T9	1		T31	11		T220	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	11		T138	1		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	3		T220	18		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T4	2		T6	9		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	12		T37	2		T133	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T137	4		T187	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	3		T131	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	2		T24	1		T36	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	2		T202	1		T40	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T354	13		T278	1		T309	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T9	1		T29	2		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16559	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T136	14		T144	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	5		T5	13		T28	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T180	9		T266	16		T282	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T16	1		T131	14		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T131	19		T150	12		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T129	9		T252	6		T272	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	11		T263	4		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	13		T42	1		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T265	11		T248	13		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T138	5		T212	10		T288	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	6		T220	11		T247	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	17		T262	5		T213	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	2		T220	11		T197	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T10	14		T25	18		T223	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	10		T133	14		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T187	2		T180	9		T258	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	16		T131	12		T132	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T36	10		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T40	4		T256	11		T257	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T354	11		T309	12		T273	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T29	5		T142	14		T279	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T286	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T144	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T251	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T154	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T3	9		T353	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T221	2		T348	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	10		T137	13		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T136	14		T137	4		T169	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T28	21		T16	3		T130	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	4		T16	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T130	10		T39	2		T247	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	13		T140	15		T150	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	13		T129	9		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T265	12		T135	13		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T128	1		T138	1		T180	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	1		T31	11		T220	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T136	11		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	3		T220	18		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T138	1		T189	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	12		T37	2		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T4	2		T6	9		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	3		T131	1		T139	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T13	2		T24	1		T36	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T7	2		T9	1		T29	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T251	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T154	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T3	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	13		T254	13		T279	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T180	9		T266	16		T282	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	16		T16	1		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T131	19		T270	8		T283	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T247	10		T272	13		T264	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	11		T150	12		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	13		T129	9		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T265	11		T229	1		T263	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T138	5		T212	10		T288	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T31	6		T220	11		T248	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T262	5		T213	15		T354	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	2		T220	11		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T138	17		T257	7		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	10		T132	7		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T10	14		T25	18		T223	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	16		T131	12		T139	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	1		T36	10		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T29	5		T40	4		T263	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2