Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22634

1

T1

12

T2

20

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3346

1

T3

24

T5

22

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19823

1

T1

12

T2

20

T3

14

auto[1]

6157

1

T3

50

T4

2

T5

45

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T137	13		T266	17		T287	15
values[0]	112	1			T187	9		T272	30		T172	21
values[1]	816	1			T3	26		T29	7		T169	13
values[2]	762	1			T3	14		T5	23		T16	4
values[3]	760	1			T137	4		T202	1		T131	20
values[4]	777	1			T3	24		T7	4		T28	37
values[5]	2871	1			T4	2		T5	22		T6	9
values[6]	792	1			T9	1		T36	27		T37	2
values[7]	608	1			T9	1		T12	1		T128	1
values[8]	779	1			T31	17		T128	1		T16	1
values[9]	1098	1			T7	7		T12	1		T13	3
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1028	1			T3	26		T29	7		T169	13
values[1]	823	1			T3	14		T5	23		T16	4
values[2]	812	1			T129	18		T137	4		T202	1
values[3]	2936	1			T3	24		T4	2		T6	9
values[4]	621	1			T5	22		T36	27		T37	2
values[5]	731	1			T9	1		T136	11		T131	13
values[6]	668	1			T9	1		T12	1		T128	1
values[7]	741	1			T24	1		T31	17		T128	1
values[8]	874	1			T12	1		T13	3		T29	19
values[9]	119	1			T7	7		T138	18		T189	6
minimum	16627	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T3	14		T197	12		T253	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T29	6		T169	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	6		T5	14		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T16	3		T189	1		T265	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T129	10		T137	1		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T131	15		T39	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T4	2		T6	1		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	12		T131	20		T40	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T36	13		T39	2		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	11		T37	1		T138	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T136	1		T131	13		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	1		T247	14		T275	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	1		T130	1		T275	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T12	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T31	10		T16	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	1		T128	1		T220	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T13	3		T37	2		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T29	17		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T7	2		T339	1		T301	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T7	3		T138	18		T189	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16451	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T187	3		T107	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	12		T197	10		T253	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T29	1		T169	12		T140	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	8		T5	9		T247	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T189	1		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T129	8		T137	3		T189	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T220	17		T263	1		T254	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T6	8		T7	2		T28	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	12		T40	7		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	14		T140	9		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	11		T37	1		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T136	10		T255	5		T272	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T247	11		T275	19		T257	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T137	3		T130	9		T256	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T133	18		T160	2		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T31	7		T130	4		T132	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T220	9		T142	16		T171	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T42	1		T140	12		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	2		T136	13		T129	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T328	3		T356	14		T357	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T7	2		T189	1		T358	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T187	6		T107	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T266	17		T287	15		T304	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T137	1		T98	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T172	11		T277	1		T327	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T187	3		T272	14		T18	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	14		T38	2		T197	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	6		T169	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	6		T5	14		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	3		T189	1		T265	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	1		T202	1		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T131	20		T39	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	2		T28	17		T129	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	12		T131	15		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T4	2		T6	1		T10	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	11		T138	6		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T36	13		T136	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	1		T37	1		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T130	1		T139	4		T275	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T9	1		T12	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	10		T16	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T128	1		T220	12		T133	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T7	2		T13	3		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T7	3		T12	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T137	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T172	10		T277	11		T327	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T187	6		T272	16		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	12		T197	10		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	1		T169	12		T140	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	8		T5	9		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T16	1		T189	1		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T137	3		T139	12		T189	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T263	1		T258	15		T359	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	2		T28	20		T129	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	12		T220	17		T40	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T6	8		T71	11		T73	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	11		T214	10		T264	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	14		T136	10		T140	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T37	1		T134	11		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	9		T139	11		T272	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T160	2		T161	8		T256	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	7		T137	3		T130	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T220	9		T133	18		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T42	1		T140	12		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	2		T29	2		T136	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T3	13		T197	11		T253	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T29	2		T169	13		T140	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	9		T5	10		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T16	3		T189	2		T265	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T129	9		T137	4		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T131	1		T39	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T4	2		T6	9		T7	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	13		T131	1		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T36	17		T39	2		T140	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	12		T37	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T136	11		T131	1		T255	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	1		T247	12		T275	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T137	4		T130	10		T275	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	1		T12	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T31	11		T16	1		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T24	1		T128	1		T220	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	2		T37	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T29	3		T136	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T7	2		T339	1		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T7	3		T138	1		T189	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16577	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T187	7		T107	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	13		T197	11		T253	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	5		T252	6		T284	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	5		T5	13		T247	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	1		T265	11		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T129	9		T150	2		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T131	14		T220	11		T263	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T10	14		T25	18		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	11		T131	19		T40	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	10		T215	9		T266	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T5	10		T138	5		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	12		T153	13		T270	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T247	13		T275	13		T257	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T256	6		T153	10		T212	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T133	14		T256	12		T257	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T31	6		T132	2		T139	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T220	11		T142	15		T212	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	1		T37	1		T132	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	16		T129	13		T261	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T301	7		T349	4		T328	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T7	2		T138	17		T189	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T213	11		T360	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T187	2		T107	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T266	1		T287	1		T304	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T137	13		T98	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T172	11		T277	12		T327	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T187	7		T272	17		T18	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	13		T38	2		T197	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	2		T169	13		T140	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	9		T5	10		T247	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	3		T189	2		T265	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T137	4		T202	1		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	1		T39	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	4		T28	21		T129	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	13		T131	1		T220	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T4	2		T6	9		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	12		T138	1		T214	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	17		T136	11		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	1		T37	2		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T130	10		T139	12		T275	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	1		T12	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T31	11		T16	1		T137	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T128	1		T220	10		T133	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T7	2		T13	2		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	3		T12	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T266	16		T287	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T172	10		T310	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T187	2		T272	13		T173	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	13		T197	11		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	5		T262	15		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	5		T5	13		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	1		T265	11		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T139	12		T150	2		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T131	19		T263	4		T258	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T28	16		T129	9		T256	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	11		T131	14		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T10	14		T25	18		T223	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	10		T138	5		T165	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T36	10		T131	12		T153	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T134	9		T247	13		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T139	3		T256	6		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T256	12		T282	10		T258	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	6		T132	2		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T220	11		T133	14		T212	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T13	1		T37	1		T132	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	2		T29	16		T129	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2