Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22625

1

T1

12

T2

20

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3355

1

T3

24

T5

22

T7

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19842

1

T1

12

T2

20

T3

14

auto[1]

6138

1

T3

50

T4

2

T5

45

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	279	1			T37	2		T129	28		T138	18
values[0]	35	1			T187	9		T172	21		T327	5
values[1]	849	1			T3	26		T29	7		T169	13
values[2]	790	1			T3	14		T5	23		T16	4
values[3]	733	1			T137	4		T202	1		T131	15
values[4]	847	1			T3	24		T7	4		T28	37
values[5]	2852	1			T4	2		T5	22		T6	9
values[6]	790	1			T9	1		T36	27		T37	2
values[7]	644	1			T9	1		T12	1		T128	1
values[8]	754	1			T31	17		T128	1		T16	1
values[9]	849	1			T7	7		T12	1		T13	3
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	857	1			T3	14		T29	7		T38	2
values[1]	736	1			T5	23		T16	4		T189	2
values[2]	773	1			T129	18		T137	4		T202	1
values[3]	2997	1			T3	24		T4	2		T6	9
values[4]	655	1			T5	22		T36	27		T37	2
values[5]	705	1			T9	1		T136	11		T131	13
values[6]	647	1			T9	1		T12	1		T128	1
values[7]	779	1			T24	1		T31	17		T128	1
values[8]	851	1			T7	5		T12	1		T29	19
values[9]	110	1			T7	2		T13	3		T129	28
minimum	16870	1			T1	12		T2	20		T3	26

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	6		T253	9		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T29	6		T38	2		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	14		T189	1		T247	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	3		T265	12		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T129	10		T137	1		T139	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T202	1		T131	15		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T4	2		T6	1		T10	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	12		T7	2		T131	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	13		T39	2		T215	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	11		T37	1		T138	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T136	1		T131	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T247	14		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T128	1		T137	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T12	1		T133	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T31	10		T16	1		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T24	1		T128	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T42	3		T140	1		T289	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	3		T12	1		T29	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	2		T13	3		T138	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T129	14		T98	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16532	1			T1	12		T2	20		T3	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T169	1		T187	3		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	8		T253	10		T135	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T29	1		T214	15		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	9		T189	1		T247	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	1		T265	11		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T129	8		T137	3		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T254	13		T145	14		T359	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T6	8		T28	20		T71	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	12		T7	2		T220	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	14		T215	11		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	11		T37	1		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T136	10		T140	9		T257	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T247	11		T255	5		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T137	3		T130	9		T272	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T133	18		T160	2		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	7		T248	12		T272	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T130	4		T132	6		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T42	1		T140	12		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	2		T29	2		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T189	1		T153	1		T19	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T129	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	12		T7	5		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T169	12		T187	6		T140	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T138	18		T189	5		T285	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T37	2		T129	14		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T172	11		T327	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T187	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	14		T197	12		T253	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	6		T169	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	6		T5	14		T189	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T16	3		T265	12		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T137	1		T139	13		T189	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T202	1		T131	15		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T28	17		T129	10		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	12		T7	2		T131	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T4	2		T6	1		T10	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	11		T138	6		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T36	13		T136	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T37	1		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T128	1		T272	1		T256	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T12	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T31	10		T16	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T128	1		T130	1		T132	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	2		T13	3		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	3		T12	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T189	1		T285	7		T264	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T129	14		T255	10		T361	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T172	10		T327	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T187	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	12		T197	10		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	1		T169	12		T140	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	8		T5	9		T189	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	1		T265	11		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	3		T139	12		T189	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T258	15		T145	14		T359	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	20		T129	8		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	12		T7	2		T220	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T6	8		T71	11		T73	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	11		T148	11		T214	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	14		T136	10		T140	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T37	1		T134	11		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T272	1		T256	5		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T160	2		T161	8		T256	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T31	7		T137	3		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T130	4		T132	6		T220	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T42	1		T140	12		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	2		T29	2		T136	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	9		T253	11		T135	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T29	2		T38	2		T214	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	10		T189	2		T247	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	3		T265	12		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T129	9		T137	4		T139	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T202	1		T131	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T4	2		T6	9		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	13		T7	4		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	17		T39	2		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	12		T37	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T136	11		T131	1		T140	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T247	12		T255	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	1		T137	4		T130	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T12	1		T133	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	11		T16	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T24	1		T128	1		T130	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T42	2		T140	13		T289	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	3		T12	1		T29	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T7	2		T13	2		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T129	15		T98	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16663	1			T1	12		T2	20		T3	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T169	13		T187	7		T140	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	5		T253	8		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	5		T252	6		T284	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	13		T247	10		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T265	11		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T129	9		T139	12		T150	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T131	14		T254	13		T306	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T10	14		T25	18		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	11		T131	19		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	10		T215	9		T153	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	10		T138	5		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T131	12		T257	8		T270	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T247	13		T143	10		T243	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T256	12		T153	10		T212	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T133	14		T256	6		T257	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	6		T132	7		T248	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	2		T220	11		T139	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T42	2		T285	6		T264	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	2		T29	16		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T13	1		T138	17		T189	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T129	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	13		T197	11		T172	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T187	2		T262	15		T344	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T138	1		T189	4		T285	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T37	1		T129	15		T255	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T172	11		T327	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T187	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	13		T197	11		T253	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T29	2		T169	13		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	9		T5	10		T189	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	3		T265	12		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T137	4		T139	13		T189	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T202	1		T131	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T28	21		T129	9		T160	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	13		T7	4		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T4	2		T6	9		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	12		T138	1		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	17		T136	11		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	1		T37	2		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T128	1		T272	2		T256	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T12	1		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T31	11		T16	1		T137	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T128	1		T130	5		T132	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	2		T13	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	3		T12	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T138	17		T189	2		T285	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T37	1		T129	13		T181	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T172	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T187	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	13		T197	11		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	5		T272	13		T262	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	5		T5	13		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	1		T265	11		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T139	12		T150	2		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	14		T258	12		T290	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T28	16		T129	9		T256	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	11		T131	19		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T10	14		T25	18		T223	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	10		T138	5		T165	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	10		T131	12		T257	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T134	9		T247	13		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T256	12		T153	10		T270	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T256	6		T257	7		T258	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	6		T212	10		T266	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T132	2		T220	11		T139	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T132	7		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	2		T29	16		T261	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2