Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22268

1

T1

12

T2

20

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3712

1

T3

38

T7

2

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19806

1

T1

12

T2

20

T3

40

auto[1]

6174

1

T3

24

T4

2

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	308	1			T9	2		T136	11		T138	18
values[0]	58	1			T257	25		T245	18		T260	15
values[1]	791	1			T5	22		T12	2		T36	27
values[2]	755	1			T3	26		T5	23		T13	3
values[3]	696	1			T3	14		T29	7		T202	1
values[4]	2962	1			T4	2		T6	9		T10	15
values[5]	788	1			T7	5		T28	37		T129	18
values[6]	532	1			T7	2		T128	1		T189	2
values[7]	1047	1			T29	19		T137	13		T246	1
values[8]	630	1			T16	1		T138	6		T131	13
values[9]	855	1			T3	24		T7	4		T136	14
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	758	1			T5	22		T12	2		T36	27
values[1]	781	1			T3	40		T5	23		T13	3
values[2]	605	1			T29	7		T130	5		T131	20
values[3]	3059	1			T4	2		T6	9		T7	5
values[4]	677	1			T137	4		T38	2		T40	14
values[5]	834	1			T7	2		T128	1		T139	15
values[6]	720	1			T29	19		T137	13		T246	1
values[7]	707	1			T7	4		T16	1		T137	4
values[8]	895	1			T3	24		T9	2		T136	25
values[9]	101	1			T140	13		T243	15		T251	13
minimum	16843	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	11		T12	1		T36	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T37	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	14		T5	14		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	6		T13	3		T132	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	6		T229	3		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T130	1		T131	20		T189	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T4	2		T6	1		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	1		T129	10		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T137	1		T42	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	2		T40	7		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T139	4		T134	11		T213	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	2		T128	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T246	1		T220	12		T215	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T29	17		T137	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	2		T137	1		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	1		T138	6		T131	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T9	1		T136	1		T129	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	12		T9	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T243	1		T250	1		T267	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T140	1		T251	13		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16470	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T39	2		T161	1		T257	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	11		T36	14		T252	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T37	1		T148	11		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	12		T5	9		T220	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	8		T248	12		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	1		T229	1		T254	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T130	4		T189	1		T255	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T6	8		T7	2		T28	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T129	8		T130	9		T132	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T137	3		T42	1		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T40	7		T133	18		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T139	11		T134	11		T213	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T42	1		T140	14		T214	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T220	17		T215	16		T256	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	2		T137	12		T140	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	2		T137	3		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T257	13		T258	8		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T136	10		T129	14		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	12		T136	13		T247	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T243	14		T250	3		T362	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T140	12		T259	9		T21	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T257	14		T234	2		T316	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T9	1		T136	1		T138	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T9	1		T140	1		T142	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T245	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T257	11		T260	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	11		T12	1		T36	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T37	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	14		T5	14		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	3		T248	14		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T29	6		T202	1		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	6		T131	20		T132	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T4	2		T6	1		T10	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T24	1		T130	2		T132	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	3		T28	17		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T129	10		T38	2		T40	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T134	11		T214	1		T143	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	2		T128	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T246	1		T220	12		T139	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T29	17		T137	1		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T189	2		T197	12		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	1		T138	6		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	2		T129	14		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	12		T136	1		T247	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T136	10		T256	5		T242	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T140	12		T173	8		T314	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T245	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T257	14		T260	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	11		T36	14		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T37	1		T148	11		T253	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	12		T5	9		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T248	12		T160	2		T142	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	1		T229	1		T254	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	8		T255	22		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T6	8		T31	7		T71	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	13		T132	6		T187	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	2		T28	20		T137	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T129	8		T40	7		T133	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	11		T214	10		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T189	1		T214	15		T261	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T220	17		T139	11		T215	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	2		T137	12		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T189	1		T197	10		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T263	6		T257	13		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	2		T129	14		T137	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	12		T136	13		T247	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	12		T12	1		T36	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	1		T37	2		T148	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	13		T5	10		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	9		T13	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	2		T229	3		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T130	5		T131	1		T189	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T4	2		T6	9		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T24	1		T129	9		T130	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	4		T42	2		T135	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	2		T40	10		T133	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	12		T134	13		T213	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	2		T128	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T246	1		T220	18		T215	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	3		T137	13		T140	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	4		T137	4		T189	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	1		T138	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T9	1		T136	11		T129	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	13		T9	1		T136	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T243	15		T250	4		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T140	13		T251	1		T259	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16620	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	2		T161	1		T257	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	10		T36	10		T252	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T253	8		T142	15		T264	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	13		T5	13		T131	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	5		T13	1		T132	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	5		T229	1		T254	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T131	19		T189	2		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T7	2		T10	14		T25	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T129	9		T132	2		T187	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	2		T150	12		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	4		T133	14		T256	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T139	3		T134	9		T213	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T42	1		T150	2		T263	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T220	11		T215	18		T256	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	16		T265	11		T263	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T197	11		T153	13		T266	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	5		T131	12		T257	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T129	13		T138	17		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	11		T247	10		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T267	2		T362	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T251	12		T21	11		T269	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T266	4		T147	11		T245	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T257	10		T288	10		T234	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T9	1		T136	11		T138	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T9	1		T140	13		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T245	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T257	15		T260	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	12		T12	1		T36	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	1		T37	2		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	13		T5	10		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	2		T248	13		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T29	2		T202	1		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	9		T131	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T4	2		T6	9		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T24	1		T130	15		T132	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	3		T28	21		T137	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T129	9		T38	2		T40	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	13		T214	11		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	2		T128	1		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T246	1		T220	18		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T29	3		T137	13		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T189	3		T197	11		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	1		T138	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T7	4		T129	15		T137	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	13		T136	14		T247	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T138	17		T256	12		T143	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T142	14		T251	12		T173	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T245	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T257	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	10		T36	10		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T253	8		T180	9		T296	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	13		T5	13		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T248	13		T142	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	5		T229	1		T254	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	5		T131	19		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T10	14		T25	18		T31	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T132	2		T187	2		T189	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	2		T28	16		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	9		T40	4		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T134	9		T143	2		T270	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T261	2		T256	6		T266	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T220	11		T139	3		T215	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T29	16		T42	1		T265	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T197	11		T180	9		T153	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T138	5		T131	12		T263	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T129	13		T247	13		T257	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	11		T247	10		T212	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2