Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	9		T5	10		T28	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T136	14		T16	1		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T16	3		T130	15		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	4		T131	1		T140	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	2		T247	24		T272	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	13		T129	9		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	13		T31	11		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T265	12		T248	13		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T138	1		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	1		T220	10		T247	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T136	11		T138	1		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	3		T148	12		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T4	2		T6	9		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	12		T37	2		T133	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T137	4		T189	4		T161	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T29	3		T131	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	2		T24	1		T36	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	2		T9	1		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T142	1		T154	1		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16636	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T180	1		T144	1		T274	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	5		T5	13		T28	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T266	16		T282	13		T270	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T16	1		T131	14		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	19		T150	12		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T247	23		T272	13		T266	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	11		T129	9		T252	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	13		T31	6		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T265	11		T248	13		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T138	5		T212	10		T172	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T220	11		T247	14		T275	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T138	17		T220	11		T257	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	2		T197	11		T284	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T10	14		T25	18		T223	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	10		T133	14		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T189	2		T180	9		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	16		T131	12		T132	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T36	10		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T29	5		T40	4		T285	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T273	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T142	14		T154	7		T176	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T254	13		T251	10		T286	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T180	9		T144	16		T287	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T150	12		T182	1		T278	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T9	1		T279	3		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	9		T5	10		T137	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T136	14		T137	4		T169	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T28	21		T16	3		T130	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	4		T16	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T39	2		T247	24		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T3	13		T150	12		T252	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	13		T42	2		T160	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T129	9		T265	12		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T31	11		T128	1		T180	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	1		T220	10		T142	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T136	11		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	3		T148	12		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T12	1		T138	1		T189	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	12		T37	2		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T4	2		T6	9		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	3		T131	1		T187	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	2		T24	1		T36	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	2		T29	2		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T150	2		T273	7		T280	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T279	6		T154	7		T288	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	5		T5	13		T254	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T180	9		T282	13		T144	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T28	16		T16	1		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	19		T266	16		T283	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T247	23		T272	13		T264	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	11		T150	12		T252	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	13		T42	1		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T129	9		T265	11		T248	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T31	6		T212	10		T288	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T220	11		T142	15		T153	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	5		T220	11		T257	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	2		T197	11		T247	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T138	17		T262	5		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	10		T132	7		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T10	14		T25	18		T223	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	16		T131	12		T187	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T36	10		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T29	5		T40	4		T263	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2