Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22511

1

T1

12

T2

20

T3

50

auto[ADC_CTRL_FILTER_COND_OUT]

3469

1

T3

14

T7

2

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19730

1

T1

12

T2

20

T3

64

auto[1]

6250

1

T4

2

T5

23

T6

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	238	1			T12	1		T37	2		T136	11
values[1]	726	1			T5	22		T7	7		T24	1
values[2]	524	1			T16	1		T202	1		T220	21
values[3]	658	1			T9	1		T12	1		T29	7
values[4]	802	1			T5	23		T31	17		T220	29
values[5]	2958	1			T4	2		T6	9		T7	4
values[6]	798	1			T3	24		T37	2		T129	28
values[7]	732	1			T136	14		T128	1		T138	6
values[8]	849	1			T3	26		T137	4		T130	5
values[9]	1137	1			T3	14		T9	1		T137	13
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	729	1			T5	22		T7	7		T129	18
values[1]	519	1			T12	1		T16	1		T202	1
values[2]	800	1			T5	23		T9	1		T29	7
values[3]	2836	1			T4	2		T6	9		T10	15
values[4]	985	1			T3	24		T7	4		T13	3
values[5]	626	1			T38	2		T132	8		T189	9
values[6]	883	1			T136	14		T128	1		T138	6
values[7]	692	1			T3	26		T137	4		T130	5
values[8]	1086	1			T3	14		T9	1		T12	1
values[9]	127	1			T289	1		T32	12		T182	1
minimum	16697	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	11		T7	3		T263	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	2		T129	10		T131	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	1		T202	1		T247	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T220	12		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T5	14		T29	6		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T140	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T4	2		T6	1		T10	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	10		T134	10		T215	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T3	12		T7	2		T28	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	3		T128	1		T129	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T132	8		T189	7		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	2		T148	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T136	1		T187	3		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T128	1		T138	6		T131	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	14		T137	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	1		T140	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T37	2		T136	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T3	6		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T32	1		T290	15		T291	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T289	1		T32	1		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16480	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T24	1		T16	3		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	11		T7	2		T263	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T129	8		T161	11		T258	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T247	11		T292	15		T146	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T220	9		T229	1		T215	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	9		T29	1		T36	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	14		T160	2		T275	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T6	8		T71	11		T73	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T31	7		T134	11		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	12		T7	2		T28	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	14		T40	7		T293	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T189	2		T150	11		T252	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	11		T160	11		T261	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	13		T187	6		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T42	1		T213	13		T216	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	12		T137	3		T130	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T140	9		T135	12		T257	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T136	10		T169	12		T247	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	8		T137	12		T132	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T32	9		T294	10		T295	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T32	1		T258	8		T296	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T16	1		T130	9		T297	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T37	2		T136	1		T257	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T12	1		T182	1		T258	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T7	3		T263	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	2		T24	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	1		T202	1		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T220	12		T215	10		T142	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	6		T36	13		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T12	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	14		T220	12		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T31	10		T134	10		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T4	2		T6	1		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	3		T128	1		T131	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	12		T37	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T129	14		T38	2		T40	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	1		T187	3		T42	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T128	1		T138	6		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	14		T137	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T131	20		T39	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T169	1		T247	15		T248	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	6		T9	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T136	10		T257	12		T32	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T258	8		T298	2		T299	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	11		T7	2		T263	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T16	1		T129	8		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T247	11		T292	15		T254	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T220	9		T215	11		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T29	1		T36	14		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	14		T229	1		T275	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	9		T220	17		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T31	7		T134	11		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T6	8		T7	2		T28	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T215	5		T173	7		T300	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	12		T37	1		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T129	14		T40	7		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	13		T187	6		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	1		T261	7		T256	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	12		T137	3		T130	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	12		T257	14		T262	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T169	12		T247	11		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	8		T137	12		T132	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	12		T7	3		T263	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	2		T129	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	1		T202	1		T247	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T220	10		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	10		T29	2		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T140	15		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T4	2		T6	9		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	11		T134	12		T215	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T3	13		T7	4		T28	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	2		T128	1		T129	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T132	1		T189	7		T150	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T38	2		T148	12		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	14		T187	7		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T128	1		T138	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	13		T137	4		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	1		T140	10		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T37	1		T136	11		T169	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	9		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T32	10		T290	1		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T289	1		T32	2		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16606	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T24	1		T16	3		T130	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	10		T7	2		T263	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T129	9		T131	12		T258	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T247	10		T146	2		T221	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T220	11		T229	1		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	13		T29	5		T36	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T275	13		T264	8		T256	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T10	14		T25	18		T223	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T31	6		T134	9		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	11		T28	16		T29	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T129	13		T131	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T132	7		T189	2		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T261	2		T256	6		T266	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T187	2		T42	2		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T138	5		T131	19		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	13		T139	3		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T257	10		T262	5		T279	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T37	1		T247	14		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	5		T138	17		T132	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T290	14		T291	7		T294	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T258	8		T296	3		T267	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T264	10		T301	7		T302	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T16	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T37	1		T136	11		T257	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T12	1		T182	1		T258	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	12		T7	3		T263	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	2		T24	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T16	1		T202	1		T247	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T220	10		T215	12		T142	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	2		T36	17		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	1		T12	1		T140	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	10		T220	18		T189	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T31	11		T134	12		T160	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T4	2		T6	9		T7	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	2		T128	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	13		T37	2		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T129	15		T38	2		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T136	14		T187	7		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T128	1		T138	1		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	13		T137	4		T130	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T131	1		T39	1		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T169	13		T247	12		T248	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	9		T9	1		T137	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T37	1		T257	7		T181	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T258	8		T299	12		T303	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	10		T7	2		T263	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	1		T129	9		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T247	10		T254	13		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T220	11		T215	9		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	5		T36	10		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T229	1		T275	13		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	13		T220	11		T265	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	6		T134	9		T263	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T10	14		T25	18		T28	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	1		T131	14		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	11		T132	7		T189	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T129	13		T40	4		T266	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T187	2		T42	2		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T138	5		T42	1		T261	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	13		T139	3		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	19		T257	10		T262	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T247	14		T248	13		T142	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	5		T138	17		T132	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2