Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19951

1

T1

12

T2

20

T3

50

auto[ADC_CTRL_FILTER_COND_OUT]

6029

1

T3

14

T4

2

T5

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19852

1

T1

12

T2

20

T3

38

auto[1]

6128

1

T3

26

T4

2

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T278	1		-	-		-	-
values[0]	72	1			T17	9		T304	1		T305	24
values[1]	810	1			T3	14		T9	1		T128	1
values[2]	749	1			T31	17		T36	27		T131	15
values[3]	837	1			T28	37		T29	19		T37	2
values[4]	604	1			T13	3		T16	4		T42	4
values[5]	452	1			T5	22		T137	4		T138	6
values[6]	697	1			T7	5		T12	1		T136	11
values[7]	991	1			T12	1		T38	2		T220	29
values[8]	712	1			T3	24		T7	4		T9	1
values[9]	3497	1			T3	26		T4	2		T5	23
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1063	1			T3	14		T9	1		T36	27
values[1]	2927	1			T4	2		T6	9		T10	15
values[2]	781	1			T28	37		T29	19		T37	2
values[3]	605	1			T13	3		T138	6		T42	3
values[4]	529	1			T5	22		T12	1		T137	17
values[5]	808	1			T7	5		T136	11		T128	1
values[6]	746	1			T7	4		T9	1		T12	1
values[7]	894	1			T3	24		T29	7		T37	2
values[8]	919	1			T3	26		T5	23		T7	2
values[9]	136	1			T137	4		T249	1		T182	1
minimum	16572	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T9	1		T36	13		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T3	6		T39	2		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T131	15		T229	3		T252	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T4	2		T6	1		T10	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T28	17		T29	17		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	2		T16	3		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	3		T42	2		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T138	6		T197	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	11		T12	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T137	2		T148	1		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T187	3		T253	9		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T7	3		T136	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	2		T12	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T38	2		T220	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	12		T29	6		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T139	13		T265	12		T150	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	14		T132	11		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	14		T7	2		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T137	1		T182	1		T306	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T249	1		T307	1		T308	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16428	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T36	14		T140	14		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	8		T40	7		T255	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T229	1		T252	12		T256	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	982	1			T6	8		T31	7		T71	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T28	20		T29	2		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	1		T169	12		T220	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T42	1		T255	12		T285	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T197	10		T160	11		T172	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	11		T204	10		T216	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T137	15		T148	11		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T187	6		T253	10		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T7	2		T136	10		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	2		T140	9		T214	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T220	17		T135	9		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	12		T29	1		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T139	12		T265	11		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	12		T132	6		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	9		T129	22		T130	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T137	3		T293	1		T175	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T307	13		T308	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T276	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T278	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T309	13		T310	3		T311	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T17	7		T304	1		T305	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	1		T128	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	6		T39	2		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T36	13		T131	15		T252	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	10		T39	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T28	17		T29	17		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	2		T169	1		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	3		T42	3		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	3		T197	12		T180	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	11		T42	2		T285	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T137	1		T138	6		T258	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	1		T187	3		T253	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	3		T136	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T214	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T38	2		T220	12		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	12		T7	2		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	1		T139	13		T247	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T3	14		T137	1		T132	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1696	1			T4	2		T5	14		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T309	4		T310	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T17	2		T305	11		T312	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T140	14		T189	1		T133	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	8		T40	7		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	14		T252	12		T256	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T31	7		T140	12		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	20		T29	2		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T169	12		T220	9		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T42	1		T255	12		T257	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T16	1		T197	10		T172	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T5	11		T42	1		T285	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T137	3		T258	8		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T187	6		T253	10		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	2		T136	10		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T214	15		T160	14		T171	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T220	17		T135	9		T161	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	12		T7	2		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T139	12		T247	11		T248	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	12		T137	3		T132	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1119	1			T5	9		T6	8		T71	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T36	17		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T3	9		T39	2		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	1		T229	3		T252	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T4	2		T6	9		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T28	21		T29	3		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T37	1		T16	3		T169	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	2		T42	2		T255	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T138	1		T197	11		T160	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	12		T12	1		T204	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T137	17		T148	12		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T187	7		T253	11		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T7	3		T136	11		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	4		T12	1		T140	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	1		T38	2		T220	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	13		T29	2		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T139	13		T265	12		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	13		T132	8		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	10		T7	2		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T137	4		T182	1		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T249	1		T307	14		T308	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16559	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T276	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T36	10		T131	19		T133	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	5		T40	4		T142	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T131	14		T229	1		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1231	1			T10	14		T25	18		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	16		T29	16		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	1		T16	1		T220	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	1		T42	1		T285	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T138	5		T197	11		T270	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T5	10		T216	12		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	9		T258	8		T290	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T187	2		T253	8		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	2		T138	17		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T254	5		T143	30		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T220	11		T247	14		T264	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	11		T29	5		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T139	12		T265	11		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	13		T132	9		T264	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	13		T129	22		T139	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T306	5		T313	3		T314	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T308	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T278	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T309	5		T310	5		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T17	7		T304	1		T305	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T128	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	9		T39	2		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T36	17		T131	1		T252	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T31	11		T39	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	21		T29	3		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T37	1		T169	13		T220	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	2		T42	2		T255	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	3		T197	11		T180	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	12		T42	2		T285	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	4		T138	1		T258	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T187	7		T253	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	3		T136	11		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	1		T214	16		T160	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T38	2		T220	18		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	13		T7	4		T29	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T139	13		T247	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T3	13		T137	4		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1485	1			T4	2		T5	10		T6	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T309	12		T310	2		T311	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T17	2		T305	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T131	19		T133	14		T256	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	5		T40	4		T142	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T36	10		T131	14		T252	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	6		T165	10		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T28	16		T29	16		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T37	1		T220	11		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T42	2		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T197	11		T181	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T5	10		T42	1		T285	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T138	5		T258	8		T251	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T187	2		T253	8		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	2		T138	17		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T254	5		T262	5		T143	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T220	11		T263	5		T272	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	11		T29	5		T275	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T139	12		T247	14		T248	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T3	13		T132	9		T264	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1330	1			T5	13		T10	14		T25	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2