Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22520

1

T1

12

T2

20

T3

50

auto[ADC_CTRL_FILTER_COND_OUT]

3460

1

T3

14

T7

2

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19750

1

T1

12

T2

20

T3

64

auto[1]

6230

1

T4

2

T5

23

T6

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T181	14		-	-		-	-
values[0]	64	1			T7	5		T271	42		T221	2
values[1]	703	1			T5	22		T7	2		T24	1
values[2]	446	1			T16	1		T202	1		T220	21
values[3]	647	1			T9	1		T12	1		T29	7
values[4]	850	1			T5	23		T31	17		T220	29
values[5]	2983	1			T4	2		T6	9		T7	4
values[6]	758	1			T3	24		T37	2		T129	28
values[7]	721	1			T136	14		T128	1		T138	6
values[8]	904	1			T3	26		T137	4		T130	5
values[9]	1332	1			T3	14		T9	1		T12	1
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	803	1			T5	22		T7	7		T24	1
values[1]	580	1			T16	1		T202	1		T220	21
values[2]	715	1			T5	23		T9	1		T12	1
values[3]	2962	1			T4	2		T6	9		T7	4
values[4]	840	1			T3	24		T13	3		T28	37
values[5]	728	1			T129	28		T38	2		T132	8
values[6]	826	1			T136	14		T128	1		T138	6
values[7]	741	1			T3	26		T137	4		T130	5
values[8]	961	1			T3	14		T9	1		T12	1
values[9]	246	1			T289	1		T135	10		T150	24
minimum	16578	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	11		T7	3		T131	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	2		T24	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	1		T202	1		T247	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T220	12		T229	3		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	14		T29	6		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T12	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T4	2		T6	1		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T31	10		T134	10		T215	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	12		T28	17		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	3		T128	1		T131	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T132	8		T189	5		T252	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T129	14		T38	2		T40	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T136	1		T187	3		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T128	1		T138	6		T131	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	14		T137	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	1		T140	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T37	2		T136	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	6		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T32	1		T270	12		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T289	1		T135	1		T150	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16428	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T315	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	11		T7	2		T263	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	1		T129	8		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T247	11		T292	15		T254	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T220	9		T229	1		T215	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	9		T29	1		T36	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	14		T160	2		T275	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T6	8		T7	2		T29	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	7		T134	11		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	12		T28	20		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T293	1		T204	10		T173	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T189	1		T252	12		T256	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T129	14		T40	7		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T136	13		T187	6		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T42	1		T160	11		T256	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	12		T137	3		T130	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	9		T135	12		T284	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T136	10		T169	12		T247	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	8		T137	12		T132	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T32	9		T316	8		T245	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T135	9		T150	11		T161	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T315	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T181	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T7	3		T221	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T271	20		T317	3		T318	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	11		T131	13		T263	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	2		T24	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	1		T202	1		T247	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T220	12		T215	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T29	6		T36	13		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	1		T12	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	14		T220	12		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T31	10		T134	10		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T4	2		T6	1		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	3		T128	1		T131	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	12		T37	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T129	14		T38	2		T40	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	1		T187	3		T42	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T128	1		T138	6		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	14		T137	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T131	20		T39	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T37	2		T136	1		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T3	6		T9	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T7	2		T221	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T271	22		T317	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	11		T263	1		T255	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	1		T129	8		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T247	11		T292	15		T254	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T220	9		T215	11		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T29	1		T36	14		T279	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T140	14		T229	1		T275	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	9		T220	17		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	7		T134	11		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T6	8		T7	2		T28	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T215	5		T263	6		T173	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	12		T37	1		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T129	14		T40	7		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T136	13		T187	6		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	1		T189	1		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	12		T137	3		T130	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T135	12		T257	14		T262	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T136	10		T169	12		T247	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	8		T137	12		T132	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	12		T7	3		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	2		T24	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T16	1		T202	1		T247	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T220	10		T229	3		T215	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	10		T29	2		T36	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T12	1		T140	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T4	2		T6	9		T7	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T31	11		T134	12		T215	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	13		T28	21		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	2		T128	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	1		T189	4		T252	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T129	15		T38	2		T40	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	14		T187	7		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T128	1		T138	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	13		T137	4		T130	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	1		T140	10		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T37	1		T136	11		T169	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	9		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T32	10		T270	1		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T289	1		T135	10		T150	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16568	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T315	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	10		T7	2		T131	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	1		T129	9		T258	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T247	10		T254	13		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T220	11		T229	1		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	13		T29	5		T36	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T275	13		T264	8		T256	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T10	14		T25	18		T29	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	6		T134	9		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	11		T28	16		T262	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T131	14		T266	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T132	7		T189	2		T252	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T129	13		T40	4		T261	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T187	2		T42	2		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	5		T131	19		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	13		T139	3		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T284	3		T257	10		T262	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T37	1		T247	14		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	5		T138	17		T132	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T270	11		T290	14		T291	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T150	12		T258	8		T296	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T315	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T181	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T7	3		T221	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T271	23		T317	2		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	12		T131	1		T263	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	2		T24	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T16	1		T202	1		T247	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T220	10		T215	12		T142	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	2		T36	17		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	1		T12	1		T140	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	10		T220	18		T189	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T31	11		T134	12		T160	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T4	2		T6	9		T7	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	2		T128	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	13		T37	2		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T129	15		T38	2		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T136	14		T187	7		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T128	1		T138	1		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	13		T137	4		T130	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T131	1		T39	1		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T37	1		T136	11		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T3	9		T9	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T181	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T7	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T271	19		T317	2		T318	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	10		T131	12		T263	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T16	1		T129	9		T258	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T247	10		T254	13		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T220	11		T215	9		T319	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	5		T36	10		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T229	1		T275	13		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	13		T220	11		T265	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	6		T134	9		T264	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T10	14		T25	18		T28	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T131	14		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	11		T132	7		T189	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T129	13		T40	4		T266	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T187	2		T42	2		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T138	5		T42	1		T261	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	13		T139	3		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T131	19		T257	10		T262	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T37	1		T247	14		T142	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	5		T138	17		T132	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2